+
+
+
+
+
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/eth/eth_udp.html" "b/doc/\346\250\241\345\235\227/eth/eth_udp.html" new file mode 100644 index 0000000..c3af5f6 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/eth/eth_udp.html" @@ -0,0 +1,1560 @@ + + + + + +TerosHDL
+
+
+
+
+
+
Entity: adjust_color
-
+
- File: adjust_color.v +
Diagram
+Ports
+| Port name | +Direction | +Type | +Description | +
|---|---|---|---|
| clk | +input | ++ | 时钟 | +
| resetn | +input | ++ | 复位 | +
| h_s_data | +input | +signed [8:0] | +色相调整值 | +
| s_s_data | +input | +signed [8:0] | +饱和度调整值 | +
| v_s_data | +input | +signed [8:0] | +明度调整值 | +
| pixel_s_data | +input | +[23:0] | +输入像素点-RGB | +
| pixel_s_valid | +input | ++ | 输入有效信号 | +
| res_m_data | +output | +[23:0] | +输出像素点 | +
| res_m_valid | +output | ++ | 输出有效信号 | +
Signals
+| Name | +Type | +Description | +
|---|---|---|
| raw_h_data | +wire [7:0] | ++ |
| raw_s_data | +wire [7:0] | ++ |
| raw_v_data | +wire [7:0] | ++ |
| modified_h_data | +wire [7:0] | ++ |
| modified_s_data | +wire [7:0] | ++ |
| modified_v_data | +wire [7:0] | ++ |
| raw_hsv_valid | +wire | ++ |
| modified_hsv_valid | +wire | ++ |
Instantiations
-
+
- convert_rgb2hsv_inst: convert_rgb2hsv +
-
+
- hsv_modify_inst: hsv_modify +
-
+
- convert_hsv2rgb_inst: convert_hsv2rgb +
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/eth/eth_udp.html" "b/doc/\346\250\241\345\235\227/eth/eth_udp.html" new file mode 100644 index 0000000..c3af5f6 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/eth/eth_udp.html" @@ -0,0 +1,1560 @@ + + + + + +
+
+
+
+
+
+
+
+
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/hdmi/hdmi_in_top.html" "b/doc/\346\250\241\345\235\227/hdmi/hdmi_in_top.html" new file mode 100644 index 0000000..ff4c491 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/hdmi/hdmi_in_top.html" @@ -0,0 +1,1376 @@ + + + + + +TerosHDL
+
+
+
+
+
+
Entity: eth_udp
-
+
- File: eth_udp.v +
Diagram
+Generics
+| Generic name | +Type | +Value | +Description | +
|---|---|---|---|
| BOARD_MAC | ++ | 48'h00_11_22_33_44_55 | ++ |
| BOARD_IP | ++ | {8'd192, 8'd168, 8'd10, 8'd10} | ++ |
| BOARD_PORT | ++ | 16'd1234 | ++ |
| DES_MAC | ++ | 48'hff_ff_ff_ff_ff_ff | ++ |
| DES_IP | ++ | {8'd192, 8'd168, 8'd10, 8'd102} | ++ |
| DES_PORT | ++ | 16'd1234 | ++ |
| IDELAY_VALUE | ++ | 0 | ++ |
Ports
+| Port name | +Direction | +Type | +Description | +
|---|---|---|---|
| clk | +input | ++ | 系统时钟 | +
| resetn | +input | ++ | 系统复位信号，低电平有效 | +
| eth_rxc | +input | ++ | RGMII接收数据时钟 | +
| eth_rx_ctl | +input | ++ | RGMII输入数据有效信号 | +
| eth_rxd | +input | +[3:0] | +RGMII输入数据 | +
| eth_txc | +output | ++ | RGMII发送数据时钟 | +
| eth_tx_ctl | +output | ++ | RGMII输出数据有效信号 | +
| eth_txd | +output | +[3:0] | +RGMII输出数据 | +
| gmii_clk | +output | ++ | GMII接收时钟 | +
| udp_rx_pkt_start | +output | ++ | 以太网单包数据接收开始信号 | +
| udp_rx_pkt_done | +output | ++ | 以太网单包数据接收完成信号 | +
| udp_rx_pkt_en | +output | ++ | 以太网接收的数据使能信号 | +
| udp_rx_pkt_data | +output | +[ 7 : 0] | +以太网接收的数据 | +
| udp_rx_pkt_dest_port | +output | +[15 : 0] | +以太网接收目的地端口 | +
| udp_rx_pkt_byte_num | +output | +[15 : 0] | +以太网接收的有效字节数 单位:byte | +
| udp_rx_m_data_tdata | +output | +[ 7:0] | +待接受数据 数据 | +
| udp_rx_m_data_tlast | +output | ++ | 待接受数据 结束传输 | +
| udp_rx_m_data_tvalid | +output | ++ | 待接受数据 有效信号 | +
| udp_rx_m_data_tready | +input | ++ | 待接受数据 准备信号 | +
| udp_rx_m_data_tsize | +output | +[15:0] | +待接受数据 数据量 | +
| udp_rx_m_cached_pkt_num | +output | +[ 5:0] | +待接受数据 已缓存数据包数量 | +
| udp_tx_s_data | +input | +[ 7:0] | +待发送数据 数据 | +
| udp_tx_s_valid | +input | ++ | 待发送数据 有效信号 | +
| udp_tx_s_start | +input | ++ | 待发送数据 开始传输 | +
| udp_tx_s_tsize | +input | +[15:0] | +待发送数据 数据量 | +
| udp_tx_s_last | +input | ++ | 待发送数据 结束传输 | +
Signals
+| Name | +Type | +Description | +
|---|---|---|
| gmii_rxd_valid | +wire | ++ |
| gmii_rxd_data | +wire [ 7:0] | ++ |
| gmii_txd_valid | +wire | ++ |
| gmii_txd_data | +wire [ 7:0] | ++ |
| arp_gmii_tx_en | +wire | ++ |
| arp_gmii_txd | +wire [ 7:0] | ++ |
| arp_rx_done | +wire | ++ |
| arp_rx_type | +wire | ++ |
| src_mac | +wire [47:0] | ++ |
| src_ip | +wire [31:0] | ++ |
| arp_tx_en | +wire | ++ |
| arp_tx_type | +wire | ++ |
| des_mac | +wire [47:0] | ++ |
| des_ip | +wire [31:0] | ++ |
| arp_tx_done | +wire | ++ |
| icmp_gmii_tx_en | +wire | ++ |
| icmp_gmii_txd | +wire [ 7:0] | ++ |
| icmp_rec_pkt_done | +wire | ++ |
| icmp_rec_en | +wire | ++ |
| icmp_rec_data | +wire [ 7:0] | ++ |
| icmp_rec_byte_num | +wire [15:0] | ++ |
| icmp_tx_byte_num | +wire [15:0] | ++ |
| icmp_tx_done | +wire | ++ |
| icmp_tx_req | +wire | ++ |
| icmp_tx_data | +wire [ 7:0] | ++ |
| icmp_tx_start_en | +wire | ++ |
| udp_gmii_tx_en | +wire | ++ |
| udp_gmii_txd | +wire [ 7:0] | ++ |
| tx_byte_num | +wire [15:0] | ++ |
| udp_tx_done | +wire | ++ |
| udp_tx_req | +wire | ++ |
| udp_tx_data | +wire [ 7:0] | ++ |
| tx_start_en | +wire | ++ |
| rec_data | +wire [ 7:0] | ++ |
| rec_en | +wire | ++ |
| tx_req | +wire | ++ |
| tx_data | +wire [ 7:0] | ++ |
| default_tx_buffer_wr_en | +reg | ++ |
| default_tx_buffer_start | +reg | ++ |
| default_tx_buffer_done | +reg | ++ |
Processes
-
+
- unnamed: ( @(*) ) +
Type: always
-
+
- unnamed: ( @(*) ) +
Type: always
-
+
- unnamed: ( @(*) ) +
Type: always
Instantiations
-
+
- u_gmii_to_rgmii: gmii_to_rgmii +
-
+
- u_arp: arp +
-
+
- u_icmp: icmp +
-
+
- u_udp: udp +
-
+
- icmp_async_fifo_2048x8b: async_fifo_2048x8 +
-
+
- udp_receive_buffer_inst: udp_receive_buffer +
-
+
- u_udp_transmit_buffer: udp_transmit_buffer +
-
+
- u_eth_ctrl: eth_ctrl +
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/hdmi/hdmi_in_top.html" "b/doc/\346\250\241\345\235\227/hdmi/hdmi_in_top.html" new file mode 100644 index 0000000..ff4c491 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/hdmi/hdmi_in_top.html" @@ -0,0 +1,1376 @@ + + + + + +
+
+
+
+
+
+
+
+
+
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/hdmi/sync_vg.html" "b/doc/\346\250\241\345\235\227/hdmi/sync_vg.html" new file mode 100644 index 0000000..1d1737f --- /dev/null +++ "b/doc/\346\250\241\345\235\227/hdmi/sync_vg.html" @@ -0,0 +1,1417 @@ + + + + + +TerosHDL
+
+
+
+
+
+
Entity: hdmi_in_top
-
+
- File: hdmi_in_top.v +
Diagram
+Generics
+| Generic name | +Type | +Value | +Description | +
|---|---|---|---|
| IMAGE_W | ++ | 1280 | ++ |
| IMAGE_H | ++ | 720 | ++ |
| IMAGE_SIZE | ++ | 11 | ++ |
Ports
+| Port name | +Direction | +Type | +Description | +
|---|---|---|---|
| clk | +input | ++ | 时钟 | +
| rst | +input | ++ | 复位 | +
| r_in | +input | +[7:0] | +像素点Red通道 | +
| g_in | +input | +[7:0] | +像素点Green通道 | +
| b_in | +input | +[7:0] | +像素点Blue通道 | +
| vs_in | +input | ++ | 垂直同步信号 | +
| hs_in | +input | ++ | 水平同步信号 | +
| de_in | +input | ++ | 数据有效信号 | +
| hdmi_data | +output | +[15:0] | +HDMI输出数据 | +
| hdmi_data_valid | +output | ++ | HDMI输出有效信号 | +
| hdmi_vs_out | +output | ++ | HDMI输出输出垂直同步 | +
Signals
+| Name | +Type | +Description | +
|---|---|---|
| r_in0 | +reg [7:0] | ++ |
| g_in0 | +reg [7:0] | ++ |
| b_in0 | +reg [7:0] | ++ |
| r_in1 | +reg [7:0] | ++ |
| g_in1 | +reg [7:0] | ++ |
| b_in1 | +reg [7:0] | ++ |
| r_in2 | +reg [7:0] | ++ |
| g_in2 | +reg [7:0] | ++ |
| b_in2 | +reg [7:0] | ++ |
| r_in3 | +reg [7:0] | ++ |
| g_in3 | +reg [7:0] | ++ |
| b_in3 | +reg [7:0] | ++ |
| vs_in0 | +reg | ++ |
| hs_in0 | +reg | ++ |
| de_in0 | +reg | ++ |
| vs_in1 | +reg | ++ |
| hs_in1 | +reg | ++ |
| de_in1 | +reg | ++ |
| vs_in2 | +reg | ++ |
| hs_in2 | +reg | ++ |
| de_in2 | +reg | ++ |
| hdmi_in_en | +reg | ++ |
| EXTRACT | +wire [1:0] | ++ |
| hs_cnt | +reg [1:0] | ++ |
| hdmi_data_valid0 | +reg | ++ |
| de_cnt | +reg [1:0] | ++ |
| cnt_hs0 | +reg [12:0] | ++ |
| cnt_hs1 | +reg [12:0] | ++ |
Processes
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/hdmi/sync_vg.html" "b/doc/\346\250\241\345\235\227/hdmi/sync_vg.html" new file mode 100644 index 0000000..1d1737f --- /dev/null +++ "b/doc/\346\250\241\345\235\227/hdmi/sync_vg.html" @@ -0,0 +1,1417 @@ + + + + + +
+
+
+
+
+
+
+
+
+
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/image_filiter/image_filiter.html" "b/doc/\346\250\241\345\235\227/image_filiter/image_filiter.html" new file mode 100644 index 0000000..86e8e46 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/image_filiter/image_filiter.html" @@ -0,0 +1,1259 @@ + + + + + + +TerosHDL
+
+
+
+
+
+
+
+ TerosHDL
+
+
+
+
+
+
+
+ TerosHDL
+
+
+
+
+
+
Entity: sync_vg
-
+
- File: sync_vg.v +
Diagram
+Generics
+| Generic name | +Type | +Value | +Description | +
|---|---|---|---|
| X_BITS | ++ | 12 | ++ |
| Y_BITS | ++ | 12 | ++ |
| HDMI_1080P_EN | ++ | 0 | ++ |
| V_TOTAL | ++ | 12'd1125 | ++ |
| V_FP | ++ | 12'd4 | ++ |
| V_BP | ++ | 12'd36 | ++ |
| V_SYNC | ++ | 12'd5 | ++ |
| V_ACT | ++ | 12'd1080 | ++ |
| H_TOTAL | ++ | 12'd2200 | ++ |
| H_FP | ++ | 12'd88 | ++ |
| H_BP | ++ | 12'd148 | ++ |
| H_SYNC | ++ | 12'd44 | ++ |
| H_ACT | ++ | 12'd1920 | ++ |
| HV_OFFSET | ++ | 12'd0 | ++ |
Ports
+| Port name | +Direction | +Type | +Description | +
|---|---|---|---|
| clk | +input | ++ | 时钟 | +
| rst | +input | ++ | 复位 | +
| rd_mode | +input | +[1:0] | +读取模式 | +
| ddr_rd_en | +output | ++ | 读取请求 | +
| ddr_image_data | +input | +[15:0] | +读取数据 | +
| vs_out | +output | ++ | 垂直同步 | +
| hs_out | +output | ++ | 水平同步 | +
| de_re | +output | ++ | 数据有效 | +
| hdmi_image_data | +output | +[15:0] | +输出像素点RGB数据 | +
| pos_x | +output | +[11:0] | +像素点对应的X坐标 | +
| pos_y | +output | +[11:0] | +像素点对应的Y坐标 | +
Signals
+| Name | +Type | +Description | +
|---|---|---|
| h_count | +reg [X_BITS-1:0] | ++ |
| v_count | +reg [Y_BITS-1:0] | ++ |
| vs_out0 | +reg | ++ |
| vs_out1 | +reg | ++ |
| vs_out2 | +reg | ++ |
| vs_out3 | +reg | ++ |
| hs_out0 | +reg | ++ |
| hs_out1 | +reg | ++ |
| hs_out2 | +reg | ++ |
| hs_out3 | +reg | ++ |
| de_re0 | +reg | ++ |
| de_re1 | +reg | ++ |
| zero_valid0 | +reg | ++ |
| zero_valid1 | +reg | ++ |
| pixel_show_en0 | +reg | ++ |
| pixel_show_en1 | +reg | ++ |
| rd_mode0 | +reg [1:0] | ++ |
| hdmi_image_data0 | +reg [15:0] | ++ |
| hdmi_image_data1 | +reg [15:0] | ++ |
| de_re2 | +reg | ++ |
| de_re3 | +reg | ++ |
Processes
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/image_filiter/image_filiter.html" "b/doc/\346\250\241\345\235\227/image_filiter/image_filiter.html" new file mode 100644 index 0000000..86e8e46 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/image_filiter/image_filiter.html" @@ -0,0 +1,1259 @@ + + + + + + +
+
+
+
+
+
+
+
+
+
+
Entity: image_filiter
-
+
- File: image_filiter.v +
Diagram
+Generics
+| Generic name | +Type | +Value | +Description | +
|---|---|---|---|
| IMAGE_WIDTH | +reg [10:0] | +1280 | ++ |
| IMAGE_HEIGHT | +reg [10:0] | +360 | ++ |
| PIXEL_DATA_WIDTH | +integer | +16 | ++ |
| R_DATA_WIDTH | +integer | +5 | ++ |
| G_DATA_WIDTH | +integer | +6 | ++ |
| B_DATA_WIDTH | +integer | +5 | ++ |
| TH | +integer | +5 | ++ |
Ports
+| Port name | +Direction | +Type | +Description | +
|---|---|---|---|
| clk | +input | ++ | 时钟 | +
| resetn | +input | ++ | 复位 | +
| rst_busy | +output | ++ | FIFO初始化忙信号 | +
| mode | +input | +[2:0] | +滤波模式 | +
| s_pixel_data | +input | +[PIXEL_DATA_WIDTH-1:0] | +输入像素点 | +
| s_pixel_valid | +input | ++ | 输入像素点有效信号 | +
| m_filtered_data | +output | +[PIXEL_DATA_WIDTH-1:0] | +输出像素点 | +
| m_filtered_valid | +output | ++ | 输出像素点有效信号 | +
Signals
+| Name | +Type | +Description | +
|---|---|---|
| multiline_pixel_data | +wire [3*PIXEL_DATA_WIDTH-1:0] | ++ |
| pixel_valid | +wire | ++ |
| matrix_data | +wire [9*PIXEL_DATA_WIDTH-1:0] | +3x3像素点矩阵 | +
| matrix_valid | +wire | +3x3像素点矩阵有效信号 | +
Instantiations
-
+
- multiline_buffer_inst: multiline_buffer +
-
+
- vector_to_matrix_inst: vector_to_matrix +
Description
+ 输入三行数据流，输出3x3矩阵
-
+
- hybrid_filter_inst: hybrid_filter +
Description
+ 对矩阵滤波
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Entity: multiline_buffer
-
+
- File: multiline_buffer.v +
Diagram
+Generics
+| Generic name | +Type | +Value | +Description | +
|---|---|---|---|
| IMAGE_WIDTH | +reg [10:0] | +1920 | +图像宽度 | +
| IMAGE_HEIGHT | +reg [10:0] | +1080 | +图像高度 | +
| PIXEL_DATA_WIDTH | +integer | +16 | +像素宽度 | +
| LINES_NUM | +integer | +3 | +行数 | +
Ports
+| Port name | +Direction | +Type | +Description | +
|---|---|---|---|
| clk | +input | ++ | 时钟 | +
| resetn | +input | ++ | 复位 | +
| rst_busy | +output | ++ | FIFO复位忙信号 | +
| s_pixel_data | +input | +[PIXEL_DATA_WIDTH-1:0] | +输入数据 | +
| s_pixel_valid | +input | ++ | 输入有效信号 | +
| m_multiline_pixel_data | +output | +[(LINES_NUM)*PIXEL_DATA_WIDTH-1:0] | +输出列向量 | +
| m_pixel_valid | +output | ++ | 输出有效信号 | +
Signals
+| Name | +Type | +Description | +
|---|---|---|
| hor_cnt | +reg [ 10:0] | ++ |
| ver_cnt | +reg [ 10:0] | ++ |
| tail_ver_cnt | +reg [ 5:0] | ++ |
| tail_hor_cnt | +reg [ 10:0] | ++ |
| srst | +reg | ++ |
| din | +reg [(LINES_NUM-1)*FifoWidth-1:0] | ++ |
| dout | +wire [(LINES_NUM-1)*FifoWidth-1:0] | ++ |
| rd_en | +reg [ LINES_NUM-2:0] | ++ |
| wr_en | +reg [ LINES_NUM-2:0] | ++ |
| full | +wire [ LINES_NUM-2:0] | ++ |
| empty | +wire [ LINES_NUM-2:0] | ++ |
| rst_s1 | +reg | ++ |
Constants
+| Name | +Type | +Value | +Description | +
|---|---|---|---|
| FifoWidth | ++ | 24 | ++ |
Processes
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk or negedge resetn) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(*) ) +
Type: always
+
+
+
+
+
+
+
+
+
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/others/param_manager.html" "b/doc/\346\250\241\345\235\227/others/param_manager.html" new file mode 100644 index 0000000..4e749fb --- /dev/null +++ "b/doc/\346\250\241\345\235\227/others/param_manager.html" @@ -0,0 +1,1741 @@ + + + + + +TerosHDL
+
+
+
+
+
+
Entity: param_cell_unsigned
-
+
- File: param_cell_unsigned.v +
Diagram
+Generics
+| Generic name | +Type | +Value | +Description | +
|---|---|---|---|
| CLK_FREQ | +integer | +50_000000 | ++ |
| PARAM_WIDTH | +integer | +3 | ++ |
| PRESSED_TRIG_CYCLE_MS | +integer | +100 | ++ |
| DEFAULT_VALUE | +integer | +0 | ++ |
| RANGE_MIN | +integer | +0 | ++ |
| RANGE_MAX | +integer | +1 | ++ |
Ports
+| Port name | +Direction | +Type | +Description | +
|---|---|---|---|
| clk | +input | ++ | + |
| resetn | +input | ++ | + |
| clk_ms | +input | ++ | + |
| restore | +input | ++ | + |
| selected | +input | ++ | + |
| load_valid | +input | ++ | + |
| load_data | +input | +[PARAM_WIDTH-1:0] | ++ |
| akey_up | +input | ++ | + |
| akey_down | +input | ++ | + |
| value | +output | +[PARAM_WIDTH-1:0] | ++ |
Signals
+| Name | +Type | +Description | +
|---|---|---|
| pressed_up | +wire | ++ |
| pressed_down | +wire | ++ |
| changed_up | +wire | ++ |
| changed_down | +wire | ++ |
| pluse | +reg | ++ |
| cnt | +reg [11:0] | ++ |
| clk_ms_ff0 | +reg | ++ |
| clk_ms_ff1 | +reg | ++ |
| pluse_ms | +reg | ++ |
Processes
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
Instantiations
-
+
- key_debounce_inst1: key_debounce +
-
+
- key_debounce_inst2: key_debounce +
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/others/param_manager.html" "b/doc/\346\250\241\345\235\227/others/param_manager.html" new file mode 100644 index 0000000..4e749fb --- /dev/null +++ "b/doc/\346\250\241\345\235\227/others/param_manager.html" @@ -0,0 +1,1741 @@ + + + + + +
+
+
+
+
+
+
+
+
+
+
+
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/ov5640/ov5640.html" "b/doc/\346\250\241\345\235\227/ov5640/ov5640.html" new file mode 100644 index 0000000..4713d6d --- /dev/null +++ "b/doc/\346\250\241\345\235\227/ov5640/ov5640.html" @@ -0,0 +1,1438 @@ + + + + + +TerosHDL
+
+
+
+
+
+
Entity: param_manager
-
+
- File: param_manager.v +
Diagram
+Generics
+| Generic name | +Type | +Value | +Description | +
|---|---|---|---|
| CLK_FREQ | +integer | +50_000000 | ++ |
Ports
+| Port name | +Direction | +Type | +Description | +
|---|---|---|---|
| clk | +input | ++ | 时钟 | +
| resetn | +input | ++ | 复位 | +
| akey_left | +input | ++ | 按键-左 | +
| akey_right | +input | ++ | 按键-右 | +
| akey_up | +input | ++ | 按键-上 | +
| akey_down | +input | ++ | 按键-下 | +
| akey_restore | +input | ++ | 按键—恢复 | +
| mem | +input | +[199:0] | +带加载参数 | +
| mem_flags | +input | +[ 24:0] | +参数变化标志 | +
| index | +output | +[3:0] | +参数序号 | +
| filiter1_mode | +output | +[2:0] | +滤波器1 模式 | +
| filiter2_mode | +output | +[2:0] | +滤波器2 模式 | +
| zoom | +output | +[9:0] | +双线性插值缩放系数 | +
| rotate | +output | +[7:0] | +旋转系数 | +
| osd_startX | +output | +[10:0] | +OSD起始X坐标 | +
| os_startY | +output | +[10:0] | +OSD起始Y坐标 | +
| osd_char_width | +output | +[10:0] | +OSD字符宽度 | +
| osd_char_height | +output | +[10:0] | +文本行距 | +
| rotate_A | +output | +[9:0] | +缩放系数2 | +
| offsetX | +output | +wire signed [11:0] | +图像偏移X | +
| offsetY | +output | +wire signed [11:0] | +图像偏移Y | +
| modify_H | +output | +wire signed [8:0] | +色相偏移 | +
| modify_S | +output | +wire signed [8:0] | +饱和度偏移 | +
| modify_V | +output | +wire signed [8:0] | +亮度偏移 | +
Signals
+| Name | +Type | +Description | +
|---|---|---|
| clk_ms | +reg | ++ |
| ms_cnt | +reg [29:0] | ++ |
| pressed_left | +wire | ++ |
| pressed_right | +wire | ++ |
| pressed_restore | +wire | ++ |
| changed_left | +wire | ++ |
| changed_right | +wire | ++ |
| changed_restore | +wire | ++ |
| selected | +reg [ParamNum-1:0] | ++ |
| filiter1_mode_flags_ff0 | +reg | ++ |
| filiter1_mode_flags_ff1 | +reg | ++ |
| filiter1_mode_load | +reg | ++ |
| filiter2_mode_flags_ff0 | +reg | ++ |
| filiter2_mode_flags_ff1 | +reg | ++ |
| filiter2_mode_load | +reg | ++ |
| zoom_flags_ff0 | +reg | ++ |
| zoom_flags_ff1 | +reg | ++ |
| zoom_flags_ff2 | +reg | ++ |
| zoom_flags_ff3 | +reg | ++ |
| zoom_load | +reg | ++ |
| rotate_flags_ff0 | +reg | ++ |
| rotate_flags_ff1 | +reg | ++ |
| rotate_load | +reg | ++ |
| osd_startX_flags_ff0 | +reg | ++ |
| osd_startX_flags_ff1 | +reg | ++ |
| osd_startX_flags_ff2 | +reg | ++ |
| osd_startX_flags_ff3 | +reg | ++ |
| osd_startX_load | +reg | ++ |
| osd_startY_flags_ff0 | +reg | ++ |
| osd_startY_flags_ff1 | +reg | ++ |
| osd_startY_flags_ff2 | +reg | ++ |
| osd_startY_flags_ff3 | +reg | ++ |
| osd_startY_load | +reg | ++ |
| osd_char_width_flags_ff0 | +reg | ++ |
| osd_char_width_flags_ff1 | +reg | ++ |
| osd_char_width_flags_ff2 | +reg | ++ |
| osd_char_width_flags_ff3 | +reg | ++ |
| osd_char_width_load | +reg | ++ |
| osd_char_height_flags_ff0 | +reg | ++ |
| osd_char_height_flags_ff1 | +reg | ++ |
| osd_char_height_flags_ff2 | +reg | ++ |
| osd_char_height_flags_ff3 | +reg | ++ |
| osd_char_height_load | +reg | ++ |
| rotate_A_flags_ff0 | +reg | ++ |
| rotate_A_flags_ff1 | +reg | ++ |
| rotate_A_flags_ff2 | +reg | ++ |
| rotate_A_flags_ff3 | +reg | ++ |
| rotate_A_load | +reg | ++ |
| offsetX_flags_ff0 | +reg | ++ |
| offsetX_flags_ff1 | +reg | ++ |
| offsetX_flags_ff2 | +reg | ++ |
| offsetX_flags_ff3 | +reg | ++ |
| offsetX_load | +reg | ++ |
| offsetY_flags_ff0 | +reg | ++ |
| offsetY_flags_ff1 | +reg | ++ |
| offsetY_flags_ff2 | +reg | ++ |
| offsetY_flags_ff3 | +reg | ++ |
| offsetY_load | +reg | ++ |
| modify_H_flags_ff0 | +reg | ++ |
| modify_H_flags_ff1 | +reg | ++ |
| modify_H_flags_ff2 | +reg | ++ |
| modify_H_flags_ff3 | +reg | ++ |
| modify_H_load | +reg | ++ |
| modify_S_flags_ff0 | +reg | ++ |
| modify_S_flags_ff1 | +reg | ++ |
| modify_S_flags_ff2 | +reg | ++ |
| modify_S_flags_ff3 | +reg | ++ |
| modify_S_load | +reg | ++ |
| modify_V_flags_ff0 | +reg | ++ |
| modify_V_flags_ff1 | +reg | ++ |
| modify_V_flags_ff2 | +reg | ++ |
| modify_V_flags_ff3 | +reg | ++ |
| modify_V_load | +reg | ++ |
Constants
+| Name | +Type | +Value | +Description | +
|---|---|---|---|
| ParamNum | ++ | 14 | ++ |
Processes
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
Description
+ 按键控制当前选择的参数序号
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
Instantiations
-
+
- key_debounce_key_left: key_debounce +
-
+
- key_debounce_key_right: key_debounce +
-
+
- key_debounce_key_restore: key_debounce +
-
+
- param_filiter1_mode: param_cell_unsigned_loop +
-
+
- param_filiter2_mode: param_cell_unsigned_loop +
-
+
- param_zoom: param_cell_unsigned +
-
+
- param_rotate: param_cell_unsigned_loop +
-
+
- param_osd_startX: param_cell_unsigned +
-
+
- param_osd_startY: param_cell_unsigned +
-
+
- param_osd_char_width: param_cell_unsigned +
-
+
- param_osd_char_height: param_cell_unsigned +
-
+
- param_rotate_A: param_cell_unsigned +
-
+
- param_offsetX: param_cell_signed +
-
+
- param_offsetY: param_cell_signed +
-
+
- param_modify_H: param_cell_signed_loop +
-
+
- param_modify_S: param_cell_signed +
-
+
- param_modify_V: param_cell_signed +
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/ov5640/ov5640.html" "b/doc/\346\250\241\345\235\227/ov5640/ov5640.html" new file mode 100644 index 0000000..4713d6d --- /dev/null +++ "b/doc/\346\250\241\345\235\227/ov5640/ov5640.html" @@ -0,0 +1,1438 @@ + + + + + +
+
+
+
+
+
+
+
+
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/rotate/rotate_image.html" "b/doc/\346\250\241\345\235\227/rotate/rotate_image.html" new file mode 100644 index 0000000..20f0915 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/rotate/rotate_image.html" @@ -0,0 +1,1804 @@ + + + + + + +TerosHDL
+
+
+
+
+
+
+
+ TerosHDL
+
+
+
+
+
+
Entity: ov5640
-
+
- File: ov5640.v +
Diagram
+Generics
+| Generic name | +Type | +Value | +Description | +
|---|---|---|---|
| IMAGE_SIZE | ++ | 11 | ++ |
| IMAGE_W | ++ | 1280 | ++ |
| IMAGE_H | ++ | 720 | ++ |
Ports
+| Port name | +Direction | +Type | +Description | +
|---|---|---|---|
| clk_50M | +input | ++ | 50M时钟 | +
| clk_25M | +input | ++ | 20M时钟 | +
| rst | +input | ++ | 复位信号 | +
| cmos1_scl | +inout | ++ | CMOS1 IIC_SCL信号 | +
| cmos1_sda | +inout | ++ | CMOS1 IIC_SDA信号 | +
| cmos1_vsync | +input | ++ | CMOS1 垂直同步信号 | +
| cmos1_href | +input | ++ | CMOS1 数据有效信号 | +
| cmos1_pclk | +input | ++ | CMOS1 像素时钟 | +
| cmos1_data | +input | +[7:0] | +CMOS1 数据 | +
| cmos1_reset | +output | ++ | CMOS1 复位 | +
| cmos2_scl | +inout | ++ | CMOS2 IIC_SCL信号 | +
| cmos2_sda | +inout | ++ | CMOS2 IIC_SDA信号 | +
| cmos2_vsync | +input | ++ | CMOS2 垂直同步信号 | +
| cmos2_href | +input | ++ | CMOS2 数据有效信号 | +
| cmos2_pclk | +input | ++ | CMOS2 像素时钟 | +
| cmos2_data | +input | +[7:0] | +CMOS2 数据 | +
| cmos2_reset | +output | ++ | CMOS2 复位 | +
| shift_w | +input | +[7:0] | +图像拼接移位 横向 | +
| shift_h | +input | +signed [7:0] | +图像拼接移位 纵向 | +
| wr_clk | +input | ++ | 数据输出 时钟 | +
| wr_rst | +input | ++ | 数据输出 复位 | +
| data_vs | +output | ++ | 数据输出 垂直同步信号 | +
| data_out_valid | +output | ++ | 视频输出 有效信号 | +
| data_out | +output | +[15:0] | +数据输出 数据 | +
Signals
+| Name | +Type | +Description | +
|---|---|---|
| cmos_init_done | +wire [1:0] | ++ |
| initial_en | +wire | ++ |
| cmos1_d_d0 | +reg [7:0] | ++ |
| cmos1_d_d1 | +reg [7:0] | ++ |
| cmos1_href_d0 | +reg | ++ |
| cmos1_href_d1 | +reg | ++ |
| cmos1_vsync_d0 | +reg | ++ |
| cmos1_vsync_d1 | +reg | ++ |
| cmos1_d_16bit | +wire [15:0] | ++ |
| cmos1_href_16bit | +wire | ++ |
| cmos2_d_16bit | +wire [15:0] | ++ |
| cmos2_href_16bit | +wire | ++ |
| cmos1_vsync0 | +wire | ++ |
| cmos2_vsync0 | +wire | ++ |
| pclk1 | +wire | ++ |
| pclk2 | +wire | ++ |
| cmos1_pclk_bufg | +wire | ++ |
| cmos1_pclk0 = ~cmos1_pclk | +wire | ++ |
| cmos2_d_d0 | +reg [7:0] | ++ |
| cmos2_d_d1 | +reg [7:0] | ++ |
| cmos2_href_d0 | +reg | ++ |
| cmos2_href_d1 | +reg | ++ |
| cmos2_vsync_d0 | +reg | ++ |
| cmos2_vsync_d1 | +reg | ++ |
Processes
-
+
- unnamed: ( @(posedge cmos1_pclk) ) +
Type: always
-
+
- unnamed: ( @(posedge cmos2_pclk) ) +
Type: always
Instantiations
-
+
- power_on_delay_inst: power_on_delay +
-
+
- coms1_reg_config: reg_config +
-
+
- coms2_reg_config: reg_config +
-
+
- cmos1_8_16bit: cmos_8_16bit +
-
+
- cmos2_8_16bit: cmos_8_16bit +
-
+
- u_mix_image: mix_image +
+ + + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/rotate/rotate_image.html" "b/doc/\346\250\241\345\235\227/rotate/rotate_image.html" new file mode 100644 index 0000000..20f0915 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/rotate/rotate_image.html" @@ -0,0 +1,1804 @@ + + + + + + +
+
+
+
+
+
+
+
+
+
+
+
+
+
Entity: rotate_image
-
+
- File: rotate_image.v +
Diagram
+Generics
+| Generic name | +Type | +Value | +Description | +
|---|---|---|---|
| IMAGE_SIZE | ++ | 11 | ++ |
| MIN_NUM | ++ | 1280 | ++ |
| IMAGE_W | ++ | 1280 | ++ |
| IMAGE_H | ++ | 720 | ++ |
Ports
+| Port name | +Direction | +Type | +Description | +
|---|---|---|---|
| clk | +input | ++ | 时钟 | +
| rst | +input | ++ | 复位 | +
| rotate_angle | +input | +[7:0] | +旋转角度 | +
| rotate_amplitude | +input | +[9:0] | +幅值 | +
| offsetX | +input | +wire signed [11:0] | +位移X | +
| offsetY | +input | +wire signed [11:0] | +位移Y | +
| rotate_en | +input | ++ | 使能 | +
| ddr_data_in_valid | +input | ++ | 读取数据-有效 | +
| ddr_data_in | +input | +[15:0] | +读取数据-数据 | +
| rd_ddr_addr_valid | +output | ++ | 读取地址-有效 | +
| rd_ddr_addr | +output | +[32-1:0] | +读取地址-数据 | +
| data_out_valid | +output | ++ | 输出数据-有效 | +
| data_out | +output | +[15:0] | +输出数据-数据 | +
Signals
+| Name | +Type | +Description | +
|---|---|---|
| rotate_sta | +reg [ 2:0] | ++ |
| rd_addr | +reg [ 7:0] | ++ |
| douta | +wire [17:0] | ++ |
| cos_data | +wire [8:0] | ++ |
| sin_data | +wire [8:0] | ++ |
| cos_data_multed | +wire [19:0] | ++ |
| sin_data_multed | +wire [19:0] | ++ |
| cos_data0 | +wire [12:0] | ++ |
| sin_data0 | +wire [12:0] | ++ |
| image_w_add_addr | +reg signed [IMAGE_SIZE+14-1:0] | ++ |
| image_h_add_addr | +reg signed [IMAGE_SIZE+14-1:0] | ++ |
| signed_zoom | +wire [10:0] | ++ |
| offsetX_ff | +reg signed [11:0] | ++ |
| offsetY_ff | +reg signed [11:0] | ++ |
| centerX | +reg signed [11:0] | ++ |
| centerY | +reg signed [11:0] | ++ |
| cnt_w | +reg signed [IMAGE_SIZE-1:0] | ++ |
| cnt_h | +reg signed [IMAGE_SIZE-1:0] | ++ |
| wr_count | +wire [11:0] | ++ |
| addr_fifo_empty | +wire | ++ |
| mult_p0[3:0] | +wire [IMAGE_SIZE+13-1:0] | ++ |
| w_mult_add | +reg signed [IMAGE_SIZE+14-1:0] | ++ |
| h_mult_add | +reg signed [IMAGE_SIZE+14-1:0] | ++ |
| image_w_valid0 | +reg [5:0] | ++ |
| image_w_valid | +wire | ++ |
| image_w_add0 | +reg [IMAGE_SIZE+15-1:0] | ++ |
| image_h_add0 | +reg [IMAGE_SIZE+15-1:0] | ++ |
| image_w_blank_valid | +reg | ++ |
| image_h_blank_valid | +reg | ++ |
| image_blank_valid | +reg | ++ |
| rd_ddr_addr_valid1 | +reg | ++ |
| rd_ddr_add | +wire | ++ |
| image_w_add1 | +reg [IMAGE_SIZE+4-1:0] | ++ |
| image_w_add2 | +reg [IMAGE_SIZE+4-1:0] | ++ |
| image_h_add1 | +reg [IMAGE_SIZE+4-1:0] | ++ |
| image_h_add2 | +reg [IMAGE_SIZE+4-1:0] | ++ |
| din | +wire [3:0] | ++ |
| dout | +wire [3:0] | ++ |
| wr_en | +wire | ++ |
| empty | +wire | ++ |
| full | +wire | ++ |
| addr_fifo_rd_en | +wire | ++ |
| addr_fifo_valid | +reg | ++ |
| ddr_data_in_valid0 | +reg | ++ |
| ddr_data_in0 | +reg [15:0] | ++ |
| image_data | +wire [15:0] | ++ |
| data_empty | +wire | ++ |
| data_rd_en | +wire | ++ |
| fifo_data_valid | +reg | ++ |
| rd_sta | +reg [2:0] | ++ |
| rd_sta_s2 | +reg | ++ |
| fifo_blank_valid = dout[0] | +wire | ++ |
| data_out2 | +reg [15:0] | ++ |
| data_out_valid0 | +wire | ++ |
| data_out_valid1 | +reg | ++ |
| data_out_valid2 | +reg | ++ |
| data_blank_out_valid | +reg | ++ |
| cnt_num | +reg [15:0] | ++ |
Constants
+| Name | +Type | +Value | +Description | +
|---|---|---|---|
| IDLE | ++ | 3'b001 | ++ |
| WAIT | ++ | 3'b010 | ++ |
| CNT | ++ | 3'b100 | ++ |
| S0 | ++ | 3'b001 | ++ |
| S1 | ++ | 3'b010 | ++ |
| S2 | ++ | 3'b100 | ++ |
Processes
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
Instantiations
-
+
- u_rotate_rom: rotate_rom +
-
+
- u_rotate_mult_zoom0: rotate_mult0 +
-
+
- u_rotate_mult_zoom1: rotate_mult0 +
-
+
- u_rotate_mult0: rotate_mult0 +
-
+
- u_rotate_mult1: rotate_mult0 +
-
+
- u_rotate_mult2: rotate_mult0 +
-
+
- u_rotate_mult3: rotate_mult0 +
-
+
- u_store_addr: store_addr +
-
+
- u_store_image_data: store_image_data +
State machines
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + + \ No newline at end of file diff --git a/project/compile/cmr.db b/project/compile/cmr.db index ddbe5f4..c2aad20 100644 --- a/project/compile/cmr.db +++ b/project/compile/cmr.db @@ -413,9 +413,9 @@ RAM(GB)
- 0h:0m:25s
- 0h:0m:25s
- 0h:1m:10s
+ 0h:0m:26s
+ 0h:0m:26s
+ 0h:1m:13s
328
WINDOWS 10 x86_64
Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz
@@ -869,7 +869,7 @@
Verilog-0001: Analyzing file D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v
- Verilog-0002: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 23)] Analyzing module ov5640 (library work)
+ Verilog-0002: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 3)] Analyzing module ov5640 (library work)
Verilog-0001: Analyzing file D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/power_on_delay.v
@@ -4817,7 +4817,7 @@
CLK_FREQ = 32'b00000111011100110101100101000000
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 78)] Elaborating instance key_debounce_key_left
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 102)] Elaborating instance key_debounce_key_left
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/key_debounce.v(line number: 1)] Elaborating module key_debounce
@@ -4829,7 +4829,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 90)] Elaborating instance key_debounce_key_right
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 114)] Elaborating instance key_debounce_key_right
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/key_debounce.v(line number: 1)] Elaborating module key_debounce
@@ -4841,7 +4841,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 102)] Elaborating instance key_debounce_key_restore
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 126)] Elaborating instance key_debounce_key_restore
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/key_debounce.v(line number: 1)] Elaborating module key_debounce
@@ -4853,7 +4853,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 171)] Elaborating instance param_filiter1_mode
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 195)] Elaborating instance param_filiter1_mode
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned_loop.v(line number: 1)] Elaborating module param_cell_unsigned_loop
@@ -4892,7 +4892,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 203)] Elaborating instance param_filiter2_mode
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 227)] Elaborating instance param_filiter2_mode
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned_loop.v(line number: 1)] Elaborating module param_cell_unsigned_loop
@@ -4907,7 +4907,7 @@
RANGE_MAX = 32'b00000000000000000000000000000100
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 238)] Elaborating instance param_zoom
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 262)] Elaborating instance param_zoom
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned
@@ -4946,7 +4946,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 271)] Elaborating instance param_rotate
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 295)] Elaborating instance param_rotate
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned_loop.v(line number: 1)] Elaborating module param_cell_unsigned_loop
@@ -4985,7 +4985,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 308)] Elaborating instance param_osd_startX
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 332)] Elaborating instance param_osd_startX
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned
@@ -5024,7 +5024,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 344)] Elaborating instance param_osd_startY
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 368)] Elaborating instance param_osd_startY
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned
@@ -5063,7 +5063,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 380)] Elaborating instance param_osd_char_width
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 404)] Elaborating instance param_osd_char_width
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned
@@ -5102,7 +5102,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 417)] Elaborating instance param_osd_char_height
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 441)] Elaborating instance param_osd_char_height
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned
@@ -5141,7 +5141,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 453)] Elaborating instance param_rotate_A
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 477)] Elaborating instance param_rotate_A
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned
@@ -5156,7 +5156,7 @@
RANGE_MAX = 32'b00000000000000000000001111111111
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 489)] Elaborating instance param_offsetX
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 513)] Elaborating instance param_offsetX
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_signed.v(line number: 1)] Elaborating module param_cell_signed
@@ -5195,7 +5195,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 524)] Elaborating instance param_offsetY
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 548)] Elaborating instance param_offsetY
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_signed.v(line number: 1)] Elaborating module param_cell_signed
@@ -5234,7 +5234,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 561)] Elaborating instance param_modify_H
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 585)] Elaborating instance param_modify_H
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_signed_loop.v(line number: 1)] Elaborating module param_cell_signed_loop
@@ -5273,7 +5273,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 598)] Elaborating instance param_modify_S
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 622)] Elaborating instance param_modify_S
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_signed.v(line number: 1)] Elaborating module param_cell_signed
@@ -5312,7 +5312,7 @@
KEY_RELEASED_VALUE = 1'b1
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 635)] Elaborating instance param_modify_V
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 659)] Elaborating instance param_modify_V
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_signed.v(line number: 1)] Elaborating module param_cell_signed
@@ -5330,7 +5330,7 @@
Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 507)] Elaborating instance u_ov5640
- Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 23)] Elaborating module ov5640
+ Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 3)] Elaborating module ov5640
Module instance {multimedia_video_processor/u_ov5640} parameter value:
@@ -5339,13 +5339,13 @@
IMAGE_H = 32'b00000000000000000000001011010000
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 62)] Elaborating instance power_on_delay_inst
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 43)] Elaborating instance power_on_delay_inst
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/power_on_delay.v(line number: 22)] Elaborating module power_on_delay
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 71)] Elaborating instance coms1_reg_config
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 52)] Elaborating instance coms1_reg_config
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/reg_config.v(line number: 22)] Elaborating module reg_config
@@ -5363,25 +5363,25 @@
Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/reg_config.v(line number: 69)] Elaborating instance U_CLKBUFG_CLK_20K
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 83)] Elaborating instance coms2_reg_config
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 64)] Elaborating instance coms2_reg_config
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/reg_config.v(line number: 22)] Elaborating module reg_config
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 148)] Elaborating instance cmos1_8_16bit
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 129)] Elaborating instance cmos1_8_16bit
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/cmos_8_16bit.v(line number: 24)] Elaborating module cmos_8_16bit
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 161)] Elaborating instance cmos2_8_16bit
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 142)] Elaborating instance cmos2_8_16bit
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/cmos_8_16bit.v(line number: 24)] Elaborating module cmos_8_16bit
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 201)] Elaborating instance u_mix_image
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 182)] Elaborating instance u_mix_image
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/mix_image.v(line number: 23)] Elaborating module mix_image
@@ -6005,7 +6005,7 @@
TH = 32'b00000000000000000000000000000100
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 637)] Elaborating instance u_rotate_image
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 638)] Elaborating instance u_rotate_image
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 23)] Elaborating module rotate_image
@@ -6018,7 +6018,7 @@
IMAGE_H = 32'b00000000000000000000001011010000
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 99)] Elaborating instance u_rotate_rom
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 102)] Elaborating instance u_rotate_rom
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/rotate_rom/rotate_rom.v(line number: 16)] Elaborating module rotate_rom
@@ -6109,7 +6109,7 @@
Verilog-2023: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/rotate_rom/rtl/ipml_rom_v1_5_rotate_rom.v(line number: 69)] Give initial value 0 for the no drive pin wr_byte_en in module instance multimedia_video_processor/u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom.U_ipml_spram_rotate_rom
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 110)] Elaborating instance u_rotate_mult_zoom0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 113)] Elaborating instance u_rotate_mult_zoom0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0
@@ -6120,7 +6120,7 @@
WIDT_B = 32'b00000000000000000000000000001011
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 119)] Elaborating instance u_rotate_mult_zoom1
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 122)] Elaborating instance u_rotate_mult_zoom1
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0
@@ -6131,7 +6131,7 @@
WIDT_B = 32'b00000000000000000000000000001011
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 187)] Elaborating instance u_rotate_mult0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 190)] Elaborating instance u_rotate_mult0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0
@@ -6142,7 +6142,7 @@
WIDT_B = 32'b00000000000000000000000000001101
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 196)] Elaborating instance u_rotate_mult1
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 199)] Elaborating instance u_rotate_mult1
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0
@@ -6153,7 +6153,7 @@
WIDT_B = 32'b00000000000000000000000000001101
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 205)] Elaborating instance u_rotate_mult2
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 208)] Elaborating instance u_rotate_mult2
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0
@@ -6164,7 +6164,7 @@
WIDT_B = 32'b00000000000000000000000000001101
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 214)] Elaborating instance u_rotate_mult3
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 217)] Elaborating instance u_rotate_mult3
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0
@@ -6175,7 +6175,7 @@
WIDT_B = 32'b00000000000000000000000000001101
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 318)] Elaborating instance u_store_addr
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 321)] Elaborating instance u_store_addr
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/store_addr/store_addr.v(line number: 16)] Elaborating module store_addr
@@ -6357,7 +6357,7 @@
c_ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 358)] Elaborating instance u_store_image_data
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 361)] Elaborating instance u_store_image_data
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/store_image_data/store_image_data.v(line number: 16)] Elaborating module store_image_data
@@ -6488,7 +6488,7 @@
Verilog-2039: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v(line number: 317)] Repeat multiplier in concatenation evaluates to 0
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 685)] Elaborating instance u_zoom_image
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 687)] Elaborating instance u_zoom_image
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 23)] Elaborating module zoom_image_v1
@@ -6778,7 +6778,7 @@
Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 434)] Width mismatch between port rd_addr and signal bound to it for instantiated module zoom_ram
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 756)] Elaborating instance mult_fra0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 751)] Elaborating instance mult_fra0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_fra.v(line number: 23)] Elaborating module mult_fra0
@@ -6789,7 +6789,7 @@
WIDT_B = 32'b00000000000000000000000000001000
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 762)] Elaborating instance mult_fra1
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 757)] Elaborating instance mult_fra1
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_fra.v(line number: 23)] Elaborating module mult_fra0
@@ -6800,7 +6800,7 @@
WIDT_B = 32'b00000000000000000000000000001000
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 768)] Elaborating instance mult_fra0_0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 763)] Elaborating instance mult_fra0_0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_fra.v(line number: 23)] Elaborating module mult_fra0
@@ -6811,7 +6811,7 @@
WIDT_B = 32'b00000000000000000000000000001000
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 774)] Elaborating instance mult_fra1_0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 769)] Elaborating instance mult_fra1_0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_fra.v(line number: 23)] Elaborating module mult_fra0
@@ -6822,7 +6822,7 @@
WIDT_B = 32'b00000000000000000000000000001000
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 784)] Elaborating instance mult_image_r0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 779)] Elaborating instance mult_image_r0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6833,7 +6833,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 790)] Elaborating instance mult_image_r1
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 785)] Elaborating instance mult_image_r1
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6844,7 +6844,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 796)] Elaborating instance mult_image_g0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 791)] Elaborating instance mult_image_g0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6855,7 +6855,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 802)] Elaborating instance mult_image_g1
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 797)] Elaborating instance mult_image_g1
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6866,7 +6866,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 808)] Elaborating instance mult_image_b0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 803)] Elaborating instance mult_image_b0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6877,7 +6877,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 814)] Elaborating instance mult_image_b1
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 809)] Elaborating instance mult_image_b1
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6888,7 +6888,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 821)] Elaborating instance mult_image_r0_0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 816)] Elaborating instance mult_image_r0_0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6899,7 +6899,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 827)] Elaborating instance mult_image_r1_0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 822)] Elaborating instance mult_image_r1_0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6910,7 +6910,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 833)] Elaborating instance mult_image_g0_0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 828)] Elaborating instance mult_image_g0_0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6921,7 +6921,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 839)] Elaborating instance mult_image_g1_0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 834)] Elaborating instance mult_image_g1_0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6932,7 +6932,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 845)] Elaborating instance mult_image_b0_0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 840)] Elaborating instance mult_image_b0_0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6943,7 +6943,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 851)] Elaborating instance mult_image_b1_0
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 846)] Elaborating instance mult_image_b1_0
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip
@@ -6954,7 +6954,7 @@
WIDT_B = 32'b00000000000000000000000000000110
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 702)] Elaborating instance u_zoom_hdmi_fifo
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 704)] Elaborating instance u_zoom_hdmi_fifo
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/zoom_hdmi_fifo/zoom_hdmi_fifo.v(line number: 16)] Elaborating module zoom_hdmi_fifo
@@ -8768,10 +8768,10 @@
Verilog-2039: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v(line number: 196)] Repeat multiplier in concatenation evaluates to 0
- Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 702)] Width mismatch between port wr_water_level and signal bound to it for instantiated module zoom_hdmi_fifo
+ Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 704)] Width mismatch between port wr_water_level and signal bound to it for instantiated module zoom_hdmi_fifo
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 741)] Elaborating instance u_sync_vg
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 743)] Elaborating instance u_sync_vg
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/hdmi/hdmi_out/sync_vg.v(line number: 35)] Elaborating module sync_vg
@@ -8794,10 +8794,10 @@
HV_OFFSET = 12'b000000000000
- Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 730)] Width mismatch between port rd_mode and signal bound to it for instantiated module sync_vg
+ Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 732)] Width mismatch between port rd_mode and signal bound to it for instantiated module sync_vg
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 779)] Elaborating instance udp_osd_inst
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 781)] Elaborating instance udp_osd_inst
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/udp_osd/udp_osd.v(line number: 3)] Elaborating module udp_osd
@@ -9598,13 +9598,13 @@
Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/udp_osd/udp_osd.v(line number: 123)] Net udp_tx_m_last connected to input port of module instance multimedia_video_processor/udp_osd_inst.eth_udp_inst has no driver, tie it to 0
- Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 772)] Width mismatch between port cfg_end_posX and signal bound to it for instantiated module udp_osd
+ Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 774)] Width mismatch between port cfg_end_posX and signal bound to it for instantiated module udp_osd
- Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 772)] Width mismatch between port cfg_end_posY and signal bound to it for instantiated module udp_osd
+ Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 774)] Width mismatch between port cfg_end_posY and signal bound to it for instantiated module udp_osd
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 823)] Elaborating instance adjust_color_wrapper_inst
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 825)] Elaborating instance adjust_color_wrapper_inst
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/adjust_color/adjust_color_wrapper.v(line number: 1)] Elaborating module adjust_color_wrapper
@@ -9978,7 +9978,7 @@
Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/adjust_color/adjust_color_wrapper.v(line number: 29)] Width mismatch between port pixel_s_valid and signal bound to it for instantiated module adjust_color
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 854)] Elaborating instance u_ddr_addr_ctr
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 856)] Elaborating instance u_ddr_addr_ctr
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v(line number: 1)] Elaborating module ddr_addr_ctr
@@ -10333,19 +10333,19 @@
WIDTH = 32'b00000000000000000000000000000101
- Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 847)] Width mismatch between port shift_h and signal bound to it for instantiated module ddr_addr_ctr
+ Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 849)] Width mismatch between port shift_h and signal bound to it for instantiated module ddr_addr_ctr
- Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 847)] Width mismatch between port rd1_mode and signal bound to it for instantiated module ddr_addr_ctr
+ Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 849)] Width mismatch between port rd1_mode and signal bound to it for instantiated module ddr_addr_ctr
- Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 847)] Width mismatch between port rd2_vs and signal bound to it for instantiated module ddr_addr_ctr
+ Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 849)] Width mismatch between port rd2_vs and signal bound to it for instantiated module ddr_addr_ctr
- Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 847)] Width mismatch between port hdmi_out_mode and signal bound to it for instantiated module ddr_addr_ctr
+ Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 849)] Width mismatch between port hdmi_out_mode and signal bound to it for instantiated module ddr_addr_ctr
- Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 935)] Elaborating instance u_axi_ddr_top
+ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 937)] Elaborating instance u_axi_ddr_top
Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ddr/rd_wr_ctrl/axi_ddr_top.v(line number: 7)] Elaborating module axi_ddr_top
@@ -17279,16 +17279,16 @@
Verilog-2039: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v(line number: 196)] Repeat multiplier in concatenation evaluates to 0
- Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 854)] Net sift_done connected to input port of module instance multimedia_video_processor.u_ddr_addr_ctr has no driver, tie it to 0
+ Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 856)] Net sift_done connected to input port of module instance multimedia_video_processor.u_ddr_addr_ctr has no driver, tie it to 0
- Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 935)] Net wr2_data_in_valid connected to input port of module instance multimedia_video_processor.u_axi_ddr_top has no driver, tie it to 0
+ Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 937)] Net wr2_data_in_valid connected to input port of module instance multimedia_video_processor.u_axi_ddr_top has no driver, tie it to 0
- Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 935)] Net wr2_data_in connected to input port of module instance multimedia_video_processor.u_axi_ddr_top has no driver, tie it to 0
+ Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 937)] Net wr2_data_in connected to input port of module instance multimedia_video_processor.u_axi_ddr_top has no driver, tie it to 0
- Verilog-2021: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 1000)] Net hdmi_out_en in multimedia_video_processor(original module multimedia_video_processor) does not have a driver, tie it to 0
+ Verilog-2021: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 1002)] Net hdmi_out_en in multimedia_video_processor(original module multimedia_video_processor) does not have a driver, tie it to 0
Loop was found during constant probe.
@@ -20452,6 +20452,12 @@
Loop was found during constant probe.
+
+ Loop was found during constant probe.
+
+
+ Loop was found during constant probe.
+
diff --git a/project/compile/formal.pvf b/project/compile/formal.pvf
index 9460f4a..daacedb 100644
--- a/project/compile/formal.pvf
+++ b/project/compile/formal.pvf
@@ -3,7 +3,7 @@
#Application name: pds_shell.exe
#OS: Windows 10 10.0.19045
#Hostname: OMEN-WSH
-Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Sat Nov 11 17:52:08 2023
+Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 19:33:20 2023
# pvf -action compile
pvf_reg_constant clk_cnt[31] 0
diff --git a/project/compile/multimedia_video_processor.cmr b/project/compile/multimedia_video_processor.cmr
index a80d019..0e59223 100644
--- a/project/compile/multimedia_video_processor.cmr
+++ b/project/compile/multimedia_video_processor.cmr
@@ -1,4 +1,4 @@
-Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:52:08 2023
+Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:33:20 2023
Inputs and Outputs :
@@ -112,6 +112,6 @@ Inputs and Outputs :
Flow Command: compile -include_path {D:/Project/FPGA_Project/Pango/multimedia_video_processor/project} -top_module multimedia_video_processor
Peak memory: 328 MB
-Total CPU time to compile completion : 0h:0m:25s
-Process Total CPU time to compile completion : 0h:0m:25s
-Total real time to compile completion : 0h:1m:10s
+Total CPU time to compile completion : 0h:0m:26s
+Process Total CPU time to compile completion : 0h:0m:26s
+Total real time to compile completion : 0h:1m:13s
diff --git a/project/compile/multimedia_video_processor_comp.adf b/project/compile/multimedia_video_processor_comp.adf
index 2055747..7226788 100644
Binary files a/project/compile/multimedia_video_processor_comp.adf and b/project/compile/multimedia_video_processor_comp.adf differ
diff --git a/project/compile/parse_design/screen.pds b/project/compile/parse_design/screen.pds
index e5c8238..891faff 100644
--- a/project/compile/parse_design/screen.pds
+++ b/project/compile/parse_design/screen.pds
@@ -1,5 +1,5 @@
(_flow fab_demo "2022.2-SP1-Lite"
- (_comment "Generated by Fabric Compiler (version on 2022.2-SP1-Lite) at Sat Nov 11 17:52:15 2023")
+ (_comment "Generated by Fabric Compiler (version on 2022.2-SP1-Lite) at Wed Nov 15 19:33:28 2023")
(_version "1.0.9")
(_status "initial")
(_project
diff --git a/project/constraint_check/constraint_check.ccr b/project/constraint_check/constraint_check.ccr
index f7d86a1..85dc965 100644
--- a/project/constraint_check/constraint_check.ccr
+++ b/project/constraint_check/constraint_check.ccr
@@ -1,4 +1,4 @@
-##### Written on 2023/11/11 17:52:59 ###############################
+##### Written on 2023/11/15 19:34:13 ###############################
##### INFO ##################################################
diff --git a/project/device_map/dmr.db b/project/device_map/dmr.db
index 90d45cf..b40157c 100644
--- a/project/device_map/dmr.db
+++ b/project/device_map/dmr.db
@@ -2855,7 +2855,7 @@
u_sys_pll/u_pll_e3
clkbufg_1
ntclkbufg_1
- 2826
+ 2824
CLKOUT1
@@ -2865,38 +2865,45 @@
1757
- CLKOUT4
- u_sys_pll/u_pll_e3
+ CLKOUT0
+ U_HDMI_PLL/u_pll_e3
clkbufg_3
ntclkbufg_3
+ 844
+
+
+ CLKOUT4
+ u_sys_pll/u_pll_e3
+ clkbufg_4
+ ntclkbufg_4
256
O
hdmi_in_clk_ibuf
- clkbufg_4
- ntclkbufg_4
+ clkbufg_5
+ ntclkbufg_5
173
O
cmos1_pclk_ibuf
- clkbufg_5
- ntclkbufg_5
+ clkbufg_6
+ ntclkbufg_6
126
O
cmos2_pclk_ibuf
- clkbufg_6
- ntclkbufg_6
+ clkbufg_7
+ ntclkbufg_7
126
CLKOUT3
u_sys_pll/u_pll_e3
- clkbufg_7
- ntclkbufg_7
+ clkbufg_8
+ ntclkbufg_8
26
@@ -2987,9 +2994,9 @@
6
- u_ddr_addr_ctr/N73
- u_ddr_addr_ctr/N73_5
- 22
+ u_ddr_addr_ctr/N76
+ u_ddr_addr_ctr/N76_5
+ 20
u_ddr_rst/N0
@@ -3022,8 +3029,8 @@
6
- u_rotate_image/N316
- u_rotate_image/N316
+ u_rotate_image/N365
+ u_rotate_image/N365
16
@@ -3338,7 +3345,7 @@
udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or
- udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_7
+ udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_4
10
@@ -3406,7 +3413,7 @@
ntclkbufg_1
clkbufg_1
- 2826
+ 2824
sync_vg_100m
@@ -3444,9 +3451,9 @@
989
- zoom_clk
- u_sys_pll/u_pll_e3
- 851
+ ntclkbufg_3
+ clkbufg_3
+ 844
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done
@@ -3464,8 +3471,8 @@
260
- ntclkbufg_3
- clkbufg_3
+ ntclkbufg_4
+ clkbufg_4
256
@@ -3475,8 +3482,8 @@
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319
- udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_3
- 203
+ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_2
+ 201
zoom_rst
@@ -3484,18 +3491,18 @@
181
- ntclkbufg_4
- clkbufg_4
+ ntclkbufg_5
+ clkbufg_5
173
- image_filiter_inst2/pixel_valid
- image_filiter_inst2/multiline_buffer_inst/m_pixel_valid
+ image_filiter_inst/pixel_valid
+ image_filiter_inst/multiline_buffer_inst/m_pixel_valid
149
- image_filiter_inst/pixel_valid
- image_filiter_inst/multiline_buffer_inst/m_pixel_valid
+ image_filiter_inst2/pixel_valid
+ image_filiter_inst2/multiline_buffer_inst/m_pixel_valid
149
@@ -3504,25 +3511,25 @@
131
- ntclkbufg_5
- clkbufg_5
+ ntclkbufg_6
+ clkbufg_6
126
- ntclkbufg_6
- clkbufg_6
+ ntclkbufg_7
+ clkbufg_7
126
+
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466_4
+ 123
+
image_filiter_inst/multiline_buffer_inst/srst
image_filiter_inst/multiline_buffer_inst/srst
120
-
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_5
- 114
-
ms72xx_ctl/iic_dri_rx/N0_1
ms72xx_ctl/iic_dri_rx/N0_1
@@ -3574,13 +3581,13 @@
71
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [1]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [3]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3]
69
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [3]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [0]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0]
69
@@ -3589,10 +3596,15 @@
69
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [0]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [1]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1]
69
+
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d
+ 65
+
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090
@@ -3609,18 +3621,18 @@
65
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d
- 65
+ u_axi_ddr_top/switch_data0 [2]
+ u_axi_ddr_top/switch_data0[2]
+ 64
- u_zoom_image/ram_ch2 [1]
- u_zoom_image/ram_ch2[1]
+ u_axi_ddr_top/switch_data0 [3]
+ u_axi_ddr_top/switch_data0[3]
64
- u_axi_ddr_top/switch_data0 [2]
- u_axi_ddr_top/switch_data0[2]
+ u_zoom_image/ram_ch2 [0]
+ u_zoom_image/ram_ch2[0]
64
@@ -3629,59 +3641,44 @@
64
- u_axi_ddr_top/switch_data0 [3]
- u_axi_ddr_top/switch_data0[3]
- 64
-
-
- u_zoom_image/ram_ch2 [0]
- u_zoom_image/ram_ch2[0]
+ u_zoom_image/ram_ch2 [1]
+ u_zoom_image/ram_ch2[1]
64
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gatecal_start
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start
- 63
+ 61
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24127
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5
56
-
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10
- 54
-
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14
54
- udp_osd_inst/eth_udp_inst/gmii_rxd_valid
- udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10
54
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N252
- 53
+ 52
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17]
+ udp_osd_inst/eth_udp_inst/gmii_rxd_valid
+ udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid
52
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N216
- 52
-
-
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]
- 50
+ 51
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr
@@ -3694,48 +3691,43 @@
49
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gate_move_en
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en
- 48
-
-
- udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96019
- udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_56
+ udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602
+ udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3
48
- udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769
- udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769
+ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26342
+ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32
48
- udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125
- udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125
+ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817
+ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817_3
48
- udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973
- udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_2
+ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639
+ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639
48
- udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26342
- udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32
+ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125
+ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125
48
- udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639
- udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639
+ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769
+ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769
48
- udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602
- udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3
+ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973
+ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_10
48
- udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817
- udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817_3
+ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97586
+ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_55
48
@@ -3743,6 +3735,11 @@
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/valid_ff[2]
47
+
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gate_move_en
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en
+ 47
+
u_rotate_image/rotate_sta_reg [0]
u_rotate_image/rotate_sta_reg[0]
@@ -3753,16 +3750,6 @@
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[15]
46
-
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15]
- 46
-
-
- u_zoom_image/zoom_sta_reg [0]
- u_zoom_image/zoom_sta_reg[0]
- 45
-
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [2]
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/rdy
@@ -3774,14 +3761,9 @@
45
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119
- 44
-
-
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]
- 44
+ u_zoom_image/zoom_sta_reg [0]
+ u_zoom_image/zoom_sta_reg[0]
+ 45
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/init_start
@@ -3789,8 +3771,8 @@
44
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]
44
@@ -3799,34 +3781,29 @@
44
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]
44
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126
44
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119
44
- adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [11]
- adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/rdy
- 43
-
-
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]
- 43
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]
+ 44
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [2]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2]
- 43
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]
+ 44
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [3]
@@ -3834,23 +3811,23 @@
43
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]
43
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [2]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2]
43
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [1]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]
+ adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [11]
+ adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/rdy
43
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [2]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [2]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2]
43
@@ -3858,6 +3835,11 @@
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2]
43
+
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]
+ 43
+
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [2]
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2]
@@ -3869,13 +3851,23 @@
43
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [1]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]
+ 43
+
+
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104
+ 43
+
+
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193
42
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198
42
@@ -3884,9 +3876,14 @@
42
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193
- 42
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr [26]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[26]
+ 41
+
+
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3
+ 41
u_zoom_image/data_in_valid0
@@ -3894,8 +3891,18 @@
41
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [3]
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb
+ u_axi_ddr_top/rd_sta [0]
+ u_axi_ddr_top/rd_sta_reg[0]
+ 41
+
+
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [3]
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb
+ 41
+
+
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_en_real
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1
41
@@ -3920,13 +3927,13 @@
FF
- 13620
+ 13618
64200
22
LUT
- 13929
+ 13927
42800
33
@@ -4010,9 +4017,9 @@
USCM
- 13
+ 14
30
- 44
+ 47
HSST
@@ -4062,10 +4069,10 @@
RAM(GB)
- 0h:0m:28s
- 0h:0m:30s
- 0h:0m:30s
- 557
+ 0h:0m:31s
+ 0h:0m:32s
+ 0h:0m:33s
+ 556
WINDOWS 10 x86_64
Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz
32
@@ -4713,25 +4720,28 @@
The instance clkbufg_2(GTP_CLKBUFG) has been inserted on the net nt_pix_clk in design, driver pin CLKOUT1(instance U_HDMI_PLL/u_pll_e3) -> load pin CLK(instance adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11).
- DeviceMap-2011: The net zoom_clk has both clock instance u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg(GTP_CLKBUFG) loader and other clock pin loader.
+ The instance clkbufg_3(GTP_CLKBUFG) has been inserted on the net zoom_clk in design, driver pin CLKOUT0(instance U_HDMI_PLL/u_pll_e3) -> load pin CLK(instance u_axi_ddr_top/u_axi_rd_connect/rd1_data_valid0).
- The instance clkbufg_3(GTP_CLKBUFG) has been inserted on the net clk_10m in design, driver pin CLKOUT4(instance u_sys_pll/u_pll_e3) -> load pin CLK(instance ms72xx_ctl/iic_dri_rx/busy).
+ The instance clkbufg_4(GTP_CLKBUFG) has been inserted on the net clk_10m in design, driver pin CLKOUT4(instance u_sys_pll/u_pll_e3) -> load pin CLK(instance ms72xx_ctl/iic_dri_rx/busy).
- The instance clkbufg_4(GTP_CLKBUFG) has been inserted on the net nt_hdmi_in_clk in design, driver pin O(instance hdmi_in_clk_ibuf) -> load pin CLK(instance u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull).
+ The instance clkbufg_5(GTP_CLKBUFG) has been inserted on the net nt_hdmi_in_clk in design, driver pin O(instance hdmi_in_clk_ibuf) -> load pin CLK(instance u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull).
- The instance clkbufg_5(GTP_CLKBUFG) has been inserted on the net nt_cmos1_pclk in design, driver pin O(instance cmos1_pclk_ibuf) -> load pin CLK(instance u_ov5640/cmos1_8_16bit/de_cnt).
+ The instance clkbufg_6(GTP_CLKBUFG) has been inserted on the net nt_cmos1_pclk in design, driver pin O(instance cmos1_pclk_ibuf) -> load pin CLK(instance u_ov5640/cmos1_8_16bit/de_cnt).
- The instance clkbufg_6(GTP_CLKBUFG) has been inserted on the net nt_cmos2_pclk in design, driver pin O(instance cmos2_pclk_ibuf) -> load pin CLK(instance u_ov5640/cmos2_8_16bit/de_cnt).
+ The instance clkbufg_7(GTP_CLKBUFG) has been inserted on the net nt_cmos2_pclk in design, driver pin O(instance cmos2_pclk_ibuf) -> load pin CLK(instance u_ov5640/cmos2_8_16bit/de_cnt).
- The instance clkbufg_7(GTP_CLKBUFG) has been inserted on the net clk_25m in design, driver pin CLKOUT3(instance u_sys_pll/u_pll_e3) -> load pin CLK(instance u_ov5640/coms1_reg_config/clk_20k_regdiv).
+ The instance clkbufg_8(GTP_CLKBUFG) has been inserted on the net clk_25m in design, driver pin CLKOUT3(instance u_sys_pll/u_pll_e3) -> load pin CLK(instance u_ov5640/coms1_reg_config/clk_20k_regdiv).
- DeviceMap-4006: Insert a inst clkgate_8(GTP_IOCLKBUF) before u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV(GTP_IOCLKDIV).
+ DeviceMap-2011: The net ddr_clk has both clock instance u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg(GTP_CLKBUFG) loader and other clock pin loader.
+
+
+ DeviceMap-4006: Insert a inst clkgate_9(GTP_IOCLKBUF) before u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV(GTP_IOCLKDIV).
Infer CARRY group, base inst: N15_0_1/gateop, insts:13.
@@ -4763,9 +4773,6 @@
Infer CARRY group, base inst: u_axi_ddr_top/N550_1.fsub_0/gateop, insts:9.
-
- Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N2_1/gateop, insts:5.
-
Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N9_1/gateop, insts:5.
@@ -4788,19 +4795,16 @@
Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N9_1/gateop, insts:6.
- Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_0/gateop, insts:3.
-
-
- Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N24_1.fsub_1/gateop, insts:6.
+ Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_0/gateop, insts:3.
- Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N30.fsub_1/gateop, insts:6.
+ Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop, insts:3.
Infer CARRY group, base inst: u_axi_ddr_top/N866_6_0/gateop, insts:22.
- Infer CARRY group, base inst: u_ddr_addr_ctr/N7_1_1/gateop, insts:21.
+ Infer CARRY group, base inst: u_ddr_addr_ctr/N7_1_1/gateop, insts:19.
Infer CARRY group, base inst: u_rotate_image/N14_1.fsub_1/gateop, insts:11.
@@ -4911,7 +4915,7 @@
Infer CARRY group, base inst: udp_wr_mem_inst/N17_1_0/gateop, insts:8.
- Infer CARRY group, base inst: udp_wr_mem_inst/N30_1.fsub_0/gateop, insts:8.
+ Infer CARRY group, base inst: udp_wr_mem_inst/N30_1.fsub_1/gateop, insts:7.
Infer CARRY group, base inst: image_filiter_inst/hybrid_filter_inst/N99.fsub_1/gateop, insts:5.
@@ -4958,9 +4962,6 @@
Infer CARRY group, base inst: ms72xx_ctl/iic_dri_rx/N136.lt_0/gateop, insts:2.
-
- Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_0/gateop, insts:3.
-
Infer CARRY group, base inst: ms72xx_ctl/iic_dri_tx/N136.lt_0/gateop, insts:2.
@@ -5522,9 +5523,6 @@
Infer CARRY group, base inst: u_ov5640/coms1_reg_config/u1/N36_1_1/gateop, insts:5.
-
- Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop, insts:3.
-
Infer CARRY group, base inst: u_ov5640/coms2_reg_config/u1/N36_1_1/gateop, insts:5.
@@ -5924,9 +5922,6 @@
Infer CARRY group, base inst: udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N185_1_1/gateop, insts:5.
-
- Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop, insts:3.
-
Infer CARRY group, base inst: udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N168_1.fsub_1/gateop, insts:13.
@@ -5987,6 +5982,9 @@
Infer CARRY group, base inst: udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_5_1/gateop, insts:32.
+
+ Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N2_1/gateop, insts:5.
+
Infer CARRY group, base inst: udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3870_1/gateop, insts:32.
@@ -6552,10 +6550,10 @@
Infer CARRY group, base inst: udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.eq_0/gateop, insts:6.
- Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_0/gateop, insts:6.
+ Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_1/gateop, insts:5.
- Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.fsub_1/gateop, insts:5.
+ Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.fsub_0/gateop, insts:6.
Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_0/gateop, insts:6.
@@ -6590,6 +6588,18 @@
Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N9_1/gateop, insts:5.
+
+ Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_0/gateop, insts:3.
+
+
+ Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N24_1.fsub_1/gateop, insts:6.
+
+
+ Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N30.fsub_1/gateop, insts:6.
+
+
+ Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop, insts:3.
+
Infer CARRY group, base inst: u_rotate_image/u_rotate_mult1/N2/gopapm, insts:2.
diff --git a/project/device_map/formal.pvf b/project/device_map/formal.pvf
index bb320b5..a48e8e3 100644
--- a/project/device_map/formal.pvf
+++ b/project/device_map/formal.pvf
@@ -3,6 +3,54 @@
#Application name: pds_shell.exe
#OS: Windows 10 10.0.19045
#Hostname: OMEN-WSH
+Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 19:36:29 2023
+#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023
+#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin
+#Application name: pds_shell.exe
+#OS: Windows 10 10.0.19045
+#Hostname: OMEN-WSH
+Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 19:22:37 2023
+#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023
+#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin
+#Application name: pds_shell.exe
+#OS: Windows 10 10.0.19045
+#Hostname: OMEN-WSH
+Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 15:07:18 2023
+#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023
+#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin
+#Application name: pds_shell.exe
+#OS: Windows 10 10.0.19045
+#Hostname: OMEN-WSH
+Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 14:37:15 2023
+#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023
+#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin
+#Application name: pds_shell.exe
+#OS: Windows 10 10.0.19045
+#Hostname: OMEN-WSH
+Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 14:19:21 2023
+#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023
+#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin
+#Application name: pds_shell.exe
+#OS: Windows 10 10.0.19045
+#Hostname: OMEN-WSH
+Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 14:07:38 2023
+#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023
+#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin
+#Application name: pds_shell.exe
+#OS: Windows 10 10.0.19045
+#Hostname: OMEN-WSH
+Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 13:48:28 2023
+#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023
+#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin
+#Application name: pds_shell.exe
+#OS: Windows 10 10.0.19045
+#Hostname: OMEN-WSH
+Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 10:39:06 2023
+#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023
+#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin
+#Application name: pds_shell.exe
+#OS: Windows 10 10.0.19045
+#Hostname: OMEN-WSH
Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Sat Nov 11 17:55:12 2023
#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023
#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin
diff --git a/project/device_map/multimedia_video_processor.dmr b/project/device_map/multimedia_video_processor.dmr
index 8d742e2..babb69d 100644
--- a/project/device_map/multimedia_video_processor.dmr
+++ b/project/device_map/multimedia_video_processor.dmr
@@ -1,4 +1,4 @@
-Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:55:11 2023
+Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:36:27 2023
Timing Constraint:
-------------------------------------------------------
@@ -569,13 +569,14 @@ Clock Signal:
| Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K | u_ov5640/coms2_reg_config/clock_20k | 25
| CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT | gmii_clk | 1988
| CLKDIVOUT | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV | clkbufg_0 | ntclkbufg_0 | 5817
-| CLKOUT0 | u_sys_pll/u_pll_e3 | clkbufg_1 | ntclkbufg_1 | 2826
+| CLKOUT0 | u_sys_pll/u_pll_e3 | clkbufg_1 | ntclkbufg_1 | 2824
| CLKOUT1 | U_HDMI_PLL/u_pll_e3 | clkbufg_2 | ntclkbufg_2 | 1757
-| CLKOUT4 | u_sys_pll/u_pll_e3 | clkbufg_3 | ntclkbufg_3 | 256
-| O | hdmi_in_clk_ibuf | clkbufg_4 | ntclkbufg_4 | 173
-| O | cmos1_pclk_ibuf | clkbufg_5 | ntclkbufg_5 | 126
-| O | cmos2_pclk_ibuf | clkbufg_6 | ntclkbufg_6 | 126
-| CLKOUT3 | u_sys_pll/u_pll_e3 | clkbufg_7 | ntclkbufg_7 | 26
+| CLKOUT0 | U_HDMI_PLL/u_pll_e3 | clkbufg_3 | ntclkbufg_3 | 844
+| CLKOUT4 | u_sys_pll/u_pll_e3 | clkbufg_4 | ntclkbufg_4 | 256
+| O | hdmi_in_clk_ibuf | clkbufg_5 | ntclkbufg_5 | 173
+| O | cmos1_pclk_ibuf | clkbufg_6 | ntclkbufg_6 | 126
+| O | cmos2_pclk_ibuf | clkbufg_7 | ntclkbufg_7 | 126
+| CLKOUT3 | u_sys_pll/u_pll_e3 | clkbufg_8 | ntclkbufg_8 | 26
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -599,14 +600,14 @@ Reset Signal:
| u_axi_ddr_top/N878 | u_axi_ddr_top/N878 | 16
| u_axi_ddr_top/N889 | u_axi_ddr_top/N889 | 16
| u_axi_rst/N0 | u_axi_rst/N0 | 6
-| u_ddr_addr_ctr/N73 | u_ddr_addr_ctr/N73_5 | 22
+| u_ddr_addr_ctr/N76 | u_ddr_addr_ctr/N76_5 | 20
| u_ddr_rst/N0 | u_ddr_rst/N0 | 3
| u_hdm_in_rst/N0 | u_hdm_in_rst/N0 | 3
| u_hdmi_in_top/N55 | u_hdmi_in_top/N55 | 2
| wr1_rst | u_hdm_in_rst/rst | 5
| u_hdmi_in_top/vs_in1 | u_hdmi_in_top/vs_in1 | 2
| u_hdmi_rst/N0 | u_hdmi_rst/N0 | 6
-| u_rotate_image/N316 | u_rotate_image/N316 | 16
+| u_rotate_image/N365 | u_rotate_image/N365 | 16
| u_sync_vg/h_count[11:0]_or | u_sync_vg/h_count[11:0]_or | 12
| u_sync_vg/pixel_show_en1 | u_sync_vg/pixel_show_en1 | 16
| u_zoom_image/zoom_sta_reg [0] | u_zoom_image/zoom_sta_reg[0] | 8
@@ -669,7 +670,7 @@ Reset Signal:
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_rst | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync/sig_async_r2[0] | 1
| u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_pll_rst | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_rst | 2
| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N861 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N861 | 11
-| udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or | udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_7 | 10
+| udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or | udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_4 | 10
| udp_osd_inst/char_osd_inst/char_next | udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2 | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 | 2275
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0 | 22
@@ -702,7 +703,7 @@ CE Signal:
| u_axi_ddr_top/N867 | u_axi_ddr_top/N867 | 25
| u_axi_ddr_top/N855 | u_axi_ddr_top/N855_inv | 5
| u_hdmi_in_top/N3 | u_hdmi_in_top/N3 | 2
-| u_rotate_image/N302 | u_rotate_image/N302 | 13
+| u_rotate_image/N350 | u_rotate_image/N350 | 13
| N139_0 | N139_0 | 15
| u_rotate_image/rotate_sta_reg [0] | u_rotate_image/rotate_sta_reg[0] | 32
| u_sync_vg/N145 | u_sync_vg/N145_5 | 11
@@ -750,7 +751,7 @@ CE Signal:
| udp_wr_mem_inst/N723 | udp_wr_mem_inst/N723 | 16
| camera_valid | u_ov5640/u_mix_image/data_out_valid1 | 11
| image_filiter_inst/multiline_buffer_inst/N272 | image_filiter_inst/multiline_buffer_inst/N272 | 6
-| image_filiter_inst/multiline_buffer_inst/N21 | image_filiter_inst/multiline_buffer_inst/N176_3 | 9
+| image_filiter_inst/multiline_buffer_inst/N21 | image_filiter_inst/multiline_buffer_inst/N236_3 | 9
| image_filiter_inst/pixel_valid | image_filiter_inst/multiline_buffer_inst/m_pixel_valid | 144
| temp_v | image_filiter_inst/hybrid_filter_inst/m_result_valid | 11
| image_filiter_inst2/multiline_buffer_inst/N272 | image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10:0]_or_1 | 6
@@ -784,9 +785,9 @@ CE Signal:
| param_manager_inst/param_filiter1_mode/N116 | param_manager_inst/param_filiter1_mode/N116 | 72
| param_manager_inst/param_filiter1_mode/N153 | param_manager_inst/param_filiter1_mode/N153 | 3
| param_manager_inst/param_filiter2_mode/N153 | param_manager_inst/param_filiter2_mode/N153 | 3
-| param_manager_inst/param_modify_H/N150 | param_manager_inst/param_modify_H/N150_1 | 9
-| param_manager_inst/param_modify_S/N150 | param_manager_inst/param_modify_S/N150_1 | 9
-| param_manager_inst/param_modify_V/N150 | param_manager_inst/param_modify_V/N150_1 | 9
+| param_manager_inst/param_modify_H/N150 | param_manager_inst/param_modify_H/N150_3 | 9
+| param_manager_inst/param_modify_S/N150 | param_manager_inst/param_modify_S/N150_3 | 9
+| param_manager_inst/param_modify_V/N150 | param_manager_inst/param_modify_V/N150_3 | 9
| param_manager_inst/param_offsetX/N150 | param_manager_inst/param_offsetX/N150_1 | 12
| param_manager_inst/param_offsetY/N150 | param_manager_inst/param_offsetY/N150_1 | 12
| param_manager_inst/param_osd_char_height/N148 | param_manager_inst/param_osd_char_height/N148_4 | 11
@@ -863,7 +864,7 @@ CE Signal:
| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N711 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N711_2 | 11
| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 | 6
| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N848 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N848 | 11
-| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873_1 | 5
+| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873_3 | 5
| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N862 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N862 | 11
| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N858 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_2 | 8
| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_6 | 8
@@ -882,8 +883,8 @@ CE Signal:
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457_1 | 15
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532_1 | 15
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N240 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N240_5 | 8
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219 | 9
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_done | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7:0]_3 | 3
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219_2 | 9
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_done | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N12_4 | 3
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N1814 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N1814 | 8
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/N18 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/N18 | 3
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2053 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2053 | 14
@@ -918,19 +919,19 @@ CE Signal:
| u_rotate_image/N164_1 | u_rotate_image/N164_1 | 12
| u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N0_1 | u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N0_1 | 12
| u_rotate_image/addr_fifo_rd_en | u_rotate_image/N181_1 | 1
-| u_rotate_image/N339_2 | u_rotate_image/N169_1 | 11
+| u_rotate_image/N395_2 | u_rotate_image/N169_1 | 11
| u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N0_1 | u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N0_1 | 11
| u_rotate_image/N170 | u_rotate_image/N170_5 | 1
-| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_3 | 81
+| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_2 | 81
| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563_4 | 5
| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N706 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N706 | 32
| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | 48
| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N1057 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N1057_5 | 8
-| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866_5 | 8
+| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866_2 | 8
| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N847 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N847 | 8
| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N834 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N834 | 32
| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | 48
-| udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N932 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_8 | 2
+| udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N932 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_16 | 2
| udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832 | 80
| udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N765 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N289_1 | 6
| udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N781 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N781_1 | 5
@@ -944,9 +945,9 @@ CE Signal:
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1170 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1170 | 16
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1057 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1057_3 | 8
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943 | 8
-| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N963 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_8 | 24
+| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N963 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943_1 | 24
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1082 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1082 | 8
-| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N518_1 | 8
+| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_9 | 8
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014 | 8
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N956 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N956 | 8
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N905 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N905 | 4
@@ -961,7 +962,7 @@ CE Signal:
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3 | 16
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | 48
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1036 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1036_9_5 | 8
-| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 | udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_2 | 48
+| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_10 | 48
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N969 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1066_4 | 16
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1731 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1731 | 16
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2622 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2622_2 | 32
@@ -972,14 +973,14 @@ CE Signal:
| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N588 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N588_4 | 5
| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N748 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N748 | 16
| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N757 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N757 | 24
-| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665_6 | 24
+| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665_7 | 24
| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3 | 48
| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N859 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N859_3 | 8
| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 | 16
-| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_2 | 8
+| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_5 | 8
| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630_3 | 8
-| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878_2 | 8
-| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_3 | 8
+| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878_4 | 8
+| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_4 | 8
| N64_0 | N64_0 | 2
| image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N9_1 | image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N9_1 | 12
| image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N0_1 | image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N0_1 | 12
@@ -998,7 +999,7 @@ CE Signal:
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752_10 | 18
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N685 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N685 | 18
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[2] | 3
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 | 19
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3 | 19
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N281 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N281 | 22
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N317 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N317 | 15
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N252 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N252 | 2
@@ -1024,9 +1025,9 @@ CE Signal:
| u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N9_1 | u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N9_1 | 11
| u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N0_1 | u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N0_1 | 11
| u_axi_ddr_top/u_axi_rd_connect/rid_en | u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[1] | 1
-| N241_0 | N241_0 | 12
+| N242_0 | N242_0 | 12
| u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N0_1 | u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N0_1 | 10
-| u_axi_ddr_top/u_axi_rd_connect/N78_1_rnmt | N245_0 | 14
+| u_axi_ddr_top/u_axi_rd_connect/N78_1_rnmt | N246_0 | 14
| u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N0_1 | u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N0_1 | 10
| u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N0_1 | u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N0_1 | 10
| u_axi_ddr_top/u_axi_rd_connect/rd_ddr_en | u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[2] | 8
@@ -1056,7 +1057,7 @@ CE Signal:
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N359 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N359 | 5
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N377 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N377 | 8
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N439 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N439 | 8
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4 | 6
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_377 | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N466 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N466 | 4
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136_7 | 8
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N456 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N456 | 13
@@ -1068,9 +1069,9 @@ CE Signal:
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N359 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N359 | 5
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N377 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N377 | 8
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N439 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N439 | 8
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_313 | 6
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4 | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466 | 4
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136_4 | 8
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136_7 | 8
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6 | 10
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N607 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N607 | 8
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N610 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N610 | 8
@@ -1079,7 +1080,7 @@ CE Signal:
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N359 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N359 | 5
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N377 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N377 | 8
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N439 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N439 | 8
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_378 | 6
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4 | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N466 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N466 | 4
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N136 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N136_4 | 8
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6 | 10
@@ -1090,7 +1091,7 @@ CE Signal:
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N359 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N359 | 5
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N377 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N377 | 8
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N439 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N439 | 8
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_10 | 6
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_378 | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N466 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N466 | 4
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N136 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N136_4 | 8
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6 | 10
@@ -1107,7 +1108,7 @@ CE Signal:
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/gate_check | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gate_check | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gatecal_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start | 12
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139 | 6
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N431 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N431_1 | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5 | 3
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/gate_check | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gate_check | 6
@@ -1120,9 +1121,9 @@ CE Signal:
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/gate_check | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139 | 6
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19_3 | 4
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19_5 | 4
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/N19 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/N19_3 | 4
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19_3 | 4
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19_5 | 4
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N7_1 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N7_1 | 5
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N0_1 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N0_1 | 5
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N7_1 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N7_1 | 5
@@ -1139,7 +1140,7 @@ Other High Fanout Signal:
| Net_Name | Driver | Fanout
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| ntclkbufg_0 | clkbufg_0 | 5817
-| ntclkbufg_1 | clkbufg_1 | 2826
+| ntclkbufg_1 | clkbufg_1 | 2824
| sync_vg_100m | sync_vg_100m | 2548
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 | 2275
| gmii_clk | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT | 1988
@@ -1147,22 +1148,22 @@ Other High Fanout Signal:
| ntclkbufg_2 | clkbufg_2 | 1757
| rd3_rst | u_clk50m_rst/rst | 1674
| u_axi_ddr_top/rst | u_axi_ddr_top/rst0 | 989
-| zoom_clk | u_sys_pll/u_pll_e3 | 851
+| ntclkbufg_3 | clkbufg_3 | 844
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done | 575
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[0] | 261
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[1] | 260
-| ntclkbufg_3 | clkbufg_3 | 256
+| ntclkbufg_4 | clkbufg_4 | 256
| rd2_rst | u_hdmi_rst/rst | 219
-| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_3 | 203
+| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_2 | 201
| zoom_rst | u_zoom_rst/rst | 181
-| ntclkbufg_4 | clkbufg_4 | 173
-| image_filiter_inst2/pixel_valid | image_filiter_inst2/multiline_buffer_inst/m_pixel_valid | 149
+| ntclkbufg_5 | clkbufg_5 | 173
| image_filiter_inst/pixel_valid | image_filiter_inst/multiline_buffer_inst/m_pixel_valid | 149
+| image_filiter_inst2/pixel_valid | image_filiter_inst2/multiline_buffer_inst/m_pixel_valid | 149
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wvld_m | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wvld_m | 131
-| ntclkbufg_5 | clkbufg_5 | 126
| ntclkbufg_6 | clkbufg_6 | 126
+| ntclkbufg_7 | clkbufg_7 | 126
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466_4 | 123
| image_filiter_inst/multiline_buffer_inst/srst | image_filiter_inst/multiline_buffer_inst/srst | 120
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_5 | 114
| ms72xx_ctl/iic_dri_rx/N0_1 | ms72xx_ctl/iic_dri_rx/N0_1 | 110
| u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_dqs_rst | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst | 106
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N208 | 104
@@ -1173,71 +1174,71 @@ Other High Fanout Signal:
| u_ov5640/coms1_reg_config/N4 | u_ov5640/coms1_reg_config/N4 | 72
| param_manager_inst/param_filiter1_mode/N116 | param_manager_inst/param_filiter1_mode/N116 | 72
| u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg | 71
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1] | 69
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [3] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3] | 69
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2] | 69
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0] | 69
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2] | 69
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1] | 69
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d | 65
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090 | 65
| u_axi_ddr_top/u_axi_wr_connect/N235 | u_axi_ddr_top/u_axi_wr_connect/N235_3 | 65
| u_axi_ddr_top/u_axi_wr_connect/N471 | u_axi_ddr_top/u_axi_wr_connect/N471_4 | 65
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d | 65
-| u_zoom_image/ram_ch2 [1] | u_zoom_image/ram_ch2[1] | 64
| u_axi_ddr_top/switch_data0 [2] | u_axi_ddr_top/switch_data0[2] | 64
-| u_axi_ddr_top/u_axi_wr_connect/N473 | u_axi_ddr_top/u_axi_wr_connect/N473_3 | 64
| u_axi_ddr_top/switch_data0 [3] | u_axi_ddr_top/switch_data0[3] | 64
| u_zoom_image/ram_ch2 [0] | u_zoom_image/ram_ch2[0] | 64
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gatecal_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start | 63
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24127 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5 | 56
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 | 54
+| u_axi_ddr_top/u_axi_wr_connect/N473 | u_axi_ddr_top/u_axi_wr_connect/N473_3 | 64
+| u_zoom_image/ram_ch2 [1] | u_zoom_image/ram_ch2[1] | 64
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gatecal_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start | 61
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5 | 56
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14 | 54
-| udp_osd_inst/eth_udp_inst/gmii_rxd_valid | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid | 54
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N252 | 53
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17] | 52
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N216 | 52
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16] | 50
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 | 54
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N252 | 52
+| udp_osd_inst/eth_udp_inst/gmii_rxd_valid | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid | 52
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N216 | 51
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr | 49
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N958 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N958_2 | 49
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gate_move_en | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en | 48
-| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96019 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_56 | 48
-| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | 48
-| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | 48
-| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 | udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_2 | 48
-| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26342 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32 | 48
-| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | 48
| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3 | 48
+| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26342 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32 | 48
| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817_3 | 48
+| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | 48
+| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | 48
+| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | 48
+| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_10 | 48
+| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97586 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_55 | 48
| adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/valid_ff [2] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/valid_ff[2] | 47
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gate_move_en | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en | 47
| u_rotate_image/rotate_sta_reg [0] | u_rotate_image/rotate_sta_reg[0] | 46
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/phy_addr [15] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[15] | 46
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15] | 46
-| u_zoom_image/zoom_sta_reg [0] | u_zoom_image/zoom_sta_reg[0] | 45
| adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [2] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/rdy | 45
| adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [12] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/rdy | 45
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 | 44
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0] | 44
+| u_zoom_image/zoom_sta_reg [0] | u_zoom_image/zoom_sta_reg[0] | 45
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/init_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/init_start | 44
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 | 44
-| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15 | 44
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0] | 44
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0] | 44
+| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15 | 44
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0] | 44
-| adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [11] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/rdy | 43
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] | 43
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2] | 43
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 | 44
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 | 44
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0] | 44
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0] | 44
| adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [3] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/rdy | 43
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] | 43
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 | 43
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1] | 43
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] | 43
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2] | 43
+| adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [11] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/rdy | 43
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2] | 43
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2] | 43
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] | 43
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2] | 43
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1] | 43
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1] | 43
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 | 43
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 | 42
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198 | 42
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3 | 42
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N197 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N197 | 42
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 | 42
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr [26] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[26] | 41
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3 | 41
| u_zoom_image/data_in_valid0 | u_zoom_image/data_in_valid0 | 41
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [3] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb | 41
+| u_axi_ddr_top/rd_sta [0] | u_axi_ddr_top/rd_sta_reg[0] | 41
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [3] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb | 41
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_en_real | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1 | 41
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -1249,8 +1250,8 @@ Device Utilization Summary:
+-------------------------------------------------------------------------+
| APM | 23.5 | 84 | 28
| IOCKDLY | 1 | 40 | 3
-| FF | 13620 | 64200 | 22
-| LUT | 13929 | 42800 | 33
+| FF | 13618 | 64200 | 22
+| LUT | 13927 | 42800 | 33
| Distributed RAM | 88 | 17000 | 1
| DLL | 2 | 10 | 20
| DQSL | 8 | 18 | 45
@@ -1264,7 +1265,7 @@ Device Utilization Summary:
| RCKB | 0 | 24 | 0
| SCANCHAIN | 0 | 2 | 0
| START | 0 | 1 | 0
-| USCM | 13 | 30 | 44
+| USCM | 14 | 30 | 47
| HSST | 0 | 1 | 0
| OSC | 0 | 1 | 0
| CRYSTAL | 0 | 2 | 0
@@ -1276,7 +1277,7 @@ Device Utilization Summary:
Virtual IO Port Info:
NULL
Device mapping done.
-Total device mapping takes 4.22 sec.
+Total device mapping takes 5.19 sec.
Inputs and Outputs :
@@ -1292,7 +1293,7 @@ Inputs and Outputs :
Flow Command: dev_map
-Peak memory: 557 MB
-Total CPU time to dev_map completion : 0h:0m:28s
-Process Total CPU time to dev_map completion : 0h:0m:30s
-Total real time to dev_map completion : 0h:0m:30s
+Peak memory: 556 MB
+Total CPU time to dev_map completion : 0h:0m:31s
+Process Total CPU time to dev_map completion : 0h:0m:32s
+Total real time to dev_map completion : 0h:0m:33s
diff --git a/project/device_map/multimedia_video_processor_map.adf b/project/device_map/multimedia_video_processor_map.adf
index bfed5cd..8be51c2 100644
Binary files a/project/device_map/multimedia_video_processor_map.adf and b/project/device_map/multimedia_video_processor_map.adf differ
diff --git a/project/device_map/psd_ddr_top.pcf b/project/device_map/psd_ddr_top.pcf
index d3a56b9..1d28b2e 100644
--- a/project/device_map/psd_ddr_top.pcf
+++ b/project/device_map/psd_ddr_top.pcf
@@ -1,4 +1,4 @@
-#Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:55:22 2023
+#Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:36:40 2023
def_port {cmos1_scl} LOC=Y11 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE
def_port {cmos1_sda} LOC=Y13 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE
diff --git a/project/generate_bitstream/bgr.db b/project/generate_bitstream/bgr.db
index c571564..19e371a 100644
--- a/project/generate_bitstream/bgr.db
+++ b/project/generate_bitstream/bgr.db
@@ -11,10 +11,10 @@
RAM(GB)
- 0h:0m:37s
- 0h:0m:37s
- 0h:0m:38s
- 927
+ 0h:0m:41s
+ 0h:0m:41s
+ 0h:0m:41s
+ 926
WINDOWS 10 x86_64
Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz
32
diff --git a/project/generate_bitstream/multimedia_video_processor.bgr b/project/generate_bitstream/multimedia_video_processor.bgr
index 6599e9d..01688ba 100644
--- a/project/generate_bitstream/multimedia_video_processor.bgr
+++ b/project/generate_bitstream/multimedia_video_processor.bgr
@@ -1,9 +1,9 @@
-Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:59:01 2023
+Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:40:41 2023
Start Generating Programming File...
-Reading design from DB takes 4.125000 sec.
+Reading design from DB takes 4.390625 sec.
The bitstream file is "D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/generate_bitstream/multimedia_video_processor.sbit"
-Generate programming file takes 26.937500 sec.
+Generate programming file takes 29.625000 sec.
Generating Programming File done.
Inputs and Outputs :
@@ -19,7 +19,7 @@ Inputs and Outputs :
Flow Command: gen_bit_stream
-Peak memory: 927 MB
-Total CPU time to gen_bit_stream completion : 0h:0m:37s
-Process Total CPU time to gen_bit_stream completion : 0h:0m:37s
-Total real time to gen_bit_stream completion : 0h:0m:38s
+Peak memory: 926 MB
+Total CPU time to gen_bit_stream completion : 0h:0m:41s
+Process Total CPU time to gen_bit_stream completion : 0h:0m:41s
+Total real time to gen_bit_stream completion : 0h:0m:41s
diff --git a/project/generate_bitstream/multimedia_video_processor.sbit b/project/generate_bitstream/multimedia_video_processor.sbit
index 1864f14..8811f53 100644
Binary files a/project/generate_bitstream/multimedia_video_processor.sbit and b/project/generate_bitstream/multimedia_video_processor.sbit differ
diff --git a/project/generate_bitstream/multimedia_video_processor.smsk b/project/generate_bitstream/multimedia_video_processor.smsk
index b11390f..60b6aa6 100644
Binary files a/project/generate_bitstream/multimedia_video_processor.smsk and b/project/generate_bitstream/multimedia_video_processor.smsk differ
diff --git a/project/impl.tcl b/project/impl.tcl
index f6e39f8..9e7668c 100644
--- a/project/impl.tcl
+++ b/project/impl.tcl
@@ -101,3 +101,61 @@ dev_map
pnr -fix_hold_violation
report_timing
gen_bit_stream
+set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484
+compile -top_module multimedia_video_processor
+set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484
+compile -top_module multimedia_video_processor
+synthesize -ads -frequency {100} -selected_syn_tool_opt 2
+dev_map
+pnr -fix_hold_violation
+report_timing
+gen_bit_stream
+set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484
+compile -top_module multimedia_video_processor
+synthesize -ads -frequency {100} -selected_syn_tool_opt 2
+dev_map
+pnr -fix_hold_violation
+report_timing
+gen_bit_stream
+set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484
+compile -top_module multimedia_video_processor
+synthesize -ads -frequency {100} -selected_syn_tool_opt 2
+dev_map
+pnr -fix_hold_violation
+report_timing
+gen_bit_stream
+set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484
+compile -top_module multimedia_video_processor
+synthesize -ads -frequency {100} -selected_syn_tool_opt 2
+dev_map
+pnr -fix_hold_violation
+report_timing
+gen_bit_stream
+set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484
+compile -top_module multimedia_video_processor
+synthesize -ads -frequency {100} -selected_syn_tool_opt 2
+dev_map
+pnr -fix_hold_violation
+report_timing
+gen_bit_stream
+set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484
+compile -top_module multimedia_video_processor
+synthesize -ads -frequency {100} -selected_syn_tool_opt 2
+dev_map
+pnr -fix_hold_violation
+report_timing
+gen_bit_stream
+set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484
+compile -top_module multimedia_video_processor
+synthesize -ads -frequency {100} -selected_syn_tool_opt 2
+dev_map
+pnr -fix_hold_violation
+report_timing
+gen_bit_stream
+set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484
+compile -top_module multimedia_video_processor
+synthesize -ads -frequency {100} -selected_syn_tool_opt 2
+dev_map
+pnr -fix_hold_violation
+report_timing
+gen_bit_stream
diff --git a/project/multimedia_video_processor.pds b/project/multimedia_video_processor.pds
index 521fccf..f4187f0 100644
--- a/project/multimedia_video_processor.pds
+++ b/project/multimedia_video_processor.pds
@@ -1,5 +1,5 @@
(_flow fab_demo "2022.2-SP1-Lite"
- (_comment "Generated by Fabric Compiler (version on 2022.2-SP1-Lite) at Sat Nov 11 17:59:26 2023")
+ (_comment "Generated by Fabric Compiler (version on 2022.2-SP1-Lite) at Wed Nov 15 19:41:09 2023")
(_version "1.0.9")
(_status "initial")
(_project
@@ -21,7 +21,7 @@
(_input
(_file "../sources/designs/multimedia_video_processor.v" + "multimedia_video_processor"
(_format verilog)
- (_timespec "2023-11-11T17:50:53")
+ (_timespec "2023-11-15T19:32:44")
)
(_file "../sources/designs/udp_osd/char_osd/char_buf_reader.v"
(_format verilog)
@@ -33,7 +33,7 @@
)
(_file "../sources/designs/udp_osd/char_osd/char_osd.v"
(_format verilog)
- (_timespec "2023-10-22T13:28:44")
+ (_timespec "2023-11-14T18:21:34")
)
(_file "../sources/designs/udp_osd/char_osd/char_pic_rom.v"
(_format verilog)
@@ -65,7 +65,7 @@
)
(_file "../sources/designs/udp_osd/eth_udp/eth_udp.v"
(_format verilog)
- (_timespec "2023-11-08T14:35:25")
+ (_timespec "2023-11-14T18:06:57")
)
(_file "../sources/designs/udp_osd/eth_udp/icmp/icmp.v"
(_format verilog)
@@ -121,7 +121,7 @@
)
(_file "../sources/designs/image_filiter/image_filiter.v"
(_format verilog)
- (_timespec "2023-11-05T17:01:17")
+ (_timespec "2023-11-14T11:20:48")
)
(_file "../sources/designs/image_filiter/median_finder9.v"
(_format verilog)
@@ -129,7 +129,7 @@
)
(_file "../sources/designs/image_filiter/multiline_buffer.v"
(_format verilog)
- (_timespec "2023-11-06T18:55:59")
+ (_timespec "2023-11-14T11:36:55")
)
(_file "../sources/designs/image_filiter/sort_3.v"
(_format verilog)
@@ -137,7 +137,7 @@
)
(_file "../sources/designs/image_filiter/vector_to_matrix.v"
(_format verilog)
- (_timespec "2023-11-06T18:56:26")
+ (_timespec "2023-11-14T11:52:33")
)
(_file "../sources/designs/others/key_debounce.v"
(_format verilog)
@@ -145,7 +145,7 @@
)
(_file "../sources/designs/others/param_manager.v"
(_format verilog)
- (_timespec "2023-11-11T17:22:27")
+ (_timespec "2023-11-15T10:35:11")
)
(_file "../sources/designs/others/udp_wr_mem.v"
(_format verilog)
@@ -153,7 +153,7 @@
)
(_file "../sources/designs/adjust_color/adjust_color.v"
(_format verilog)
- (_timespec "2023-11-10T14:46:20")
+ (_timespec "2023-11-14T23:57:44")
)
(_file "../sources/designs/adjust_color/adjust_color_wrapper.v"
(_format verilog)
@@ -185,7 +185,7 @@
)
(_file "../sources/designs/others/param_cell_signed_loop.v"
(_format verilog)
- (_timespec "2023-11-10T15:35:23")
+ (_timespec "2023-11-13T13:23:08")
)
(_file "../sources/designs/others/param_cell_unsigned.v"
(_format verilog)
@@ -201,7 +201,7 @@
)
(_file "../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v"
(_format verilog)
- (_timespec "2023-11-11T12:21:50")
+ (_timespec "2023-11-15T14:33:30")
)
(_file "../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v"
(_format verilog)
@@ -221,7 +221,7 @@
)
(_file "../sources/designs/ddr/addr_ctrl/wr0_addr_ctr.v"
(_format verilog)
- (_timespec "2023-11-11T12:21:56")
+ (_timespec "2023-11-12T21:42:35")
)
(_file "../sources/designs/ddr/addr_ctrl/wr1_addr_ctr.v"
(_format verilog)
@@ -249,7 +249,7 @@
)
(_file "../sources/designs/hdmi/hdmi_out/sync_vg.v"
(_format verilog)
- (_timespec "2023-11-11T12:22:10")
+ (_timespec "2023-11-15T10:28:46")
)
(_file "../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v"
(_format verilog)
@@ -277,11 +277,11 @@
)
(_file "../sources/designs/ov5640/mix_image.v"
(_format verilog)
- (_timespec "2023-11-11T12:23:05")
+ (_timespec "2023-11-13T20:58:00")
)
(_file "../sources/designs/ov5640/ov5640.v"
(_format verilog)
- (_timespec "2023-11-11T13:00:25")
+ (_timespec "2023-11-13T23:26:58")
)
(_file "../sources/designs/ov5640/power_on_delay.v"
(_format verilog)
@@ -297,7 +297,7 @@
)
(_file "../sources/designs/rotate/rotate_image.v"
(_format verilog)
- (_timespec "2023-11-11T16:05:07")
+ (_timespec "2023-11-15T15:01:39")
)
(_file "../sources/designs/rotate/rotate_mult0.v"
(_format verilog)
@@ -317,11 +317,11 @@
)
(_file "../sources/designs/zoom/zoom_image_v1.v"
(_format verilog)
- (_timespec "2023-11-11T16:30:42")
+ (_timespec "2023-11-14T16:38:20")
)
(_file "../sources/designs/hdmi/hdmi_in/hdmi_in_top.v"
(_format verilog)
- (_timespec "2023-11-11T12:22:10")
+ (_timespec "2023-11-14T11:14:09")
)
)
)
@@ -848,17 +848,17 @@
(_db_output
(_file "compile/multimedia_video_processor_comp.adf"
(_format adif)
- (_timespec "2023-11-11T17:52:48")
+ (_timespec "2023-11-15T19:34:03")
)
)
(_output
(_file "compile/multimedia_video_processor.cmr"
(_format verilog)
- (_timespec "2023-11-11T17:52:49")
+ (_timespec "2023-11-15T19:34:03")
)
(_file "compile/cmr.db"
(_format text)
- (_timespec "2023-11-11T17:52:49")
+ (_timespec "2023-11-15T19:34:03")
)
)
)
@@ -874,25 +874,25 @@
(_db_output
(_file "synthesize/multimedia_video_processor_syn.adf"
(_format adif)
- (_timespec "2023-11-11T17:54:39")
+ (_timespec "2023-11-15T19:35:56")
)
)
(_output
(_file "synthesize/multimedia_video_processor_syn.vm"
(_format structural_verilog)
- (_timespec "2023-11-11T17:54:44")
+ (_timespec "2023-11-15T19:35:59")
)
(_file "synthesize/multimedia_video_processor_controlsets.txt"
(_format text)
- (_timespec "2023-11-11T17:54:12")
+ (_timespec "2023-11-15T19:35:28")
)
(_file "synthesize/snr.db"
(_format text)
- (_timespec "2023-11-11T17:54:49")
+ (_timespec "2023-11-15T19:36:04")
)
(_file "synthesize/multimedia_video_processor.snr"
(_format text)
- (_timespec "2023-11-11T17:54:48")
+ (_timespec "2023-11-15T19:36:03")
)
)
)
@@ -913,21 +913,21 @@
(_db_output
(_file "device_map/multimedia_video_processor_map.adf"
(_format adif)
- (_timespec "2023-11-11T17:55:22")
+ (_timespec "2023-11-15T19:36:40")
)
)
(_output
(_file "device_map/multimedia_video_processor_dmr.prt"
(_format text)
- (_timespec "2023-11-11T17:55:09")
+ (_timespec "2023-11-15T19:36:26")
)
(_file "device_map/multimedia_video_processor.dmr"
(_format text)
- (_timespec "2023-11-11T17:55:22")
+ (_timespec "2023-11-15T19:36:40")
)
(_file "device_map/dmr.db"
(_format text)
- (_timespec "2023-11-11T17:55:22")
+ (_timespec "2023-11-15T19:36:40")
)
)
)
@@ -936,7 +936,7 @@
(_input
(_file "device_map/psd_ddr_top.pcf"
(_format pcf)
- (_timespec "2023-11-11T17:55:22")
+ (_timespec "2023-11-15T19:36:40")
)
)
)
@@ -946,7 +946,7 @@
(_file "kkk.rcf"
(_option target_file (_switch ON))
(_format rcf)
- (_timespec "2023-11-11T16:19:45")
+ (_timespec "")
)
)
)
@@ -958,33 +958,33 @@
(_db_output
(_file "place_route/multimedia_video_processor_pnr.adf"
(_format adif)
- (_timespec "2023-11-11T17:58:10")
+ (_timespec "2023-11-15T19:39:47")
)
)
(_output
(_file "place_route/clock_utilization.txt"
(_format text)
- (_timespec "2023-11-11T17:57:51")
+ (_timespec "2023-11-15T19:39:27")
)
(_file "place_route/multimedia_video_processor_plc.adf"
(_format adif)
- (_timespec "2023-11-11T17:56:43")
+ (_timespec "2023-11-15T19:38:00")
)
(_file "place_route/multimedia_video_processor.prr"
(_format text)
- (_timespec "2023-11-11T17:58:11")
+ (_timespec "2023-11-15T19:39:48")
)
(_file "place_route/multimedia_video_processor_prr.prt"
(_format text)
- (_timespec "2023-11-11T17:57:51")
+ (_timespec "2023-11-15T19:39:27")
)
(_file "place_route/multimedia_video_processor_pnr.netlist"
(_format text)
- (_timespec "2023-11-11T17:58:11")
+ (_timespec "2023-11-15T19:39:48")
)
(_file "place_route/prr.db"
(_format text)
- (_timespec "2023-11-11T17:58:11")
+ (_timespec "2023-11-15T19:39:48")
)
)
)
@@ -1000,17 +1000,17 @@
(_db_output
(_file "report_timing/multimedia_video_processor_rtp.adf"
(_format adif)
- (_timespec "2023-11-11T17:58:38")
+ (_timespec "2023-11-15T19:40:16")
)
)
(_output
(_file "report_timing/multimedia_video_processor.rtr"
(_format text)
- (_timespec "2023-11-11T17:58:40")
+ (_timespec "2023-11-15T19:40:19")
)
(_file "report_timing/rtr.db"
(_format text)
- (_timespec "2023-11-11T17:58:41")
+ (_timespec "2023-11-15T19:40:19")
)
)
)
@@ -1034,19 +1034,19 @@
(_output
(_file "generate_bitstream/multimedia_video_processor.sbit"
(_format text)
- (_timespec "2023-11-11T17:59:23")
+ (_timespec "2023-11-15T19:41:06")
)
(_file "generate_bitstream/multimedia_video_processor.smsk"
(_format text)
- (_timespec "2023-11-11T17:59:24")
+ (_timespec "2023-11-15T19:41:07")
)
(_file "generate_bitstream/bgr.db"
(_format text)
- (_timespec "2023-11-11T17:59:25")
+ (_timespec "2023-11-15T19:41:08")
)
(_file "generate_bitstream/multimedia_video_processor.bgr"
(_format text)
- (_timespec "2023-11-11T17:59:24")
+ (_timespec "2023-11-15T19:41:07")
)
)
)
diff --git a/project/multiseed_summary.csv b/project/multiseed_summary.csv
index b4f115b..15791f5 100644
--- a/project/multiseed_summary.csv
+++ b/project/multiseed_summary.csv
@@ -3,23 +3,23 @@ project name,multimedia_video_processor.pds
Single Seed:
Seed,State,Convergence,Setup(Slow),Setup(Fast),Hold(Slow),Hold(Fast),Recovery(Slow),Recovery(Fast),Removal(Slow),Removal(Fast),PBM-GP,PBM-PreGP,PBM-PostGP,LP,Total Placement Cpu Time,Detailed routing,Total Routing Cpu Time,Wire Length After Post-GP,Wire Length After LP,Wire Length After DP,Routing Arc Length,Worst Slack After GP Timing,Worst Slack After LP Timing,Worst Slack Before RP,Worst Slack Before DP,Worst Slack After DP,Worst Slack After Placement,Worst Slack After TA By Preroute,TNS After DP,TNS Before Route,Setup(Slow) Total Failing TNS,Setup(Slow) Total Failing Endpoints,Hold(Slow) Total Failing THS,Hold(Slow) Total Failing Endpoints
-single,OK,Fail,-0.788,0.707,0.149,0.106,1.103,2.157,0.554,0.418,NA,NA,NA,1.64,44.78,30.09,49.84,121211,154129,154129,215189,NA,NA,-1259,NA,NA,-1259,NA,NA,-36829,-18.651,44,0.000,0
-Pass Rate/Convergence Rate,100.00%,0.00%
+single,OK,OK,1.026,1.834,0.157,0.075,1.149,2.160,0.555,0.452,NA,NA,NA,1.70,42.31,37.05,64.98,129229,158300,158329,212372,NA,NA,556,NA,NA,1339,NA,NA,0,0.000,0,0.000,0
+Pass Rate/Convergence Rate,100.00%,100.00%
Synthesize:
control_set,504
Synthesize Performance Summary:
slack category,Synthesize Setup WNS,Synthesize Setup TNS,Synthesize Recovery WNS,Synthesize Recovery TNS
-slack value,0.130,0.000,1.564,0.000
-Synthesize Process Cpu Time,0h:1m:39s
+slack value,1.064,0.000,1.564,0.000
+Synthesize Process Cpu Time,0h:1m:43s
Device Map:
Device Map Resource Usage Summary:
Logic Utilization,LUT,FF,DRM,APM,Distributed RAM,HSSTHP,USCM,HCKB,RCKB
-Used,13929,13620,98.5,23.5,88,NA,13,NA,0
+Used,13927,13618,98.5,23.5,88,NA,14,NA,0
Available,42800,64200,134,84,17000,NA,30,NA,24
-Utilization(%),33%,22%,74%,28%,1%,NA,44%,NA,0%
-Device Map Process Cpu Time,0h:0m:30s
+Utilization(%),33%,22%,74%,28%,1%,NA,47%,NA,0%
+Device Map Process Cpu Time,0h:0m:32s
Project Configurations:
top module,multimedia_video_processor
diff --git a/project/place_route/clock_utilization.txt b/project/place_route/clock_utilization.txt
index a43b4be..3ae07a6 100644
--- a/project/place_route/clock_utilization.txt
+++ b/project/place_route/clock_utilization.txt
@@ -23,17 +23,18 @@ Global Clock Buffer Constraint Details:
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Clock Region Of Buffer Site | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-| u_sys_pll/u_pll_e3/goppll | CLKOUT0 | rd3_clk | CLK | clkbufg_1/gopclkbufg | CLKOUT | ntclkbufg_1 | --- | --- | --- | --- | 2517 | 0
-| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf | CLK | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | CLKOUT | gmii_clk | --- | --- | (36,158,90,91) | --- | 1861 | 0
-| u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | CLK | clkbufg_3/gopclkbufg | CLKOUT | ntclkbufg_3 | --- | --- | --- | --- | 235 | 0
-| hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | CLK | clkbufg_4/gopclkbufg | CLKOUT | ntclkbufg_4 | --- | --- | --- | --- | 167 | 0
-| cmos1_pclk_ibuf/opit_1 | INCK | _N64 | CLK | clkbufg_5/gopclkbufg | CLKOUT | ntclkbufg_5 | --- | --- | --- | --- | 118 | 0
-| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | zoom_clk | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | --- | --- | --- | (79,79,43,47) | 68 | 0
-| u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | CLK | clkbufg_7/gopclkbufg | CLKOUT | ntclkbufg_7 | --- | --- | --- | --- | 26 | 0
+| u_sys_pll/u_pll_e3/goppll | CLKOUT0 | rd3_clk | CLK | clkbufg_1/gopclkbufg | CLKOUT | ntclkbufg_1 | --- | --- | --- | --- | 2516 | 0
+| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf | CLK | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | CLKOUT | gmii_clk | --- | --- | (36,158,90,91) | --- | 1862 | 0
+| u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | CLK | clkbufg_4/gopclkbufg | CLKOUT | ntclkbufg_4 | --- | --- | --- | --- | 235 | 0
+| hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | CLK | clkbufg_5/gopclkbufg | CLKOUT | ntclkbufg_5 | --- | --- | --- | --- | 167 | 0
+| cmos1_pclk_ibuf/opit_1 | INCK | _N64 | CLK | clkbufg_6/gopclkbufg | CLKOUT | ntclkbufg_6 | --- | --- | --- | --- | 118 | 0
+| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | ddr_clk | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | --- | --- | --- | (79,79,43,47) | 71 | 0
+| u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | CLK | clkbufg_8/gopclkbufg | CLKOUT | ntclkbufg_8 | --- | --- | --- | --- | 26 | 0
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT1 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk | --- | --- | --- | (74,74,46,46) | 1 | 0
-| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | --- | --- | (0,4,4,89) | (4,4,7,84) | 5464 | 0
| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | nt_pix_clk | CLK | clkbufg_2/gopclkbufg | CLKOUT | ntclkbufg_2 | --- | --- | --- | --- | 1635 | 0
-| cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | CLK | clkbufg_6/gopclkbufg | CLKOUT | ntclkbufg_6 | --- | --- | --- | --- | 118 | 0
+| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | --- | --- | (0,4,4,89) | (4,4,7,84) | 5464 | 0
+| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT0 | zoom_clk | CLK | clkbufg_3/gopclkbufg | CLKOUT | ntclkbufg_3 | --- | --- | --- | --- | 750 | 0
+| cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | CLK | clkbufg_7/gopclkbufg | CLKOUT | ntclkbufg_7 | --- | --- | --- | --- | 118 | 0
| u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms1_reg_config/clock_20k | --- | --- | --- | --- | 19 | 0
| u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms2_reg_config/clock_20k | --- | --- | --- | --- | 19 | 0
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -47,11 +48,12 @@ Global Clock Source Constraint Details:
| u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | (X0,Y0) | PLL_158_55 | 1 | 0
| hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | (X1,Y0) | IOL_163_6 | 1 | 0
| cmos1_pclk_ibuf/opit_1 | INCK | _N64 | (X1,Y0) | IOL_171_6 | 1 | 0
-| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | zoom_clk | (X0,Y0) | PLL_158_55 | 1 | 759
+| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | ddr_clk | (X0,Y0) | PLL_158_55 | 1 | 6
| u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | (X0,Y0) | PLL_158_55 | 1 | 0
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT1 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll | (X0,Y1) | PLL_158_199 | 1 | 0
-| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | --- | --- | 1 | 0
| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | nt_pix_clk | --- | --- | 1 | 1
+| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | --- | --- | 1 | 0
+| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT0 | zoom_clk | --- | --- | 1 | 0
| cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | (X0,Y0) | IOL_39_6 | 1 | 0
| u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | --- | --- | 1 | 2
| u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | --- | --- | 1 | 2
@@ -64,7 +66,7 @@ IO Clock Buffer Constraint Details:
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] | --- | --- | (0,4,32,59) | (4,4,37,54) | 28 | 0
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] | --- | --- | (0,4,62,84) | (4,4,67,84) | 11 | 0
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_1 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [2] | --- | --- | (4,4,7,24) | (4,4,7,24) | 2 | 0
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | clkgate_8/gopclkgate | OUT | ntclkgate_0 | --- | --- | --- | --- | 0 | 1
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | clkgate_9/gopclkgate | OUT | ntclkgate_0 | --- | --- | --- | --- | 0 | 1
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
IO Clock Source Constraint Details:
@@ -79,19 +81,20 @@ Device Cell Placement Summary for Global Clock Buffer:
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | USCM_84_116 | (0,2,4,89) | (4,70,3,84) | 5464 | 0
-| u_sys_pll/u_pll_e3/goppll | CLKOUT0 | rd3_clk | CLK | clkbufg_1/gopclkbufg | CLKOUT | ntclkbufg_1 | USCM_84_108 | --- | (23,102,2,53) | 2517 | 0
-| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | nt_pix_clk | CLK | clkbufg_2/gopclkbufg | CLKOUT | ntclkbufg_2 | USCM_84_117 | --- | (74,152,8,88) | 1635 | 0
-| u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | CLK | clkbufg_3/gopclkbufg | CLKOUT | ntclkbufg_3 | USCM_84_110 | --- | (70,120,13,38) | 235 | 0
-| hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | CLK | clkbufg_4/gopclkbufg | CLKOUT | ntclkbufg_4 | USCM_84_111 | --- | (28,96,8,28) | 167 | 0
-| cmos1_pclk_ibuf/opit_1 | INCK | _N64 | CLK | clkbufg_5/gopclkbufg | CLKOUT | ntclkbufg_5 | USCM_84_112 | --- | (66,76,2,10) | 118 | 0
-| cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | CLK | clkbufg_6/gopclkbufg | CLKOUT | ntclkbufg_6 | USCM_84_118 | --- | (63,78,3,15) | 118 | 0
-| u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | CLK | clkbufg_7/gopclkbufg | CLKOUT | ntclkbufg_7 | USCM_84_114 | --- | (90,92,3,6) | 26 | 0
-| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | zoom_clk | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | USCM_84_113 | --- | (7,100,36,47) | 68 | 0
+| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | USCM_84_116 | (0,2,4,89) | (4,81,4,84) | 5464 | 0
+| u_sys_pll/u_pll_e3/goppll | CLKOUT0 | rd3_clk | CLK | clkbufg_1/gopclkbufg | CLKOUT | ntclkbufg_1 | USCM_84_108 | --- | (25,102,5,88) | 2516 | 0
+| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | nt_pix_clk | CLK | clkbufg_2/gopclkbufg | CLKOUT | ntclkbufg_2 | USCM_84_117 | --- | (74,150,3,74) | 1635 | 0
+| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT0 | zoom_clk | CLK | clkbufg_3/gopclkbufg | CLKOUT | ntclkbufg_3 | USCM_84_118 | --- | (56,150,3,78) | 750 | 0
+| u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | CLK | clkbufg_4/gopclkbufg | CLKOUT | ntclkbufg_4 | USCM_84_110 | --- | (42,133,43,80) | 235 | 0
+| hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | CLK | clkbufg_5/gopclkbufg | CLKOUT | ntclkbufg_5 | USCM_84_111 | --- | (39,77,4,33) | 167 | 0
+| cmos1_pclk_ibuf/opit_1 | INCK | _N64 | CLK | clkbufg_6/gopclkbufg | CLKOUT | ntclkbufg_6 | USCM_84_112 | --- | (64,76,3,15) | 118 | 0
+| cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | CLK | clkbufg_7/gopclkbufg | CLKOUT | ntclkbufg_7 | USCM_84_119 | --- | (39,74,2,10) | 118 | 0
+| u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | CLK | clkbufg_8/gopclkbufg | CLKOUT | ntclkbufg_8 | USCM_84_114 | --- | (59,61,2,4) | 26 | 0
+| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | ddr_clk | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | USCM_84_113 | --- | (7,86,43,61) | 71 | 0
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT1 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk | USCM_84_115 | --- | (74,74,46,46) | 1 | 0
-| u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms1_reg_config/clock_20k | USCM_84_119 | --- | (83,91,3,5) | 19 | 0
-| u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms2_reg_config/clock_20k | USCM_84_120 | --- | (85,90,6,9) | 19 | 0
-| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf | CLK | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | CLKOUT | gmii_clk | USCM_84_109 | (36,158,90,91) | (76,125,27,64) | 1861 | 0
+| u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms1_reg_config/clock_20k | USCM_84_120 | --- | (66,72,2,4) | 19 | 0
+| u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms2_reg_config/clock_20k | USCM_84_121 | --- | (40,46,3,4) | 19 | 0
+| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf | CLK | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | CLKOUT | gmii_clk | USCM_84_109 | (36,158,90,91) | (75,134,47,85) | 1862 | 0
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Device Cell Placement Summary for Global Clock Source:
@@ -101,15 +104,16 @@ Device Cell Placement Summary for Global Clock Source:
| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | IOCKDIV_6_323 | 1 | 0
| u_sys_pll/u_pll_e3/goppll | CLKOUT0 | rd3_clk | PLL_158_55 | 1 | 1
| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | nt_pix_clk | PLL_158_303 | 1 | 1
+| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT0 | zoom_clk | PLL_158_303 | 1 | 0
| u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | PLL_158_55 | 1 | 0
| hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | IOL_163_6 | 1 | 0
| cmos1_pclk_ibuf/opit_1 | INCK | _N64 | IOL_171_6 | 1 | 0
| cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | IOL_39_6 | 1 | 0
| u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | PLL_158_55 | 1 | 0
-| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | zoom_clk | PLL_158_55 | 1 | 759
+| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | ddr_clk | PLL_158_55 | 1 | 6
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT1 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll | PLL_158_199 | 1 | 0
-| u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | CLMA_182_12 | 1 | 2
-| u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | CLMA_182_25 | 1 | 2
+| u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | CLMS_122_9 | 1 | 2
+| u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | CLMA_122_12 | 1 | 2
| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf | IOCKDLY_237_367 | 1 | 0
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -117,7 +121,7 @@ Device Cell Placement Summary for IO Clock Buffer:
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | clkgate_8/gopclkgate | OUT | ntclkgate_0 | IOCKGATE_6_322 | --- | (5,5,77,77) | 0 | 1
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | clkgate_9/gopclkgate | OUT | ntclkgate_0 | IOCKGATE_6_322 | --- | (5,5,77,77) | 0 | 1
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] | IOCKGATE_6_312 | (0,2,62,70) | (4,4,67,84) | 11 | 0
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] | IOCKGATE_6_188 | (0,2,32,59) | (4,5,37,54) | 28 | 0
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_1 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [2] | IOCKGATE_6_64 | --- | (4,4,7,24) | 2 | 0
diff --git a/project/place_route/multimedia_video_processor.prr b/project/place_route/multimedia_video_processor.prr
index dac8d5a..6f60925 100644
--- a/project/place_route/multimedia_video_processor.prr
+++ b/project/place_route/multimedia_video_processor.prr
@@ -1,23 +1,23 @@
-Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:55:39 2023
+Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:36:57 2023
In normal mode(fast, normal, performance).
Placement started.
Placement done.
-Total placement takes 44.78 sec.
+Total placement takes 42.31 sec.
Routing started.
-Building routing graph takes 2.20 sec.
-Processing design graph takes 1.97 sec.
-Total nets for routing : 27066.
-Global routing takes 5.95 sec.
-Detailed routing takes 30.09 sec.
-Hold Violation Fix in router takes 4.84 sec.
-Finish routing takes 1.48 sec.
-Hold violation fix takes 2.00 sec.
+Building routing graph takes 2.25 sec.
+Processing design graph takes 2.03 sec.
+Total nets for routing : 27114.
+Global routing takes 8.94 sec.
+Detailed routing takes 37.05 sec.
+Hold Violation Fix in router takes 9.83 sec.
+Finish routing takes 1.53 sec.
+Hold violation fix takes 2.09 sec.
Cleanup routing takes 0.02 sec.
Routing done.
-Total routing takes 49.84 sec.
+Total routing takes 64.98 sec.
IO Port Info:
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -212,21 +212,21 @@ Device Utilization Summary :
+---------------------------------------------------------------------------+
| Use of APM | 23.5 | 84 | 28
| Use of BKCL | 4 | 4 | 100
-| Use of CLMA | 2694 | 6450 | 42
-| FF | 8356 | 38700 | 22
-| LUT | 8529 | 25800 | 34
-| LUT-FF pairs | 3368 | 25800 | 14
-| Use of CLMS | 1700 | 4250 | 40
-| FF | 5264 | 25500 | 21
-| LUT | 5415 | 17000 | 32
-| LUT-FF pairs | 2199 | 17000 | 13
+| Use of CLMA | 2666 | 6450 | 42
+| FF | 8349 | 38700 | 22
+| LUT | 8468 | 25800 | 33
+| LUT-FF pairs | 3365 | 25800 | 14
+| Use of CLMS | 1728 | 4250 | 41
+| FF | 5269 | 25500 | 21
+| LUT | 5482 | 17000 | 33
+| LUT-FF pairs | 2194 | 17000 | 13
| Distributed RAM | 88 | 17000 | 1
| Use of CRYSTAL | 0 | 2 | 0
| Use of DLL | 2 | 10 | 20
| Use of DQSL | 8 | 18 | 45
| Use of DRM | 98.5 | 134 | 74
| Use of FUSECODE | 0 | 1 | 0
-| Use of HARD0N1 | 1334 | 6672 | 20
+| Use of HARD0N1 | 1340 | 6672 | 21
| Use of HSST | 0 | 1 | 0
| Use of IO | 180 | 296 | 61
| IOBD | 32 | 64 | 50
@@ -254,7 +254,7 @@ Device Utilization Summary :
| Use of SCANCHAIN | 0 | 2 | 0
| Use of START | 1 | 1 | 100
| Use of UDID | 0 | 1 | 0
-| Use of USCM | 16 | 30 | 54
+| Use of USCM | 17 | 30 | 57
| USCM dataused | 0 | 30 | 0
| Use of USCMMUX_TEST | 0 | 30 | 0
| Use of VCKBMUX_TEST | 0 | 12 | 0
@@ -265,18 +265,19 @@ Global Clock Info:
| GClk Inst | Site Of GClk Inst | GClk Fanout Net | Clock Loads | Non_Clock Loads | Driver Inst | Driver Pin | Site Of Driver Inst
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| clkbufg_0/gopclkbufg | USCM_84_116 | ntclkbufg_0 | 5446 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | IOCKDIV_6_323
-| clkbufg_1/gopclkbufg | USCM_84_108 | ntclkbufg_1 | 2506 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT0 | PLL_158_55
+| clkbufg_1/gopclkbufg | USCM_84_108 | ntclkbufg_1 | 2505 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT0 | PLL_158_55
| clkbufg_2/gopclkbufg | USCM_84_117 | ntclkbufg_2 | 1633 | 0 | U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | PLL_158_303
-| clkbufg_3/gopclkbufg | USCM_84_110 | ntclkbufg_3 | 233 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT4 | PLL_158_55
-| clkbufg_4/gopclkbufg | USCM_84_111 | ntclkbufg_4 | 167 | 0 | hdmi_in_clk_ibuf/opit_1 | INCK | IOL_163_6
-| clkbufg_5/gopclkbufg | USCM_84_112 | ntclkbufg_5 | 118 | 0 | cmos1_pclk_ibuf/opit_1 | INCK | IOL_171_6
-| clkbufg_6/gopclkbufg | USCM_84_118 | ntclkbufg_6 | 118 | 0 | cmos2_pclk_ibuf/opit_1 | OUT | IOL_39_6
-| clkbufg_7/gopclkbufg | USCM_84_114 | ntclkbufg_7 | 26 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT3 | PLL_158_55
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | USCM_84_113 | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | 68 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT1 | PLL_158_55
+| clkbufg_3/gopclkbufg | USCM_84_118 | ntclkbufg_3 | 733 | 0 | U_HDMI_PLL/u_pll_e3/goppll | CLKOUT0 | PLL_158_303
+| clkbufg_4/gopclkbufg | USCM_84_110 | ntclkbufg_4 | 233 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT4 | PLL_158_55
+| clkbufg_5/gopclkbufg | USCM_84_111 | ntclkbufg_5 | 167 | 0 | hdmi_in_clk_ibuf/opit_1 | INCK | IOL_163_6
+| clkbufg_6/gopclkbufg | USCM_84_112 | ntclkbufg_6 | 118 | 0 | cmos1_pclk_ibuf/opit_1 | INCK | IOL_171_6
+| clkbufg_7/gopclkbufg | USCM_84_119 | ntclkbufg_7 | 118 | 0 | cmos2_pclk_ibuf/opit_1 | OUT | IOL_39_6
+| clkbufg_8/gopclkbufg | USCM_84_114 | ntclkbufg_8 | 26 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT3 | PLL_158_55
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | USCM_84_113 | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | 71 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT1 | PLL_158_55
| u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg | USCM_84_115 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk | 1 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT1 | PLL_158_199
-| u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | USCM_84_119 | u_ov5640/coms1_reg_config/clock_20k | 18 | 0 | u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | CLMA_182_12
-| u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | USCM_84_120 | u_ov5640/coms2_reg_config/clock_20k | 18 | 0 | u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | CLMA_182_25
-| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | USCM_84_109 | gmii_clk | 1860 | 0 | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | IOCKDLY_237_367
+| u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | USCM_84_120 | u_ov5640/coms1_reg_config/clock_20k | 18 | 0 | u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | CLMS_122_9
+| u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | USCM_84_121 | u_ov5640/coms2_reg_config/clock_20k | 18 | 0 | u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | CLMA_122_12
+| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | USCM_84_109 | gmii_clk | 1861 | 0 | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | IOCKDLY_237_367
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
PLL Clock Info:
@@ -284,23 +285,24 @@ PLL Clock Info:
| Pll Inst | Site Of Pll Inst | Pin | Net Of Pin | Clock Loads | Non_Clock Loads | Driver(Load) Inst | Driver(Load) Pin | Site Of Driver(Load) Inst
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKFB | U_HDMI_PLL/u_pll_e3/ntCLKFB | - | - | U_HDMI_PLL/u_pll_e3/goppll | CLK_INT_FB | PLL_158_303
-| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKIN1 | ntR3907 | - | - | USCMROUTE_0 | CLKOUT | USCM_84_154
-| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKIN2 | ntR2156 | - | - | GND_1215 | Z | HARD0N1_156_305
+| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKIN1 | ntR3950 | - | - | USCMROUTE_0 | CLKOUT | USCM_84_154
+| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKIN2 | ntR2187 | - | - | GND_1222 | Z | HARD0N1_156_305
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKFB | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/ntCLKFB | - | - | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLK_INT_FB | PLL_158_199
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKIN1 | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | - | - | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | USCM_84_113
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKIN2 | ntR2589 | - | - | GND_482 | Z | HARD0N1_156_197
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKIN2 | ntR2620 | - | - | GND_465 | Z | HARD0N1_156_197
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | PLL_158_179 | CLKFB | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/ntCLKFB | - | - | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | CLK_INT_FB | PLL_158_179
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | PLL_158_179 | CLKIN1 | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | - | - | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | USCM_84_113
-| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | PLL_158_179 | CLKIN2 | ntR2593 | - | - | GND_1216 | Z | HARD0N1_156_181
+| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | PLL_158_179 | CLKIN2 | ntR2624 | - | - | GND_1220 | Z | HARD0N1_156_181
| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKFB | u_sys_pll/u_pll_e3/ntCLKFB | - | - | u_sys_pll/u_pll_e3/goppll | CLK_INT_FB | PLL_158_55
| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKIN1 | _N69 | - | - | clk_ibuf/opit_1 | INCK | IOL_327_210
-| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKIN2 | ntR2973 | - | - | GND_1214 | Z | HARD0N1_156_57
+| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKIN2 | ntR3004 | - | - | GND_1221 | Z | HARD0N1_156_57
+| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKOUT0 | zoom_clk | 733 | 0 | ... | ... | ...
| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKOUT1 | nt_pix_clk | 1633 | 1 | ... | ... | ...
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKOUT0_WL | clkout0_wl_0 | 5447 | 0 | ... | ... | ...
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKOUT1 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll | 1 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg | CLK | USCM_84_115
| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | PLL_158_179 | CLKOUT0_WL | clkout0_wl_1 | 2 | 0 | ... | ... | ...
-| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT0 | rd3_clk | 2507 | 0 | ... | ... | ...
-| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT1 | zoom_clk | 810 | 0 | ... | ... | ...
+| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT0 | rd3_clk | 2506 | 0 | ... | ... | ...
+| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT1 | ddr_clk | 77 | 0 | ... | ... | ...
| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT3 | clk_25m | 26 | 0 | ... | ... | ...
| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT4 | clk_10m | 233 | 0 | ... | ... | ...
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -310,11 +312,11 @@ Device Utilization Summary Of Each Module:
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module Inst Name | LUT | FF | Distributed RAM | APM | DRM | CRYSTAL | DLL | DQSL | FUSECODE | HSST | IO | IOCKDIV | IOCKDLY | IOCKGATE | IPAL | OSC | PCIE | PLL | RCKB | RESCAL | SCANCHAIN | START | UDID | USCM
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-| multimedia_video_processor | 13929 | 13620 | 88 | 23.5 | 98.5 | 0 | 2 | 8 | 0 | 0 | 180 | 1 | 1 | 4 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 16
+| multimedia_video_processor | 13927 | 13618 | 88 | 23.5 | 98.5 | 0 | 2 | 8 | 0 | 0 | 180 | 1 | 1 | 4 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 17
| + U_HDMI_PLL | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0
-| + adjust_color_wrapper_inst | 1127 | 1096 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + adjust_color_inst | 1127 | 1018 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + convert_hsv2rgb_inst | 69 | 81 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + adjust_color_wrapper_inst | 1128 | 1096 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + adjust_color_inst | 1128 | 1018 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + convert_hsv2rgb_inst | 70 | 81 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + convert_rgb2hsv_inst | 1006 | 883 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + divider_inst_h | 415 | 268 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + g_sqrt_stepx[1].u_divider_step | 36 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
@@ -375,8 +377,8 @@ Device Utilization Summary Of Each Module:
| + U_ipml_fifo_ctrl | 61 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_sdpram | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + vector_to_matrix_inst | 32 | 145 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + image_filiter_inst2 | 946 | 856 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + hybrid_filter_inst | 727 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + image_filiter_inst2 | 945 | 856 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + hybrid_filter_inst | 726 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + gaussian_conv_b | 56 | 83 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + gaussian_conv_g | 65 | 98 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + gaussian_conv_r | 56 | 83 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
@@ -402,35 +404,35 @@ Device Utilization Summary Of Each Module:
| + U_ipml_fifo_ctrl | 61 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_sdpram | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + vector_to_matrix_inst | 32 | 145 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + ms72xx_ctl | 333 | 236 | 0 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + iic_dri_rx | 80 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + iic_dri_tx | 65 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + ms72xx_ctl | 332 | 236 | 0 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + iic_dri_rx | 81 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + iic_dri_tx | 64 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + ms7200_ctl | 100 | 54 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + ms7210_ctl | 88 | 62 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + param_manager_inst | 666 | 354 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + ms7210_ctl | 87 | 62 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + param_manager_inst | 672 | 354 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + key_debounce_key_left | 16 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + key_debounce_key_restore | 13 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + key_debounce_key_right | 14 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + param_filiter1_mode | 67 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + param_filiter1_mode | 69 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + key_debounce_inst1 | 14 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + key_debounce_inst2 | 14 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + param_filiter2_mode | 8 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + param_modify_H | 51 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + param_modify_S | 28 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + param_modify_V | 28 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + param_offsetX | 56 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + param_modify_H | 52 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + param_modify_S | 30 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + param_modify_V | 29 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + param_offsetX | 54 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + param_offsetY | 33 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + param_osd_char_height | 57 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + param_osd_char_width | 32 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + param_osd_char_height | 55 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + param_osd_char_width | 33 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + param_osd_startX | 55 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + param_osd_startY | 32 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + param_rotate | 47 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + param_rotate_A | 33 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + param_rotate | 49 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + param_rotate_A | 34 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + param_zoom | 33 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_axi_ddr_top | 5792 | 6000 | 88 | 0 | 30.5 | 0 | 1 | 8 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2
-| + I_ipsxb_ddr_top | 4006 | 4123 | 88 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2
+| + u_axi_ddr_top | 5801 | 6000 | 88 | 0 | 30.5 | 0 | 1 | 8 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2
+| + I_ipsxb_ddr_top | 4015 | 4123 | 88 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2
| + u_ddrp_rstn_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_ddrphy_top | 2351 | 2360 | 0 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 70 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + u_ddrphy_top | 2363 | 2360 | 0 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 70 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + ddrphy_calib_top | 323 | 236 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + calib_mux | 23 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + ddrphy_init | 136 | 92 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
@@ -440,41 +442,41 @@ Device Utilization Summary Of Each Module:
| + upcal | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + ddrphy_dfi | 311 | 613 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + ddrphy_dll_update_ctrl | 11 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + ddrphy_info | 98 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + ddrphy_reset_ctrl | 77 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + ddrphy_pll_lock_debounce | 44 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + ddrphy_info | 101 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + ddrphy_reset_ctrl | 86 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + ddrphy_pll_lock_debounce | 45 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_ddrphy_rstn_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_dll_rst_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + ddrphy_slice_top | 1526 | 1371 | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 70 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + i_dqs_group[0].u_ddrphy_data_slice | 478 | 308 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + i_dqs_group[0].u_ddrphy_data_slice | 479 | 308 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + data_slice_dqs_gate_cal | 147 | 69 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + dqs_gate_coarse_cal | 97 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + gatecal | 50 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + data_slice_wrlvl | 108 | 76 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + data_slice_wrlvl | 106 | 76 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + dqs_rddata_align | 45 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + dqsi_rdel_cal | 169 | 84 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + dqsi_rdel_cal | 172 | 84 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + wdata_path_adj | 9 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + i_dqs_group[1].u_ddrphy_data_slice | 332 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + i_dqs_group[1].u_ddrphy_data_slice | 336 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + data_slice_dqs_gate_cal | 83 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + dqs_gate_coarse_cal | 34 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + gatecal | 49 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + data_slice_wrlvl | 102 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + dqs_rddata_align | 44 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + data_slice_wrlvl | 105 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + dqs_rddata_align | 45 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + dqsi_rdel_cal | 98 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + wdata_path_adj | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + i_dqs_group[2].u_ddrphy_data_slice | 338 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + data_slice_dqs_gate_cal | 81 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + i_dqs_group[2].u_ddrphy_data_slice | 334 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + data_slice_dqs_gate_cal | 82 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + dqs_gate_coarse_cal | 34 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + gatecal | 47 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + data_slice_wrlvl | 107 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + gatecal | 48 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + data_slice_wrlvl | 106 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + dqs_rddata_align | 44 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + dqsi_rdel_cal | 101 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + dqsi_rdel_cal | 97 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + wdata_path_adj | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + i_dqs_group[3].u_ddrphy_data_slice | 341 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + i_dqs_group[3].u_ddrphy_data_slice | 340 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + data_slice_dqs_gate_cal | 82 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + dqs_gate_coarse_cal | 34 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + gatecal | 48 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + data_slice_wrlvl | 103 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + data_slice_wrlvl | 102 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + dqs_rddata_align | 44 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + dqsi_rdel_cal | 107 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + wdata_path_adj | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
@@ -482,15 +484,15 @@ Device Utilization Summary Of Each Module:
| + u_logic_rstn_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_slice_rddata_align | 5 | 260 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + ddrphy_training_ctrl | 5 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_ipsxb_ddrc_top | 1654 | 1761 | 88 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + u_ipsxb_ddrc_top | 1651 | 1761 | 88 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + mcdq_calib_delay | 0 | 46 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + mcdq_cfg_apb | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + mcdq_dcd_top | 179 | 158 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + mcdq_dcd_top | 178 | 158 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + mcdq_dcd_bm | 128 | 80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + mcdq_dcd_rowaddr | 17 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + mcdq_dcd_sm | 51 | 78 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + mcdq_dcp_top | 854 | 626 | 82 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + mcdq_dcp_back_ctrl | 545 | 406 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + mcdq_dcd_rowaddr | 12 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + mcdq_dcd_sm | 50 | 78 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + mcdq_dcp_top | 852 | 626 | 82 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + mcdq_dcp_back_ctrl | 543 | 406 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + PRE_PASS_LOOP[0].timing_pre_pass | 21 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + PRE_PASS_LOOP[1].timing_pre_pass | 21 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + PRE_PASS_LOOP[2].timing_pre_pass | 21 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
@@ -507,7 +509,7 @@ Device Utilization Summary Of Each Module:
| + TRC_LOOP[5].trc_timing | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + TRC_LOOP[6].trc_timing | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + TRC_LOOP[7].trc_timing | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + TRDA2ACT_LOOP[0].trda2act_timing | 8 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + TRDA2ACT_LOOP[0].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + TRDA2ACT_LOOP[1].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + TRDA2ACT_LOOP[2].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + TRDA2ACT_LOOP[3].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
@@ -523,15 +525,15 @@ Device Utilization Summary Of Each Module:
| + TWRA2ACT_LOOP[5].twra2act_timing | 9 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + TWRA2ACT_LOOP[6].twra2act_timing | 9 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + TWRA2ACT_LOOP[7].twra2act_timing | 9 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + mcdq_timing_rd_pass | 11 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + mcdq_timing_rd_pass | 10 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + tfaw_timing | 26 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + TFAW_LOOP[0].mcdq_tfaw | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + TFAW_LOOP[1].mcdq_tfaw | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + TFAW_LOOP[2].mcdq_tfaw | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + timing_act_pass | 27 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + timing_prea_pass | 15 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + timing_prea_pass | 16 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + timing_ref_pass | 19 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + timing_wr_pass | 9 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + timing_wr_pass | 8 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + mcdq_dcp_buf | 244 | 159 | 82 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + A_ipsxb_distributed_fifo | 83 | 15 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_ipsxb_distributed_fifo_distributed_fifo_v1_0 | 83 | 15 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
@@ -551,7 +553,7 @@ Device Utilization Summary Of Each Module:
| + u_ipsxb_distributed_fifo_ctr | 31 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + mcdq_ui_axi | 218 | 345 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + mcdq_reg_fifo2 | 96 | 71 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_user_cmd_fifo | 41 | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + u_user_cmd_fifo | 42 | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + mcdq_wdatapath | 288 | 475 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + ipsxb_distributed_fifo | 27 | 14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_ipsxb_distributed_fifo_distributed_fifo_v1_0 | 27 | 14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
@@ -612,7 +614,7 @@ Device Utilization Summary Of Each Module:
| + U_ipml_sdpram | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_axi_rst | 2 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_clk50m_rst | 1 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_ddr_addr_ctr | 280 | 434 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + u_ddr_addr_ctr | 277 | 432 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_rd0_addr_ctr | 38 | 43 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_rd1_addr_ctr | 77 | 95 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_rd1_ddr_addr_fifo1 | 42 | 20 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
@@ -630,13 +632,13 @@ Device Utilization Summary Of Each Module:
| + u_hdm_in_rst | 2 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_hdmi_in_top | 9 | 79 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_hdmi_rst | 2 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_ov5640 | 453 | 504 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2
+| + u_ov5640 | 455 | 504 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2
| + cmos1_8_16bit | 3 | 47 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + cmos2_8_16bit | 3 | 47 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + coms1_reg_config | 61 | 36 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1
| + u1 | 29 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + coms2_reg_config | 61 | 36 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1
-| + u1 | 29 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + coms2_reg_config | 63 | 36 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1
+| + u1 | 31 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + power_on_delay_inst | 41 | 37 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_mix_image | 284 | 261 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_mix_fifo1 | 86 | 90 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
@@ -667,9 +669,9 @@ Device Utilization Summary Of Each Module:
| + U_ipml_sdpram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_sync_vg | 91 | 90 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_sys_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_zoom_hdmi_fifo | 166 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + U_ipml_fifo_zoom_hdmi_fifo | 166 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + U_ipml_fifo_ctrl | 165 | 138 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + u_zoom_hdmi_fifo | 148 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + U_ipml_fifo_zoom_hdmi_fifo | 148 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + U_ipml_fifo_ctrl | 147 | 138 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_sdpram | 1 | 1 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_zoom_image | 430 | 509 | 0 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + mult_fra0 | 0 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
@@ -707,41 +709,41 @@ Device Utilization Summary Of Each Module:
| + zoom_ram3_0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_sdpram_zoom_ram | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_zoom_rst | 1 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + udp_osd_inst | 2209 | 1831 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1
+| + udp_osd_inst | 2212 | 1831 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1
| + char_buf_writer_inst | 93 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + char_osd_inst | 262 | 215 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + char_buf_reader_inst | 175 | 129 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + char_pic_rom_inst | 42 | 47 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + char_buf_reader_inst | 176 | 129 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + char_pic_rom_inst | 41 | 47 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + ascii_char_rom_inst | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_rom_ascii_char_rom | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_spram_ascii_char_rom | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + pixels_shifter_inst | 45 | 39 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + char_ram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_sdpram_async_ram2048x8_2clk | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + eth_udp_inst | 1818 | 1541 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1
+| + eth_udp_inst | 1821 | 1541 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1
| + icmp_async_fifo_2048x8b | 97 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_fifo_async_fifo_2048x8 | 97 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_fifo_ctrl | 97 | 98 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_sdpram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_arp | 423 | 424 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_arp_rx | 215 | 278 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + u_arp | 422 | 424 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + u_arp_rx | 214 | 278 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_arp_tx | 154 | 114 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_crc32_d8 | 54 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_eth_ctrl | 12 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_gmii_to_rgmii | 0 | 9 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1
-| + u_icmp | 927 | 628 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + u_icmp | 929 | 628 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_crc32_d8 | 55 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + u_icmp_rx | 288 | 284 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_icmp_tx | 584 | 312 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_udp | 161 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + u_udp_rx | 161 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + u_icmp_tx | 586 | 312 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + u_udp | 163 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + u_udp_rx | 163 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + udp_receive_buffer_inst | 193 | 175 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + udp_rx_done_cdc | 3 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + udp_rx_fifo | 107 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_fifo_async_fifo_2048x8 | 107 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_fifo_ctrl | 107 | 98 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
| + U_ipml_sdpram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
-| + udp_wr_mem_inst | 105 | 190 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+| + udp_wr_mem_inst | 106 | 190 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -763,7 +765,7 @@ Inputs and Outputs :
Flow Command: pnr -fix_hold_violation
-Peak memory: 1,902 MB
-Total CPU time to pnr completion : 0h:2m:39s
-Process Total CPU time to pnr completion : 0h:4m:9s
-Total real time to pnr completion : 0h:2m:46s
+Peak memory: 1,901 MB
+Total CPU time to pnr completion : 0h:2m:59s
+Process Total CPU time to pnr completion : 0h:4m:43s
+Total real time to pnr completion : 0h:3m:5s
diff --git a/project/place_route/multimedia_video_processor_plc.adf b/project/place_route/multimedia_video_processor_plc.adf
index d0f2560..66e85ca 100644
Binary files a/project/place_route/multimedia_video_processor_plc.adf and b/project/place_route/multimedia_video_processor_plc.adf differ
diff --git a/project/place_route/multimedia_video_processor_pnr.adf b/project/place_route/multimedia_video_processor_pnr.adf
index dcffcaf..98ab1c0 100644
Binary files a/project/place_route/multimedia_video_processor_pnr.adf and b/project/place_route/multimedia_video_processor_pnr.adf differ
diff --git a/project/place_route/multimedia_video_processor_pnr.netlist b/project/place_route/multimedia_video_processor_pnr.netlist
index 2e1b8a1..6395a53 100644
--- a/project/place_route/multimedia_video_processor_pnr.netlist
+++ b/project/place_route/multimedia_video_processor_pnr.netlist
@@ -246,33 +246,36 @@ L3;1
L4;1
Inst
-N24_mux18_3/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-sync_vg_100m/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[15]/opit_0_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[10]/gateop_perm;gopLUT5
+Pin
+Z;2
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-N298_9/gateop_perm;gopLUT5
+N104_mux11_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -282,7 +285,7 @@ L3;1
L4;1
Inst
-N298_11/gateop_perm;gopLUT5
+N299_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -292,7 +295,7 @@ L3;1
L4;1
Inst
-N298_12/gateop_perm;gopLUT5
+N299_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -402,20 +405,23 @@ I13;1
I14;1
Inst
-N108_0.fsub_11/gateop;gopA
+u_ddr_addr_ctr/u_wr1_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-N328_9/gateop_perm;gopLUT5
+N119_mux11_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -425,7 +431,7 @@ L3;1
L4;1
Inst
-N328_11/gateop_perm;gopLUT5
+N329_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -435,7 +441,7 @@ L3;1
L4;1
Inst
-N328_10/gateop_perm;gopLUT5
+N329_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -564,7 +570,7 @@ Z;2
I;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_24/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -574,7 +580,7 @@ L3;1
L4;1
Inst
-N285_10/gateop_perm;gopLUT5
+N286_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -584,17 +590,23 @@ L3;1
L4;1
Inst
-N285_11/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-rstn_1ms[0]/opit_0_inv_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -610,7 +622,7 @@ L4;1
RS;1
Inst
-vs_down_delay_cnt[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd1_addr_start_fall/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -626,20 +638,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N161.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-vs_down_delay_cnt[10]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -655,7 +654,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N104_40/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/u1/N256_2_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -665,7 +664,17 @@ L3;1
L4;1
Inst
-vs_down_delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
+N329_11/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+wr0_vs/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -681,14 +690,20 @@ L4;1
RS;1
Inst
-N119_mux11_9/gateop_perm;gopLUT5
+vs_down_delay_cnt[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
U_HDMI_PLL/u_pll_e3/goppll;gopPLL
@@ -863,16 +878,6 @@ RATIOM[6];1
RST;1
RSTODIV;1
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N241_4_4/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm;gopAPM2
Pin
@@ -1057,7 +1062,7 @@ Z[22];1
Z[23];1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N19_mux2_2/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N155_18/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -1067,7 +1072,7 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[6]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N53_mux2_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -1077,20 +1082,14 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm;gopAPM
@@ -1426,7 +1425,7 @@ Z[46];1
Z[47];1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -1442,7 +1441,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[0]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -1452,23 +1451,17 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[1]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -1478,7 +1471,7 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[4]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -1488,7 +1481,7 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N19_inv_1/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -1598,23 +1591,17 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[0]/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/N102_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -1624,14 +1611,36 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[3]/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_left/pluse_ms/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff1[1]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[4]/gateop_perm;gopLUT5
@@ -1644,7 +1653,7 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_51/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_45/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -1654,23 +1663,17 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff1[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -2526,20 +2529,14 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff1[2]/opit_0_L5Q_perm;gopL5Q
@@ -2558,20 +2555,14 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_restore/N20_mux4_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff2[0]/opit_0;gopQ
@@ -2936,7 +2927,7 @@ I13;1
I14;1
Inst
-param_manager_inst/param_modify_S/N63_mux8_7/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N133_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -2946,30 +2937,30 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5
+param_manager_inst/param_modify_V/value[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_sync_vg/hdmi_image_data0[13]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N153_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N153_12/gateop_perm;gopLUT5
@@ -2982,7 +2973,7 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3402,20 +3393,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/N20.fsub_8/gateop;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3431,7 +3409,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3447,7 +3425,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3463,7 +3441,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3479,7 +3457,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3495,7 +3473,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3511,7 +3489,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3527,7 +3505,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3543,7 +3521,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3575,7 +3553,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3591,7 +3569,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3607,7 +3585,20 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/N20.fsub_8/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3623,7 +3614,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3650,7 +3641,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3666,7 +3657,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3682,7 +3673,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_right/pressed/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3698,7 +3689,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3714,7 +3705,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3730,7 +3721,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3746,23 +3737,26 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[7]/opit_0_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3911,7 +3905,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3927,7 +3921,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3943,7 +3937,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3959,7 +3953,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3975,7 +3969,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -3991,7 +3985,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4023,7 +4017,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4039,7 +4033,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4055,7 +4049,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4071,7 +4065,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4087,7 +4081,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4103,7 +4097,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[6]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4119,7 +4113,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4146,7 +4140,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4162,7 +4156,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4178,7 +4172,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4194,7 +4188,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4210,20 +4204,14 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
@@ -4242,20 +4230,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/N20.fsub_8/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4270,6 +4245,16 @@ L3;1
L4;1
RS;1
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[2]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/N6.lt_0/gateop_A2;gopA2
Pin
@@ -4404,20 +4389,14 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
@@ -4436,7 +4415,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4452,7 +4431,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4468,7 +4447,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4484,7 +4463,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4500,7 +4479,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4516,7 +4495,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4548,7 +4527,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4564,7 +4543,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4580,7 +4559,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4596,7 +4575,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4639,7 +4618,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4655,7 +4634,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4671,7 +4650,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4719,7 +4698,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4735,20 +4714,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/N20.fsub_8/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/N6.lt_0/gateop_A2;gopA2
@@ -4884,7 +4860,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4900,7 +4876,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4916,7 +4892,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4932,7 +4908,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4948,7 +4924,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -4993,7 +4969,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5009,7 +4985,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5025,7 +5001,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_h_data[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5041,23 +5017,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/N102_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5100,20 +5070,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N20.fsub_8/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5129,7 +5086,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[2]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5145,7 +5102,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5161,7 +5118,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5177,7 +5134,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5193,7 +5150,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5208,6 +5165,19 @@ L3;1
L4;1
RS;1
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N20.fsub_8/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N6.lt_0/gateop_A2;gopA2
Pin
@@ -5249,17 +5219,20 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N6.lt_4/gateop;gopA
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N20.fsub_0/gateop_A2;gopA2
@@ -5342,7 +5315,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5358,7 +5331,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5374,7 +5347,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5422,7 +5395,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5438,7 +5411,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5454,7 +5427,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5486,7 +5459,7 @@ L4;1
RS;1
Inst
-u_sync_vg/hdmi_image_data0[11]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5502,7 +5475,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5518,20 +5491,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N6.lt_4/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/rdy/opit_0;gopQ
@@ -5577,7 +5547,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5593,7 +5563,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[3]/opit_0_L5Q;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5609,7 +5579,20 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/N20.fsub_8/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5625,7 +5608,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[6]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5641,7 +5624,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5656,19 +5639,6 @@ L3;1
L4;1
RS;1
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/N20.fsub_8/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/N6.lt_0/gateop_A2;gopA2
Pin
@@ -5803,7 +5773,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5819,7 +5789,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5835,7 +5805,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5851,7 +5821,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5867,7 +5837,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5883,7 +5853,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5899,7 +5869,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5915,7 +5885,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5931,7 +5901,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5963,7 +5933,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -5979,7 +5949,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6006,7 +5976,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6022,20 +5992,23 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/N6.lt_4/gateop_perm;gopA
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6051,7 +6024,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6067,7 +6040,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6096,7 +6069,7 @@ I3;1
I4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6112,20 +6085,14 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N133_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/N6.lt_0/gateop_A2;gopA2
@@ -6168,20 +6135,17 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/N6.lt_4/gateop;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/N20.fsub_0/gateop_A2;gopA2
@@ -6264,7 +6228,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6280,7 +6244,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6296,7 +6260,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6328,7 +6292,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6344,7 +6308,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6360,7 +6324,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6376,7 +6340,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6392,20 +6356,14 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_left/N47_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
@@ -6424,7 +6382,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6440,7 +6398,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6467,7 +6425,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6483,7 +6441,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6499,7 +6457,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6515,7 +6473,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_left/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6531,7 +6489,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6547,7 +6505,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6563,7 +6521,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6579,20 +6537,14 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_left/N87/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N6.lt_0/gateop_A2;gopA2
@@ -6728,7 +6680,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6744,7 +6696,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6760,7 +6712,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6776,7 +6728,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6792,7 +6744,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6808,7 +6760,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6824,7 +6776,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6840,23 +6792,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/N63_mux6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6888,7 +6834,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6904,7 +6850,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6931,7 +6877,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6947,7 +6893,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6963,7 +6909,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6979,7 +6925,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[3]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -6995,7 +6941,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7011,7 +6957,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7027,7 +6973,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7192,7 +7138,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7208,7 +7154,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7224,7 +7170,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[2]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7240,7 +7186,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7272,7 +7218,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7288,7 +7234,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7304,7 +7250,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7320,7 +7266,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7336,7 +7282,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7352,7 +7298,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7368,7 +7314,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7384,7 +7330,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7411,7 +7357,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7427,7 +7373,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7443,7 +7389,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7459,7 +7405,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7491,7 +7437,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff1[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7507,7 +7453,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7523,7 +7469,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7720,7 +7666,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7736,7 +7682,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7784,7 +7730,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7800,7 +7746,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7816,7 +7762,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7832,7 +7778,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7848,7 +7794,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7864,7 +7810,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7880,7 +7826,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7907,7 +7853,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7923,7 +7869,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7939,7 +7885,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -7955,7 +7901,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8003,7 +7949,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_zoom/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8019,14 +7965,20 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[1]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N6.lt_0/gateop_A2;gopA2
@@ -8162,7 +8114,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8178,7 +8130,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[1]/opit_0_L5Q;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8194,7 +8146,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8210,7 +8162,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8226,7 +8178,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8242,20 +8194,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/N6.lt_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8271,7 +8210,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8287,7 +8226,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8303,7 +8242,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8319,7 +8258,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8335,7 +8274,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8351,7 +8290,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8367,7 +8306,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8383,7 +8322,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/N20_mux4_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8410,7 +8359,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8426,23 +8375,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N364/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8458,17 +8401,23 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N2076/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8484,7 +8433,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8500,7 +8449,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[2]/gateop_perm;gopLUT5
+u_zoom_image/N322_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -8510,14 +8459,20 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[3]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/N6.lt_0/gateop_A2;gopA2
@@ -8560,7 +8515,20 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/N6.lt_4/gateop;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8576,23 +8544,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_zoom/N63_mux9_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8608,7 +8570,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/opit_0_inv_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8624,7 +8586,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8640,17 +8602,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N155_18/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8666,7 +8618,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8682,17 +8634,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/N6_mux7_8/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/N6_mux7_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -8702,7 +8660,7 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8754,7 +8712,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8770,7 +8728,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8786,23 +8744,26 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[7]/opit_0_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8818,7 +8779,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8834,7 +8795,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[0]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/data_out_valid1/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8850,7 +8811,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8866,7 +8827,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8882,7 +8843,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8898,7 +8859,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8930,7 +8891,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8946,23 +8907,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_right/N20_mux2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_right/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -8989,7 +8944,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9086,23 +9041,14 @@ I14;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[7]/opit_0_AQ;gopAQ
+param_manager_inst/key_debounce_key_right/N47_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/N6.lt_0/gateop_A2;gopA2
@@ -9238,7 +9184,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9254,7 +9200,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9270,7 +9216,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9286,7 +9232,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9302,7 +9248,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9318,7 +9264,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9334,7 +9280,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9366,7 +9312,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9382,20 +9328,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/N20.fsub_8/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9411,7 +9344,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[3]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9427,7 +9360,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9443,7 +9376,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9459,7 +9392,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9475,7 +9408,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/N126/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9491,7 +9434,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9507,7 +9450,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9539,7 +9482,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9555,7 +9498,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9571,20 +9514,23 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/N20.fsub_8/gateop_perm;gopA
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9733,7 +9679,7 @@ I13;1
I14;1
Inst
-u_sync_vg/hdmi_image_data0[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9749,7 +9695,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9765,20 +9711,23 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/N20.fsub_8/gateop_perm;gopA
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9794,7 +9743,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9810,14 +9759,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
@@ -9852,7 +9807,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9884,7 +9839,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9900,7 +9855,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9916,7 +9871,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9932,7 +9887,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9948,20 +9903,23 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/N20.fsub_8/gateop_perm;gopA
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -9977,7 +9935,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10009,7 +9967,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10025,7 +9983,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[5]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10041,7 +9999,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[6]/opit_0_L5Q;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10057,7 +10015,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10206,7 +10164,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10222,7 +10180,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10238,7 +10196,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10254,7 +10212,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10270,7 +10228,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10318,23 +10276,20 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/N20.fsub_8/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10350,7 +10305,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10366,7 +10321,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10382,7 +10337,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10398,7 +10353,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[13]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10430,7 +10385,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10446,7 +10401,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10478,7 +10433,20 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/N20.fsub_8/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10494,7 +10462,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10510,20 +10478,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/N20.fsub_8/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10672,7 +10627,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10688,7 +10643,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[8]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10704,7 +10659,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10720,7 +10675,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10768,17 +10723,23 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/N6_mux7_8/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10794,7 +10755,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10810,7 +10771,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10826,7 +10787,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10842,7 +10803,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10858,7 +10819,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10874,7 +10835,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10890,7 +10851,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10906,7 +10867,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10922,7 +10883,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10954,7 +10915,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -10970,14 +10931,20 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/N6_mux7_7/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/N6.lt_0/gateop_A2;gopA2
@@ -11113,23 +11080,20 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/N20.fsub_8/gateop;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11145,7 +11109,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11161,7 +11125,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11177,7 +11141,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11193,7 +11157,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11225,7 +11189,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11241,7 +11205,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11257,20 +11221,23 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/N20.fsub_8/gateop_perm;gopA
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11302,7 +11269,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11318,7 +11285,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11334,7 +11301,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11350,7 +11317,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11366,7 +11333,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11382,7 +11349,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11398,7 +11365,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11547,7 +11514,20 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/N20.fsub_8/gateop;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11563,7 +11543,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11579,23 +11559,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N306_11/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11611,20 +11585,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/N20.fsub_8/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11640,7 +11601,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11656,7 +11617,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11672,7 +11633,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/flags[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11704,7 +11665,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11720,7 +11681,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11736,7 +11697,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11800,7 +11761,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11816,7 +11777,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11965,7 +11926,7 @@ I13;1
I14;1
Inst
-udp_osd_inst/rgb_out[16]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -11981,7 +11942,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12013,7 +11974,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12029,7 +11990,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12061,7 +12022,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12077,7 +12038,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12109,7 +12070,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12157,7 +12118,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12205,7 +12166,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12221,20 +12182,23 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6.lt_4/gateop_perm;gopA
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12290,20 +12254,17 @@ I13;1
I14;1
Inst
-udp_osd_inst/rgb_out[10]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6.lt_4/gateop;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N20_1.fsub_0/gateop_A2;gopA2
@@ -12386,7 +12347,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12402,7 +12363,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12418,7 +12379,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12434,7 +12395,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12450,7 +12411,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12482,7 +12443,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12498,7 +12459,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12514,7 +12475,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12530,7 +12491,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12546,7 +12507,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12562,7 +12523,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12578,7 +12539,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12594,7 +12555,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12610,7 +12571,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12626,7 +12587,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12642,7 +12603,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12658,7 +12619,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12807,7 +12768,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12823,7 +12784,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12855,7 +12816,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12871,7 +12832,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12887,7 +12848,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12903,7 +12864,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12935,7 +12896,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12951,7 +12912,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12967,7 +12928,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -12983,7 +12944,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13015,7 +12976,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13031,7 +12992,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13047,7 +13008,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13063,7 +13024,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/wr_addr2[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13079,7 +13040,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13095,7 +13056,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13244,7 +13205,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13260,7 +13221,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13276,7 +13237,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13292,7 +13253,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[3]/opit_0_L5Q;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13308,7 +13269,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13324,7 +13285,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[5]/opit_0_L5Q;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13372,7 +13333,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13388,7 +13349,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13420,7 +13381,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13436,7 +13397,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13452,7 +13413,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13468,7 +13429,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13484,7 +13445,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13516,7 +13477,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13532,7 +13493,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13548,7 +13509,7 @@ L4;1
RS;1
Inst
-u_sync_vg/hdmi_image_data0[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13713,7 +13674,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13729,7 +13690,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13745,7 +13706,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/ram_sta_reg[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13777,7 +13738,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13793,7 +13754,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13809,7 +13770,7 @@ L4;1
RS;1
Inst
-u_sync_vg/pixel_show_en1/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13825,7 +13786,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13841,7 +13802,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13857,7 +13818,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13873,17 +13834,23 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_21/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13899,7 +13866,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13915,7 +13882,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13931,7 +13898,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13947,7 +13914,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13963,7 +13930,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13979,7 +13946,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -13995,7 +13962,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[6]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14011,7 +13978,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14160,7 +14127,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14176,7 +14143,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14192,7 +14159,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14208,7 +14175,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14224,7 +14191,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14240,7 +14207,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14256,7 +14223,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14272,7 +14239,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14288,7 +14255,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14304,7 +14271,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14320,7 +14287,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14336,17 +14303,23 @@ L4;1
RS;1
Inst
-N162_mux3/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14362,14 +14335,20 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/rdy/opit_0;gopQ
@@ -14383,7 +14362,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14399,7 +14378,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14431,7 +14410,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14447,7 +14426,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14463,7 +14442,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14479,7 +14458,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/offsetY_load/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14495,7 +14474,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14644,7 +14623,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14660,7 +14639,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14676,17 +14655,23 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N53_mux2_inv/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14702,7 +14687,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14718,7 +14703,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14734,7 +14719,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14766,7 +14751,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14782,7 +14767,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14798,7 +14783,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14814,7 +14799,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14830,7 +14815,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14846,7 +14831,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14862,7 +14847,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[6]/opit_0_L5Q;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14889,7 +14874,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14905,7 +14890,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14921,7 +14906,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -14937,7 +14922,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15001,20 +14986,14 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/N149/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/N6.lt_0/gateop_A2;gopA2
@@ -15057,20 +15036,17 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/N6.lt_4/gateop;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/N20_1.fsub_0/gateop_A2;gopA2
@@ -15153,7 +15129,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15169,7 +15145,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15185,7 +15161,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15201,7 +15177,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15217,7 +15193,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15233,7 +15209,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15249,7 +15225,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15265,7 +15241,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15281,23 +15257,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_V/N139_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15313,7 +15283,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15329,23 +15299,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N344/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15361,7 +15325,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15393,14 +15357,20 @@ L4;1
RS;1
Inst
-u_sync_vg/N126/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/rdy/opit_0;gopQ
@@ -15414,7 +15384,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15430,7 +15400,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15446,7 +15416,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15462,7 +15432,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15478,7 +15448,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15494,7 +15464,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15510,7 +15480,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15526,7 +15496,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/offsetX_load/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15595,7 +15565,7 @@ I3;1
I4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15611,7 +15581,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15627,7 +15597,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15643,7 +15613,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15659,7 +15629,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/index[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15675,23 +15645,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/N47_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[8]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15707,17 +15671,23 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_12/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_10/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/N20_mux2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -15727,36 +15697,24 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/N6_mux7_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/rgb_out[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/N6_mux7_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/N20.fsub_0/gateop_A2;gopA2
@@ -15779,7 +15737,7 @@ I13;1
I14;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15795,7 +15753,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15811,17 +15769,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N153_6/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15837,7 +15785,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[13]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/flags[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15869,7 +15817,20 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/N20.fsub_8/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15885,7 +15846,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15901,7 +15862,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15917,7 +15878,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15933,7 +15894,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15949,7 +15910,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15965,7 +15926,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15981,7 +15942,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -15997,7 +15958,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/N20.fsub_8/gateop_perm;gopA
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/N20.fsub_8/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -16010,14 +15971,20 @@ I3;1
I4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/N6_mux7_7/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21;gopA2Q2
@@ -16101,22 +16068,19 @@ I14;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[7]/opit_0_AQ;gopAQ
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
-Cout;2
Q;2
RSOUT;2
-Y;2
+Z;2
CE;1
CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
@@ -16224,7 +16188,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/flags[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -16240,14 +16204,20 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N140_7/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/flags_d0[0]/opit_0;gopQ
@@ -17417,7 +17387,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/flags[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -17433,7 +17403,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -17449,7 +17419,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -17465,39 +17435,27 @@ L4;1
RS;1
Inst
-udp_osd_inst/rgb_out[13]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N140_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[6]/opit_0_L5Q_perm;gopL5Q
+N286_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -17513,7 +17471,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/rgb_out[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -17529,7 +17487,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -17752,7 +17710,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -17784,20 +17742,14 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N76_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[5]/opit_0_L5Q_perm;gopL5Q
@@ -17816,7 +17768,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -17848,7 +17800,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -19393,7 +19345,7 @@ D;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N76_inv/gateop_perm;gopLUT5
+param_manager_inst/param_modify_S/N139_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -19403,7 +19355,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
+param_manager_inst/param_modify_V/N76_mux8_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -19413,23 +19365,17 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N76_inv/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N76_7/gateop_perm;gopLUT5
+param_manager_inst/param_modify_S/N63_mux8_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -19656,7 +19602,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+param_manager_inst/param_modify_H/N102_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -19666,7 +19612,7 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -19698,7 +19644,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[6]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -19714,7 +19660,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[4]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -19746,7 +19692,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -19762,7 +19708,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/change/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -19778,23 +19724,17 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/N156_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -19842,7 +19782,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -19858,7 +19798,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -19906,7 +19846,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -21797,7 +21737,13 @@ CLKOUT;2
CLK;1
Inst
-clkgate_8/gopclkgate;gopCLKGATE
+clkbufg_8/gopclkbufg;gopCLKBUFG
+Pin
+CLKOUT;2
+CLK;1
+
+Inst
+clkgate_9/gopclkgate;gopCLKGATE
Pin
OUT;2
CLK;1
@@ -23005,14 +22951,20 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/N99.fsub_1/gateop_A2;gopA2
@@ -23055,7 +23007,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -23071,20 +23036,17 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N39.lt_2/gateop_perm;gopA
+param_manager_inst/param_filiter1_mode/N153/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-param_manager_inst/param_modify_S/N148_2/gateop_perm;gopLUT5
+param_manager_inst/param_filiter2_mode/N152_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -23094,7 +23056,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_ac5/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -23104,7 +23066,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/N134_72/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N104_40/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -23174,7 +23136,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/N162_72/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -23184,7 +23146,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/N162_76/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -23194,7 +23156,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/N162_76/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -23203,6 +23165,19 @@ L2;1
L3;1
L4;1
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
Inst
image_filiter_inst/hybrid_filter_inst/N155.fsub_1/gateop_A2;gopA2
Pin
@@ -23244,27 +23219,7 @@ I13;1
I14;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[0]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac4/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -23274,17 +23229,20 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N424/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_maj3/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N176_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -23294,7 +23252,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_ac5/gateop;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -23304,7 +23262,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/N102_11/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_maj3/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -24591,7 +24549,7 @@ I4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -24604,20 +24562,17 @@ I3;1
I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac6/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_hdm_in_rst/N0/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -24627,17 +24582,14 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_7/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N47_1_1/gateop_A2;gopA2
@@ -25032,14 +24984,23 @@ I14;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/N259/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ;gopAQ
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/opit_0;gopQ
@@ -26124,7 +26085,7 @@ I14;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/N56/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_maj3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -26134,17 +26095,20 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_maj3/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_ac5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -27462,17 +27426,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N155.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/N37.lt_0/gateop_A2;gopA2
@@ -27495,17 +27462,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N35.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/N39.lt_0/gateop_A2;gopA2
@@ -27528,20 +27498,14 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/N83.lt_0/gateop_A2;gopA2
@@ -27564,7 +27528,7 @@ I13;1
I14;1
Inst
-clk_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -27600,7 +27564,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -27636,17 +27600,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N87.lt_2/gateop;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N83.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N155.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -27679,7 +27646,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -27709,17 +27676,14 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N161.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/N146_mux2_3/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/N111.lt_0/gateop_A2;gopA2
@@ -27742,17 +27706,14 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N107.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/N155.lt_0/gateop_A2;gopA2
@@ -27775,7 +27736,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N188_40/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/N12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -27805,7 +27766,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N167.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N39.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -27838,36 +27799,24 @@ I13;1
I14;1
Inst
-u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm;gopL5Q
+u_hdmi_in_top/N3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/cnt0_w[8]/opit_0_L5Q_perm;gopL5Q
+N104_mux11_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_0/gateop_A2;gopA2
@@ -27890,14 +27839,17 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N109.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_0/gateop_A2;gopA2
@@ -27920,14 +27872,17 @@ I13;1
I14;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/N155.fsub_5/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -27950,14 +27905,17 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_7/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N111.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -27980,59 +27938,30 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N167.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -28045,7 +27974,7 @@ I3;1
I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N107.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -28057,6 +27986,32 @@ I2;1
I3;1
I4;1
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
Pin
@@ -28175,23 +28130,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -28217,7 +28156,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -28233,7 +28172,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -28249,7 +28188,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -28265,7 +28204,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N37.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -28278,7 +28217,20 @@ I3;1
I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -28314,7 +28266,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -28344,7 +28296,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -28374,17 +28326,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -28407,39 +28362,30 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+u_ov5640/power_on_delay_inst/N15_mux15_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -28449,23 +28395,30 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/rd1_data_valid0/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -28480,16 +28433,6 @@ L3;1
L4;1
RS;1
-Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_78/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
Pin
@@ -28576,20 +28519,7 @@ S0;1
S1;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N87.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -28637,7 +28567,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N161.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -28649,6 +28579,16 @@ I2;1
I3;1
I4;1
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
@@ -28666,17 +28606,23 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -28692,7 +28638,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N104_40/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -28702,20 +28648,17 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N35.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_0/gateop_A2;gopA2
@@ -28738,20 +28681,17 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_0/gateop_A2;gopA2
@@ -28774,14 +28714,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -28804,20 +28750,14 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -28840,17 +28780,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_7/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -28860,7 +28790,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -28873,7 +28803,7 @@ I3;1
I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -28889,17 +28819,20 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -28911,6 +28844,22 @@ I2;1
I3;1
I4;1
+Inst
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
Pin
@@ -28997,7 +28946,7 @@ S0;1
S1;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -29013,7 +28962,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[38]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -29029,7 +28978,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -29045,20 +28994,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -29074,7 +29010,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -29090,7 +29026,20 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N83.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -29106,7 +29055,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N37.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N85.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -29119,30 +29068,36 @@ I3;1
I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N39.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N85.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[0]/opit_0;gopQ
@@ -29785,7 +29740,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -29821,7 +29776,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N37.lt_2/gateop;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N155.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -29887,7 +29842,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N188_40/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -29917,20 +29872,17 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N85.lt_2/gateop;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/N87.lt_0/gateop_A2;gopA2
@@ -29953,23 +29905,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N87.lt_2/gateop;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N85.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N83.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -30002,14 +29951,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/N114_mux5_4/gateop_perm;gopLUT5
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/N109.lt_0/gateop_A2;gopA2
@@ -30032,14 +29987,17 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac5/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/N111.lt_0/gateop_A2;gopA2
@@ -30062,20 +30020,17 @@ I13;1
I14;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N111.lt_2/gateop;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/N155.lt_0/gateop_A2;gopA2
@@ -30098,7 +30053,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N167.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N161.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -30131,20 +30086,14 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/N114_mux5_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/N167.lt_0/gateop_A2;gopA2
@@ -30167,23 +30116,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N35.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/N118_mux3_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -30213,20 +30159,14 @@ I13;1
I14;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_0/gateop_A2;gopA2
@@ -30249,7 +30189,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop;gopA
Pin
Cout;2
Y;2
@@ -30282,14 +30222,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -30312,23 +30258,17 @@ I13;1
I14;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N104_40/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -30338,23 +30278,20 @@ L3;1
L4;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/N188_40/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -30364,7 +30301,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -30492,20 +30429,7 @@ S0;1
S1;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -30521,7 +30445,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -30537,17 +30461,23 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/N118_mux3_4/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -30563,7 +30493,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -30594,6 +30524,16 @@ L3;1
L4;1
RS;1
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q
Pin
@@ -30611,33 +30551,17 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N107.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_maj3/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -30665,6 +30589,19 @@ I2;1
I3;1
I4;1
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_0/gateop_A2;gopA2
Pin
@@ -30686,20 +30623,14 @@ I13;1
I14;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_0/gateop_A2;gopA2
@@ -30722,7 +30653,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N109.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop;gopA
Pin
Cout;2
Y;2
@@ -30755,7 +30686,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_maj3/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/N134_78/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -30785,7 +30716,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac6/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -30795,7 +30726,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -30805,7 +30736,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -30815,7 +30746,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_7/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -30828,30 +30769,17 @@ I3;1
I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -30972,20 +30900,14 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
@@ -31004,7 +30926,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31020,7 +30942,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31036,20 +30958,14 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/N134_72/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
@@ -31068,7 +30984,20 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31084,17 +31013,23 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31110,27 +31045,20 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac4/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_0/gateop_A2;gopA2
@@ -31153,14 +31081,20 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/N866_2_and[32][0]_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_0/gateop_A2;gopA2
@@ -31183,14 +31117,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -31213,20 +31153,14 @@ I13;1
I14;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -31249,53 +31183,49 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31311,7 +31241,17 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_vary0/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31429,23 +31369,17 @@ S0;1
S1;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31477,7 +31411,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31493,33 +31427,43 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N104_40/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/N16/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N109.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31535,7 +31479,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31551,26 +31495,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ_perm;gopAQ
-Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31586,7 +31511,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -31602,7 +31527,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -32382,7 +32307,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N161.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N39.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -32415,14 +32340,20 @@ I13;1
I14;1
Inst
-param_manager_inst/param_offsetX/N63_mux6_7/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/N39.lt_0/gateop_A2;gopA2
@@ -32445,14 +32376,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/N83.lt_0/gateop_A2;gopA2
@@ -32475,17 +32412,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N155.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/N85.lt_0/gateop_A2;gopA2
@@ -32541,17 +32481,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/N86_mux4_3/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N85.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N104_40/gateop;gopLUT5
+image_filiter_inst/hybrid_filter_inst/N106_72/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -32614,7 +32557,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -32650,14 +32593,20 @@ I13;1
I14;1
Inst
-param_manager_inst/param_modify_S/N156_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/N155.lt_0/gateop_A2;gopA2
@@ -32680,7 +32629,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -32716,17 +32665,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_neg/opit_0_inv_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/N167.lt_0/gateop_A2;gopA2
@@ -32749,30 +32701,27 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N104_40/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N188_40/gateop;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_0/gateop_A2;gopA2
@@ -32795,20 +32744,14 @@ I13;1
I14;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_0/gateop_A2;gopA2
@@ -32831,14 +32774,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -32861,7 +32810,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -32897,81 +32846,60 @@ I13;1
I14;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_rotate_image/rotate_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33072,23 +33000,20 @@ S0;1
S1;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33120,7 +33045,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33136,7 +33061,20 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33152,7 +33090,7 @@ L4;1
RS;1
Inst
-u_rotate_image/rotate_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33168,36 +33106,17 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/N86_mux4_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N37.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_rotate_image/rotate_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33213,7 +33132,7 @@ L4;1
RS;1
Inst
-u_rotate_image/N57_mux6_2/gateop_perm;gopLUT5
+u_rotate_image/N144_mux4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -33243,7 +33162,7 @@ I13;1
I14;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -33303,14 +33222,17 @@ I13;1
I14;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -33333,20 +33255,17 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -33356,20 +33275,17 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/N99.fsub_5/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -33392,7 +33308,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33493,20 +33409,17 @@ S0;1
S1;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N167.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
@@ -33525,7 +33438,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33541,7 +33454,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33557,7 +33470,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N87.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -33570,17 +33483,23 @@ I3;1
I4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33596,14 +33515,20 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/N106_76/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
@@ -33622,7 +33547,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N37.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -33655,7 +33580,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -33685,14 +33610,20 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_ac4/gateop_perm;gopLUT5
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -33715,14 +33646,17 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -33745,7 +33679,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -33755,33 +33689,17 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N109.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33797,7 +33715,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -33807,14 +33725,33 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -33902,7 +33839,7 @@ S0;1
S1;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33918,7 +33855,20 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33950,23 +33900,20 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N107.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -33982,33 +33929,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N167.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -34040,7 +33961,20 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N87.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N109.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -35713,17 +35647,7 @@ I13;1
I14;1
Inst
-image_filiter_inst/multiline_buffer_inst/N93_mux7_14/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_rotate_image/N52_mux6_6/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N271/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35733,7 +35657,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/N48/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N199_mux5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35743,7 +35667,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/N271/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N229_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35753,7 +35677,7 @@ L3;1
L4;1
Inst
-u_rotate_image/N52_mux6_7/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N269_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35763,17 +35687,23 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/N216/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/N176_15/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N236_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35783,7 +35713,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/N176_12/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N176_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35793,7 +35723,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/N236_4/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N189[1]_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35803,7 +35733,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/N179_mux8_9/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35813,7 +35743,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -35829,17 +35759,23 @@ L4;1
RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/N199_mux5/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/N236_3/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/N142_mux4_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35849,23 +35785,17 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N229_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35875,17 +35805,23 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/N229_11/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -35901,7 +35837,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/N272/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N236_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35911,7 +35847,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_ac5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35921,7 +35857,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/N269_5/gateop;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35931,7 +35867,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/N189[1]_4/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N272/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35941,23 +35877,30 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N35.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35967,7 +35910,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -35977,23 +35920,17 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/N229_8/gateop_perm;gopLUT5
+u_axi_ddr_top/N928_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36003,7 +35940,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36023,7 +35960,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36033,7 +35970,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/N229_9/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36053,7 +35990,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36063,7 +36000,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/N176_2/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36073,7 +36010,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_and[25][0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36093,7 +36030,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36103,7 +36040,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36113,7 +36050,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36123,17 +36060,23 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+u_ov5640/power_on_delay_inst/cnt2[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36143,7 +36086,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -36153,20 +36096,14 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
@@ -36189,23 +36126,17 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N743_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -36509,14 +36440,20 @@ I14;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
+u_axi_ddr_top/cnt1_times[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -37159,7 +37096,7 @@ WR_EOP;1
WR_ERR;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37169,7 +37106,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37179,7 +37116,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37189,17 +37126,20 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N83.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37219,17 +37159,23 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37239,7 +37185,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37249,7 +37195,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37259,23 +37205,17 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7210_ctl/N539/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N122_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37285,7 +37225,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37295,17 +37235,23 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37315,17 +37261,20 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N87.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37335,7 +37284,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37345,37 +37294,55 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startY/N76_mux7_5/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37385,7 +37352,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetY/N63_mux5_3/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -37395,14 +37362,20 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetY/N63_mux3/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2;gopA2
@@ -37693,20 +37666,14 @@ I14;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -38349,14 +38316,20 @@ WR_EOP;1
WR_ERR;1
Inst
-image_filiter_inst/multiline_buffer_inst/N176_3/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/multiline_buffer_inst/hor_cnt[2]/opit_0_A2Q21;gopA2Q2
@@ -38466,20 +38439,14 @@ I14;1
RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/N93_mux7_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/multiline_buffer_inst/hor_cnt[9]/opit_0_A2Q0;gopA2Q0
@@ -38508,17 +38475,23 @@ I14;1
RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/N122_2/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_rotate_image/rotate_sta_fsm[2:0]_9_2/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N236_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -38668,7 +38641,7 @@ I14;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N269_3/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N271/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -38788,7 +38761,7 @@ I14;1
RS;1
Inst
-param_manager_inst/param_offsetX/N63_mux6_5/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N48/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -38798,14 +38771,20 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst/multiline_buffer_inst/ver_cnt[2]/opit_0_A2Q21;gopA2Q2
@@ -38835,20 +38814,14 @@ I14;1
RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/N122_10/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1;gopA2Q1
@@ -38935,23 +38908,17 @@ I14;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/N53_mux5_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -38967,7 +38934,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -38983,7 +38950,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -38999,7 +38966,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39015,7 +38982,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39031,7 +38998,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39047,7 +39014,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39063,7 +39030,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39079,23 +39046,17 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39111,7 +39072,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39127,17 +39088,23 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_1/gateop_perm;gopLUT5
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39153,20 +39120,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39182,7 +39136,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39197,6 +39151,19 @@ L3;1
L4;1
RS;1
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
Inst
image_filiter_inst/vector_to_matrix_inst/mat[0][1][0]/opit_0;gopQ
Pin
@@ -39374,20 +39341,27 @@ D;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_ac4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm;gopL5Q
@@ -39406,49 +39380,24 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/N216/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm;gopL5Q
@@ -39467,33 +39416,24 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac5/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
image_filiter_inst/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm;gopL5Q
@@ -39512,7 +39452,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39528,20 +39468,17 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N111.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_1/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39573,30 +39510,23 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][9]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -39611,6 +39541,19 @@ L3;1
L4;1
RS;1
+Inst
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N107.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
Inst
image_filiter_inst/vector_to_matrix_inst/mat[1][0][0]/opit_0;gopQ
Pin
@@ -40679,20 +40622,17 @@ D;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/N90_mux2_3/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N104_40/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -40742,7 +40682,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N35.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N167.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -40755,34 +40695,20 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/N106_78/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/N162_72/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_zoom_image/N709_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/cnt_times[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/N134_72/gateop_perm;gopLUT5
@@ -40795,14 +40721,20 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/N127.fsub_1/gateop_A2;gopA2
@@ -40865,20 +40797,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_ddr_addr_ctr/N69_6/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/N162_72/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -40888,20 +40807,40 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/N155.fsub_5/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N107.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/N155.fsub_1/gateop_A2;gopA2
@@ -40944,33 +40883,30 @@ I13;1
I14;1
Inst
-u_ddr_addr_ctr/N69_18/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N111.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_ac5/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_maj3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -40980,7 +40916,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_maj3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -40990,20 +40926,14 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[16]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_ac5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N47_1_1/gateop_A2;gopA2
@@ -42283,7 +42213,7 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_maj3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -42293,7 +42223,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N188_40/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N155.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -42306,24 +42246,17 @@ I3;1
I4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_maj3/gateop;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N161.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N47_1_1/gateop_A2;gopA2
@@ -43829,7 +43762,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/image_h_blank_valid/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -43845,20 +43778,14 @@ L4;1
RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][13]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/N39_0_ac5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/N47_1_1/gateop_A2;gopA2
@@ -45169,14 +45096,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N104_40/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N37.lt_0/gateop_A2;gopA2
@@ -45199,17 +45132,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N35.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N39.lt_0/gateop_A2;gopA2
@@ -45268,20 +45204,14 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N104_40/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N85.lt_0/gateop_A2;gopA2
@@ -45304,7 +45234,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N39.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N83.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -45337,36 +45267,27 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N87.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N107.lt_0/gateop_A2;gopA2
@@ -45389,20 +45310,17 @@ I13;1
I14;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N39.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N109.lt_0/gateop_A2;gopA2
@@ -45425,20 +45343,14 @@ I13;1
I14;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N111.lt_0/gateop_A2;gopA2
@@ -45461,7 +45373,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -45497,20 +45409,17 @@ I13;1
I14;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N85.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N161.lt_0/gateop_A2;gopA2
@@ -45533,17 +45442,14 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N155.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N167.lt_0/gateop_A2;gopA2
@@ -45566,20 +45472,23 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N167.lt_2/gateop;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/N155.fsub_5/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -45612,20 +45521,14 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_0/gateop_A2;gopA2
@@ -45648,14 +45551,17 @@ I13;1
I14;1
Inst
-N119_mux11_11/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -45678,14 +45584,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_7/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -45708,20 +45620,14 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_ac4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5
@@ -45734,17 +45640,23 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_wr3_addr_ctr/N1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -45754,7 +45666,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_7/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -45764,7 +45676,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[10]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -45865,20 +45777,7 @@ S0;1
S1;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -45910,7 +45809,17 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -45926,56 +45835,71 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -45988,14 +45912,17 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_ac4/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N109.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_0/gateop_A2;gopA2
@@ -46018,7 +45945,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46054,14 +45981,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -46084,17 +46017,14 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -46117,7 +46047,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46133,39 +46063,27 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -46175,7 +46093,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -46185,14 +46103,20 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -46280,7 +46204,7 @@ S0;1
S1;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46296,7 +46220,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46312,20 +46236,23 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N87.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N109.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -46338,20 +46265,23 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46367,7 +46297,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46399,7 +46329,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46415,7 +46345,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N83.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -46448,20 +46378,17 @@ I13;1
I14;1
Inst
-vs_down_delay_cnt[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_0/gateop_A2;gopA2
@@ -46484,14 +46411,20 @@ I13;1
I14;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -46514,20 +46447,14 @@ I13;1
I14;1
Inst
-u_ov5640/u_mix_image/rd_vs_rise/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -46550,7 +46477,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -46580,39 +46507,33 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_ov5640/u_mix_image/N339_9/gateop_perm;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -46707,7 +46628,7 @@ S0;1
S1;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46723,36 +46644,17 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46768,7 +46670,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46784,7 +46686,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46800,7 +46702,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -46816,23 +46718,20 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -46845,7 +46744,23 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -47495,7 +47410,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N37.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N37.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -47528,7 +47443,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -47564,7 +47479,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -47600,17 +47515,14 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N85.lt_2/gateop_perm;gopA
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N85.lt_0/gateop_A2;gopA2
@@ -47633,14 +47545,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N104_40/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N87.lt_0/gateop_A2;gopA2
@@ -47663,7 +47581,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -47679,7 +47597,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -47715,20 +47633,53 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N107.lt_2/gateop;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_7/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N109.lt_0/gateop_A2;gopA2
Pin
Cout;2
-Y;2
+Y0;2
+Y1;2
Cin;1
-I0;1
I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N109.lt_0/gateop_A2;gopA2
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N111.lt_0/gateop_A2;gopA2
Pin
Cout;2
Y0;2
@@ -47748,7 +47699,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N39.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N107.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -47761,7 +47712,7 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N111.lt_0/gateop_A2;gopA2
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N155.lt_0/gateop_A2;gopA2
Pin
Cout;2
Y0;2
@@ -47781,23 +47732,17 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N155.lt_0/gateop_A2;gopA2
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N161.lt_0/gateop_A2;gopA2
Pin
Cout;2
Y0;2
@@ -47817,7 +47762,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N167.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N161.lt_2/gateop;gopA
Pin
Cout;2
Y;2
@@ -47830,7 +47775,7 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N161.lt_0/gateop_A2;gopA2
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N167.lt_0/gateop_A2;gopA2
Pin
Cout;2
Y0;2
@@ -47850,53 +47795,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N167.lt_0/gateop_A2;gopA2
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N37.lt_2/gateop_perm;gopA
Pin
Cout;2
-Y0;2
-Y1;2
+Y;2
Cin;1
+I0;1
I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N188_40/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N161.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N35.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -47929,7 +47841,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -47962,17 +47874,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -47995,14 +47910,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -48025,20 +47946,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48054,7 +47962,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -48064,14 +47972,20 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
@@ -48084,7 +47998,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48099,6 +48013,19 @@ L3;1
L4;1
RS;1
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
Pin
@@ -48218,7 +48145,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48234,7 +48161,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48250,14 +48177,20 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
@@ -48276,7 +48209,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48292,7 +48225,17 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48308,20 +48251,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N35.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48337,7 +48267,17 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48353,7 +48293,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48368,19 +48308,6 @@ L3;1
L4;1
RS;1
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N161.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_0/gateop_A2;gopA2
Pin
@@ -48402,20 +48329,14 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/N142_mux4_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_0/gateop_A2;gopA2
@@ -48438,14 +48359,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -48468,17 +48395,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -48501,33 +48431,23 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N111.lt_2/gateop_perm;gopA
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst/multiline_buffer_inst/N229_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -48537,7 +48457,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48553,7 +48473,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/N146_mux2_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -48563,7 +48483,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -48572,6 +48492,19 @@ L2;1
L3;1
L4;1
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
Pin
@@ -48675,23 +48608,7 @@ S0;1
S1;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48707,7 +48624,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48733,7 +48650,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48749,7 +48666,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48765,20 +48682,30 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
@@ -48797,7 +48724,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48813,7 +48740,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -48829,36 +48756,27 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_0/gateop_A2;gopA2
@@ -48881,14 +48799,17 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac5/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_0/gateop_A2;gopA2
@@ -48911,20 +48832,14 @@ I13;1
I14;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -48947,7 +48862,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -48990,17 +48905,7 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -49010,7 +48915,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -49023,7 +48928,7 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -49033,20 +48938,27 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N167.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -49151,7 +49063,7 @@ S0;1
S1;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -49167,7 +49079,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -49183,36 +49095,17 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N85.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -49225,7 +49118,7 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N109.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -49238,7 +49131,7 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -49254,23 +49147,17 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -49286,7 +49173,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -49299,7 +49186,7 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -49315,17 +49202,36 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[0]/opit_0;gopQ
@@ -50092,20 +49998,14 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/N86_mux4_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N37.lt_0/gateop_A2;gopA2
@@ -50128,20 +50028,17 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N107.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N39.lt_0/gateop_A2;gopA2
@@ -50164,7 +50061,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -50200,17 +50097,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N85.lt_0/gateop_A2;gopA2
@@ -50233,14 +50133,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N104_40/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N87.lt_0/gateop_A2;gopA2
@@ -50263,7 +50169,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -50279,7 +50185,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N155.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -50312,7 +50218,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N85.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N111.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -50345,7 +50251,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N83.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N37.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -50378,17 +50284,14 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N155.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N155.lt_0/gateop_A2;gopA2
@@ -50411,17 +50314,14 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N37.lt_2/gateop_perm;gopA
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N161.lt_0/gateop_A2;gopA2
@@ -50444,20 +50344,14 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/rd_ddr_idle/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N188_40/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N167.lt_0/gateop_A2;gopA2
@@ -50480,30 +50374,30 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N111.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N167.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/N106_72/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_0/gateop_A2;gopA2
@@ -50526,7 +50420,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -50556,14 +50450,17 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -50586,14 +50483,17 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N155.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_0/gateop_A2;gopA2
@@ -50616,7 +50516,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -50632,7 +50532,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -50642,7 +50542,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -50652,23 +50552,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -50678,14 +50572,20 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -50789,7 +50689,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -50805,14 +50705,20 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_7/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
@@ -50831,17 +50737,20 @@ L4;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -50857,23 +50766,17 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N83.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -50886,36 +50789,27 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N87.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_0/gateop_A2;gopA2
@@ -50938,7 +50832,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -50971,14 +50865,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -51001,7 +50901,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51037,36 +50937,17 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -51076,23 +50957,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -51105,7 +50980,7 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51120,6 +50995,19 @@ L3;1
L4;1
RS;1
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
Pin
@@ -51206,17 +51094,7 @@ S0;1
S1;1
Inst
-image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/N39_0_ac4/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51232,7 +51110,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51248,7 +51126,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51264,27 +51142,33 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N188_40/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/N39_0_ac5/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51300,7 +51184,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -51310,23 +51194,30 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N109.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51362,17 +51253,20 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_0/gateop_A2;gopA2
@@ -51395,20 +51289,17 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2
@@ -51431,7 +51322,7 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -51461,17 +51352,23 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -51481,7 +51378,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -51491,7 +51388,7 @@ L3;1
L4;1
Inst
-u_clk50m_rst/rst/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51507,30 +51404,30 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N85.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -51618,7 +51515,7 @@ S0;1
S1;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51634,7 +51531,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51650,7 +51547,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N87.lt_2/gateop_perm;gopA
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N167.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -51663,20 +51560,23 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[0]/opit_0_inv_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51708,7 +51608,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51724,7 +51624,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51740,7 +51640,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -51756,17 +51656,14 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N39.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[0]/opit_0;gopQ
@@ -53429,7 +53326,7 @@ I13;1
I14;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -53445,7 +53342,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N93_mux7_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53455,23 +53352,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/N96_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N189[1]_1/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N269_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53481,7 +53372,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N176_3/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N189[1]_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53491,7 +53382,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N176_15/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N179_mux8_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53501,7 +53392,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N179_mux8_9/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N176_15/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53511,23 +53402,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/N229_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N216/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53537,7 +53422,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N189[1]_8/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53547,7 +53432,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N199_mux5/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N93_mux7_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53557,37 +53442,55 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10:0]_or_1/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N271/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N236_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53607,7 +53510,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/N69_14/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/N26_mux2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53617,24 +53520,36 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/u1/cyc_count[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10:0]_or_3/gateop_perm;gopLUT5
@@ -53647,7 +53562,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53657,7 +53572,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53667,24 +53582,33 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
@@ -53697,7 +53621,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53707,7 +53631,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -53723,7 +53647,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N176_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53743,7 +53667,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53763,7 +53687,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/N117_mux7_7/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53783,7 +53707,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53793,7 +53717,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53803,7 +53727,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53823,23 +53747,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53849,7 +53767,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/N924_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -53859,14 +53777,20 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5
@@ -53889,7 +53813,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N189[1]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -54187,20 +54111,14 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -54853,39 +54771,27 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/u1/N267_21/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -54895,7 +54801,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -54905,27 +54811,39 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -54945,23 +54863,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N199_mux5_8/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -54971,23 +54883,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/coms2_reg_config/u1/N146_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -54997,7 +54903,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -55007,7 +54913,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -55017,7 +54923,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -55027,7 +54933,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -55037,23 +54943,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -55063,23 +54963,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -55099,7 +54993,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/N117_mux7_6/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -55109,7 +55003,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N216/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/u1/N8_mux3_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -55407,7 +55301,7 @@ I14;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -56057,7 +55951,7 @@ WR_EOP;1
WR_ERR;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N93_mux7_14/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N229_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -56216,7 +56110,7 @@ I14;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N176_2/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -56226,7 +56120,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N96_3/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N199_mux5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -56236,23 +56130,172 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21;gopA2Q2
Pin
CEOUT;2
-Q;2
+Cout;2
+Q0;2
+Q1;2
RSOUT;2
-Z;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
CE;1
CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+Pin
+Z;2
L0;1
L1;1
L2;1
L3;1
L4;1
+
+Inst
+image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21;gopA2Q2
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -56279,104 +56322,7 @@ I14;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_empty0/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21;gopA2Q2
+image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -56403,7 +56349,7 @@ I14;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ_perm;gopAQ
+image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ;gopAQ
Pin
CEOUT;2
Cout;2
@@ -56422,77 +56368,7 @@ I4;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/u_axi_rd_connect/rd1_fifo_full0/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-image_filiter_inst2/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -56535,14 +56411,20 @@ I14;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N236_4/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
image_filiter_inst2/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1;gopA2Q1
@@ -56571,7 +56453,7 @@ I14;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -56587,20 +56469,14 @@ L4;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10:0]_or_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/multiline_buffer_inst/ver_cnt[7]/opit_0_A2Q0;gopA2Q0
@@ -56639,23 +56515,17 @@ L3;1
L4;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/N176_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -56671,20 +56541,17 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N111.lt_2/gateop_perm;gopA
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -56700,7 +56567,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -56748,7 +56615,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -56764,7 +56631,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -56780,17 +56647,20 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N37.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -56806,7 +56676,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -56822,7 +56692,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -56838,17 +56708,23 @@ L4;1
RS;1
Inst
-u_axi_rst/N0/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][13]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -56864,20 +56740,14 @@ L4;1
RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
image_filiter_inst2/vector_to_matrix_inst/mat[0][1][0]/opit_0;gopQ
@@ -57056,7 +56926,7 @@ D;1
RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -57072,39 +56942,27 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[8]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/N176_12/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -57120,7 +56978,7 @@ L4;1
RS;1
Inst
-N119_mux11_12/gateop_perm;gopLUT5
+image_filiter_inst2/multiline_buffer_inst/N53_mux5_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -57130,17 +56988,23 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/N146_mux2_3/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -57156,52 +57020,37 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/multiline_buffer_inst/N93_mux7_11/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N37.lt_2/gateop_perm;gopA
+image_filiter_inst/multiline_buffer_inst/N236_3/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N85.lt_2/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -57214,23 +57063,17 @@ I3;1
I4;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N188_40/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst2/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -57246,7 +57089,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N176_12/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -57256,17 +57099,23 @@ L3;1
L4;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58704,7 +58553,7 @@ MIPI_IN;1
TS;1
Inst
-ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_7_2/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N357_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58714,7 +58563,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/N313_7/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N315_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58724,7 +58573,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N40_6/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_7_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58776,17 +58625,7 @@ I13;1
I14;1
Inst
-ms72xx_ctl/iic_dri_rx/N499_inv/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-ms72xx_ctl/iic_dri_rx/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/trans_bit[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -58802,7 +58641,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N315_5/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N310_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58812,7 +58651,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/scl_out/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/fre_cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -58828,23 +58667,17 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/fre_cnt[1]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N530_mux7_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/iic_dri_tx/N345_2/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N434/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58854,7 +58687,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/twr_cnt[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/scl_out/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -58870,17 +58703,23 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N460/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N434/gateop;gopLUT5
+ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_53/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58890,17 +58729,23 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/N461_8_and[3][3]/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/scl_out/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N498_2/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N461_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58920,7 +58765,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -58936,23 +58781,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/N461_8_or[1][3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N461_8_or[4][3]/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58962,7 +58801,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1845_3/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N461_8_or[2][3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58972,7 +58811,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N2/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58982,7 +58821,23 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_H/N63_mux5_5/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/addr[2]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+ms72xx_ctl/iic_dri_rx/N461_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -58992,7 +58847,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_39_3/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N498_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -59032,6 +58887,16 @@ L2;1
L3;1
L4;1
+Inst
+ms72xx_ctl/iic_dri_tx/N168_mux3_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_31/gateop_perm;gopLUT5
Pin
@@ -59043,7 +58908,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_53/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_71/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -59053,39 +58918,27 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/busy/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/N504/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/iic_dri_rx/trans_bit[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N40_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/iic_dri_rx/byte_over/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/trans_en/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -59205,7 +59058,7 @@ D;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/fre_cnt[2]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/fre_cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -59221,7 +59074,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/twr_cnt[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/fre_cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -59237,20 +59090,14 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/fre_cnt[3]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N40_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
ms72xx_ctl/iic_dri_rx/fre_cnt[4]/opit_0_L5Q_perm;gopL5Q
@@ -59269,7 +59116,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N345_2/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N165_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -59400,14 +59247,20 @@ D;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N165_1/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/fre_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
ms72xx_ctl/iic_dri_rx/sda_out/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -59427,7 +59280,7 @@ S0;1
S1;1
Inst
-ms72xx_ctl/iic_dri_rx/send_data[3]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/send_data[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -59459,7 +59312,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/send_data[4]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/send_data[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -59506,16 +59359,6 @@ L3;1
L4;1
RS;1
-Inst
-ms72xx_ctl/iic_dri_rx/N461_8_and[5][3]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
ms72xx_ctl/iic_dri_rx/send_data[7]/opit_0_L5Q_perm;gopL5Q
Pin
@@ -59533,23 +59376,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N1359/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/iic_dri_rx/trans_en/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -59565,7 +59402,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N461_8_or[2][3]/gateop_perm;gopLUT5
+u_zoom_image/N715_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -59575,7 +59412,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/N357_2/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N24_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -59585,7 +59422,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -59601,23 +59438,17 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_H/value[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/N80_0/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_71/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/twr_en_ce_mux/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -59627,17 +59458,23 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/N461_5/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/trans_byte_max[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N461_9/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/N504/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -59647,7 +59484,17 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/N39/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+ms72xx_ctl/iic_dri_rx/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -59680,14 +59527,20 @@ S0;1
S1;1
Inst
-ms72xx_ctl/iic_dri_rx/N461_5/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/iic_trig/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
ms72xx_ctl/iic_dri_rx/state_reg[3]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -59707,14 +59560,20 @@ S0;1
S1;1
Inst
-ms72xx_ctl/iic_dri_rx/N461_11/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/send_data[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
ms72xx_ctl/iic_dri_rx/state_reg[5]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -59783,20 +59642,14 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/trans_byte_max[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_39_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
ms72xx_ctl/iic_dri_rx/trans_byte[1]/opit_0_L5Q_perm;gopL5Q
@@ -59847,30 +59700,30 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/twr_en/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/N345_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/iic_dri_rx/twr_en_ce_mux/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/byte_over/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
ms72xx_ctl/iic_dri_rx/trans_byte_max[2]/opit_0;gopQ
@@ -59884,7 +59737,7 @@ D;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/trans_byte[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/twr_en/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -59948,30 +59801,39 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/mult_image2[1][12]/opit_0_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-param_manager_inst/param_modify_H/N151_19/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_70/gateop_perm;gopLUT5
@@ -60006,7 +59868,7 @@ D;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/N80_0/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/N165_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60016,7 +59878,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/N499_inv/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N622_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60066,7 +59928,7 @@ I13;1
I14;1
Inst
-ms72xx_ctl/iic_dri_tx/N460/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/N461_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60076,30 +59938,30 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/iic_trig/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/N499_inv/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/iic_dri_tx/N461_9/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/byte_over/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
ms72xx_ctl/iic_dri_tx/twr_en_ce_mux/gateop_perm;gopLUT5
@@ -60112,7 +59974,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_71/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N983_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60122,7 +59984,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/N504/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/N461_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60143,20 +60005,14 @@ S0;1
S1;1
Inst
-ms72xx_ctl/ms7210_ctl/addr[0]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/N461_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
ms72xx_ctl/iic_dri_tx/N461_8_or[2]_2/gateop;gopMUX4TO1
@@ -60181,7 +60037,7 @@ S0;1
S1;1
Inst
-ms72xx_ctl/iic_dri_tx/N461_11/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N539/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60191,7 +60047,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate_A/N154/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N493_and[0][4]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60201,30 +60057,30 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/N493_or[0]_3/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/iic_dri_tx/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/N14_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
ms72xx_ctl/iic_dri_tx/N493_or[0]_5/gateop;gopMUX4TO1
@@ -60238,7 +60094,7 @@ S0;1
S1;1
Inst
-ms72xx_ctl/iic_dri_tx/trans_bit[0]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/image_h0[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60254,7 +60110,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_39_3/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_7_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60264,7 +60120,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/start_en/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/trans_en/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60280,14 +60136,20 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/N2/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/start_en/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
ms72xx_ctl/iic_dri_tx/data_out[0]/opit_0;gopQ
@@ -60499,7 +60361,7 @@ D;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/fre_cnt[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/busy/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60532,7 +60394,7 @@ S0;1
S1;1
Inst
-ms72xx_ctl/iic_dri_tx/send_data[2]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/send_data[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60548,7 +60410,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/send_data[5]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/send_data[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60580,7 +60442,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/send_data[4]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/addr[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60596,7 +60458,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/addr[3]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/send_data[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60644,7 +60506,7 @@ L4;1
RS;1
Inst
-u_sync_vg/N28_mux8_5/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N589/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60654,7 +60516,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/trans_en/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/imag_addr0[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60670,33 +60532,17 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_10/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-ms72xx_ctl/iic_dri_tx/trans_byte[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N59_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_rotate_A/value[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60712,7 +60558,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/N168_mux3_1/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_39_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60722,39 +60568,30 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate_A/value[5]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_53/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_modify_H/value[1]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N383.eq_6/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-ms72xx_ctl/iic_dri_tx/trans_byte_max[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/trans_byte[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60770,7 +60607,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/twr_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60803,20 +60640,14 @@ S0;1
S1;1
Inst
-ms72xx_ctl/iic_dri_tx/state_reg[2]/opit_0_inv_L5Q;gopL5Q
+ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_10/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
ms72xx_ctl/iic_dri_tx/state_reg[3]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -60836,7 +60667,7 @@ S0;1
S1;1
Inst
-ms72xx_ctl/iic_dri_tx/N39/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60912,7 +60743,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_31/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N620/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -60922,7 +60753,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/trans_byte[2]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/trans_byte[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60938,7 +60769,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/trans_byte[1]/opit_0_L5Q;gopL5Q
+ms72xx_ctl/iic_dri_tx/trans_byte[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60970,7 +60801,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate_A/value[3]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -60986,14 +60817,20 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_70/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/trans_byte_max[0]/opit_0_L5Q;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
ms72xx_ctl/iic_dri_tx/trans_byte_max[2]/opit_0;gopQ
@@ -61071,7 +60908,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N316_3/gateop_perm;gopLUT5
+u_zoom_image/N857_8[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61081,7 +60918,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate_A/N156_19/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/N345_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61091,14 +60928,22 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/N489_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[7]_2_muxf6_perm;gopLUT6
Pin
+Y0;2
+Y1;2
Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+A0;1
+A1;1
+A2;1
+A3;1
+A4;1
+B0;1
+B1;1
+B2;1
+B3;1
+B4;1
+M;1
Inst
ms72xx_ctl/iic_dri_tx/w_r_1d/opit_0_inv;gopQ
@@ -61123,7 +60968,7 @@ D;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N2082_1/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N8_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61143,7 +60988,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1877/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61153,7 +60998,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N24_4/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N63_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61163,7 +61008,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N63_5/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61173,7 +61018,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_10/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N499_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61183,17 +61028,23 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N8_5/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/twr_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N39/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1797/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61203,7 +61054,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1797/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61532,7 +61383,7 @@ WR_EOP;1
WR_ERR;1
Inst
-ms72xx_ctl/ms7200_ctl/N1844_2/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1844_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61542,17 +61393,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1366_6/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N2082_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61562,7 +61403,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1844_5_2/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1366_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61572,7 +61413,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/N461_8_or[1][3]/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61582,7 +61423,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1895/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1845_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61592,7 +61433,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1872_7/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N2031/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61602,17 +61443,23 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N1844_7_or[1]_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61622,7 +61469,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1845_1/gateop_perm;gopLUT5
+u_zoom_image/N306_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61632,71 +61479,47 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N1879_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N1954_1_or[0]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/iic_dri_rx/send_data[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/N537_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N1879_11/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N1879_5/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1953/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61716,27 +61539,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1989_1_or[6]_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-ms72xx_ctl/ms7200_ctl/N1844_5_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-ms72xx_ctl/ms7200_ctl/N2031/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N580/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61746,7 +61549,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate_A/N148_5/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1955/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61756,7 +61559,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1955/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N461_8_and[3][3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61766,7 +61569,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/dri_cnt[8:0]_130/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/dri_cnt[8:0]_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61776,7 +61579,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1954_1_or[10]_3/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1989_1_or[4]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61786,17 +61589,23 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1989_1_or[0]_4/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/addr[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/ms7200_ctl/cmd_index[0]/opit_0_inv_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -61812,17 +61621,23 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N2071_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N1844_7_or[1]_2_2/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1989_1_or[0]_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61832,23 +61647,17 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[6]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/N460/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N2085/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/dri_cnt[8:0]_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61858,7 +61667,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N2076/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61868,39 +61677,27 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N2085/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[1]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/N461_8_and[5][3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7200_ctl/iic_trig/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/addr[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -61916,7 +61713,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N1954_1_or[0]_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[5]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -61926,7 +61723,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -61942,7 +61739,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[2]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/addr[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -61958,7 +61755,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/addr[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -61974,7 +61771,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/addr[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -61990,7 +61787,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[13]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62006,7 +61803,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[7]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/addr[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62022,7 +61819,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[12]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62054,7 +61851,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[9]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/data_in[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62070,7 +61867,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/data_in[2]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/addr[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62086,7 +61883,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/data_in[1]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/cmd_index[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62102,7 +61899,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/send_data[1]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62129,7 +61926,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N81/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62265,23 +62062,17 @@ I4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N2071_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7200_ctl/data_in[4]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/data_in[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62313,7 +62104,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/data_in[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62329,7 +62120,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[3]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62345,17 +62136,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/addr[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62371,7 +62168,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N1953/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1954_1_or[0]_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62381,7 +62178,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62397,7 +62194,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/dri_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62413,7 +62210,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/dri_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62429,7 +62226,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62445,7 +62242,17 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/dri_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+ms72xx_ctl/ms7200_ctl/dri_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62461,7 +62268,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/dri_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/dri_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62477,7 +62284,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/dri_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/dri_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62503,23 +62310,40 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/dri_cnt[8:0]_116_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7200_ctl/addr[8]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/dri_cnt[8:0]_168/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/N20.fsub_8/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62535,7 +62359,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N2083/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N165_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62611,39 +62435,27 @@ D;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/N461_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7200_ctl/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/N489_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_modify_H/N149/gateop_perm;gopLUT5
+u_zoom_image/N234_0/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62653,7 +62465,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62685,17 +62497,23 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N1359_1/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/ms7200_ctl/init_over/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_rx/send_data[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62728,17 +62546,7 @@ S0;1
S1;1
Inst
-ms72xx_ctl/iic_dri_tx/N461_8_or[1][2]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-ms72xx_ctl/ms7210_ctl/N14_8/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N527/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62748,7 +62556,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_7_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62758,7 +62566,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/N537_1/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N14_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62768,7 +62576,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/N390_3/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N559_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62778,7 +62586,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/N382_3/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N124_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62788,7 +62596,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/N165_5/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N556_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62912,7 +62720,7 @@ WEA;1
WEB;1
Inst
-ms72xx_ctl/ms7210_ctl/N405_9/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N390_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62922,7 +62730,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/N527/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N405_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62942,7 +62750,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/N403_18/gateop_perm;gopLUT5
+u_zoom_image/N919/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -62962,7 +62770,7 @@ L3;1
L4;1
Inst
-param_manager_inst/offsetY_load/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -62988,33 +62796,33 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/N403_18/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7210_ctl/N556_1/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/ms7210_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/iic_trig/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63030,33 +62838,33 @@ L4;1
RS;1
Inst
-u_sync_vg/N184_14/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_rotate_image/image_h_blank_valid/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/N586/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7210_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_zoom_image/imag_addr1[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63082,7 +62890,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/N586/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N62_ac2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -63092,7 +62900,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/N589/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N36/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -63102,33 +62910,33 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/N591/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/trans_byte[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/ms7210_ctl/addr[2]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/N591/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7210_ctl/N580/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1879_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -63138,7 +62946,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/addr[5]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/addr[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63154,7 +62962,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/addr[4]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/addr[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63170,7 +62978,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/addr[8]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/data_in[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63186,7 +62994,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/addr[9]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/data_in[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63202,7 +63010,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/data_in[0]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/addr[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63218,7 +63026,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/addr[7]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/addr[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63234,7 +63042,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/addr[11]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/addr[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63250,20 +63058,14 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/data_in[6]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N1918/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
ms72xx_ctl/ms7210_ctl/addr[10]/opit_0_inv_L5Q_perm;gopL5Q
@@ -63282,7 +63084,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/data_in[1]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/data_in[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63298,7 +63100,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/data_in[2]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/addr[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63314,20 +63116,14 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/data_in[5]/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1109/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
ms72xx_ctl/ms7210_ctl/busy_1d/opit_0;gopQ
@@ -63341,7 +63137,7 @@ D;1
RS;1
Inst
-udp_wr_mem_inst/N538_16/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -63431,7 +63227,7 @@ I14;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/data_in[4]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/data_in[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63463,7 +63259,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/addr[1]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/data_in[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63479,7 +63275,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/send_data[1]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/init_over/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63495,7 +63291,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/send_data[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/data_in[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63511,7 +63307,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/data_in[7]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63527,7 +63323,7 @@ L4;1
RS;1
Inst
-param_manager_inst/selected[8]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/data_in[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63543,20 +63339,14 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/state_reg[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
ms72xx_ctl/ms7210_ctl/N403_10/gateop_perm;gopLUT5
@@ -63858,7 +63648,7 @@ I4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63874,14 +63664,20 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N1844_7_or[1]_5/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
ms72xx_ctl/ms7210_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
@@ -63900,7 +63696,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_zoom_image/imag_addr0[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -63916,23 +63712,17 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_zoom_image/ram_sta_fsm[3:0]_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/iic_dri_tx/N165_1/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/N403_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -63942,20 +63732,14 @@ L3;1
L4;1
Inst
-u_sync_vg/h_count[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
ms72xx_ctl/ms7210_ctl/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -63974,7 +63758,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -64006,14 +63790,20 @@ L4;1
RS;1
Inst
-u_sync_vg/N184_13/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
ms72xx_ctl/ms7210_ctl/w_r/opit_0_inv_L5Q_perm;gopL5Q
@@ -64032,20 +63822,14 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_tx/byte_over/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/N382_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
ms72xx_ctl/rstn/opit_0;gopQ
@@ -64091,7 +63875,7 @@ L3;1
L4;1
Inst
-param_manager_inst/N314_26/gateop_perm;gopLUT5
+param_manager_inst/N314_24/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64101,7 +63885,7 @@ L3;1
L4;1
Inst
-param_manager_inst/N314_24/gateop_perm;gopLUT5
+param_manager_inst/N314_28/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64111,14 +63895,20 @@ L3;1
L4;1
Inst
-param_manager_inst/N335/gateop_perm;gopLUT5
+u_sync_vg/hdmi_image_data0[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/N344/gateop_perm;gopLUT5
@@ -64131,7 +63921,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_10/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/N63_mux9_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64141,7 +63931,7 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_left/pluse_ms/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/ms_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -64157,7 +63947,7 @@ L4;1
RS;1
Inst
-param_manager_inst/N314_28/gateop_perm;gopLUT5
+param_manager_inst/N314_26/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64167,20 +63957,24 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/N9_mux11/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+param_manager_inst/N335/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/clk_ms/opit_0_L5Q_perm;gopL5Q
@@ -64199,7 +63993,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[6]/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/N157_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64209,27 +64003,20 @@ L3;1
L4;1
Inst
-param_manager_inst/N345/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_left/change/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N361.eq_8/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+RS;1
Inst
param_manager_inst/N9_mux15_4/gateop_perm;gopLUT5
@@ -64302,7 +64089,7 @@ D;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/pluse/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/rotate_load/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -64318,7 +64105,7 @@ L4;1
RS;1
Inst
-param_manager_inst/index[0]/opit_0_L5Q;gopL5Q
+param_manager_inst/index[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -64366,7 +64153,7 @@ L4;1
RS;1
Inst
-param_manager_inst/key_debounce_key_left/N20_mux2/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/N148_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64376,7 +64163,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N135_mux9_4/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_left/N20_mux4_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64386,7 +64173,7 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_left/N47_12/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_left/N89_5[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64396,7 +64183,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startX/N102_8/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N102_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64406,7 +64193,7 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_left/N89_5[2]/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_left/N88/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64416,7 +64203,7 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_left/N20_mux4_1/gateop_perm;gopLUT5
+param_manager_inst/param_modify_V/N63_mux8_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64426,7 +64213,7 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_left/N88/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_left/N47_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64436,23 +64223,17 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_left/cnt[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_V/N140/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/key_debounce_key_left/change/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_left/cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -64468,20 +64249,14 @@ L4;1
RS;1
Inst
-param_manager_inst/key_debounce_key_left/cnt[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/N151_19/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/key_debounce_key_left/clk_ms_ff0/opit_0;gopQ
@@ -64506,7 +64281,7 @@ D;1
RS;1
Inst
-param_manager_inst/key_debounce_key_left/cnt[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_left/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -64522,14 +64297,20 @@ L4;1
RS;1
Inst
-u_zoom_image/N858_inv/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_left/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/key_debounce_key_left/cnt[3]/opit_0_L5Q_perm;gopL5Q
@@ -64548,36 +64329,24 @@ L4;1
RS;1
Inst
-param_manager_inst/key_debounce_key_left/cnt[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_left/N20_mux2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/index[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/N345/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/key_debounce_key_left/key_ff0/opit_0;gopQ
@@ -64602,7 +64371,7 @@ D;1
RS;1
Inst
-param_manager_inst/N9_mux11/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N19_mux2_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64612,17 +64381,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N748/gateop_perm;gopLUT5
+param_manager_inst/modify_V_load/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/key_debounce_key_restore/N47_7/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_restore/N87/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64642,7 +64417,7 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_restore/N87/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_restore/N47_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64662,49 +64437,43 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_restore/N88/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N102_7/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_restore/cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/key_debounce_key_restore/cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N135/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_restore/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -64736,7 +64505,7 @@ L4;1
RS;1
Inst
-param_manager_inst/key_debounce_key_restore/cnt[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_restore/cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -64752,23 +64521,17 @@ L4;1
RS;1
Inst
-param_manager_inst/key_debounce_key_restore/cnt[4]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/N184_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/key_debounce_key_restore/N20_mux4_1/gateop_perm;gopLUT5
+udp_osd_inst/N69_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64800,17 +64563,23 @@ D;1
RS;1
Inst
-param_manager_inst/key_debounce_key_right/N87/gateop_perm;gopLUT5
+param_manager_inst/osd_startY_load/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/key_debounce_key_right/N47_6/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_right/N20_mux4_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -64820,30 +64589,30 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_right/N47_7/gateop_perm;gopLUT5
+rstn_1ms[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/key_debounce_key_restore/cnt[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_right/N47_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/key_debounce_key_right/N89_5[2]/gateop_perm;gopLUT5
@@ -64866,7 +64635,7 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_right/pressed/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_right/change/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -64882,7 +64651,7 @@ L4;1
RS;1
Inst
-param_manager_inst/key_debounce_key_right/cnt[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_right/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -64898,14 +64667,20 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff1[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/key_debounce_key_right/cnt[1]/opit_0_L5Q_perm;gopL5Q
@@ -64924,7 +64699,7 @@ L4;1
RS;1
Inst
-param_manager_inst/key_debounce_key_right/cnt[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_right/cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -64940,33 +64715,33 @@ L4;1
RS;1
Inst
-param_manager_inst/key_debounce_key_right/cnt[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N19_inv_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/key_debounce_key_right/N20_mux2/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_right/cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/key_debounce_key_restore/pressed/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/addr_bus_rd_ce[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -65004,7 +64779,7 @@ D;1
RS;1
Inst
-param_manager_inst/key_debounce_key_restore/N20_mux2/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_right/N87/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -65058,20 +64833,14 @@ D;1
RS;1
Inst
-param_manager_inst/modify_V_load/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/N20_mux2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/modify_S_flags_ff0/opit_0;gopQ
@@ -65118,7 +64887,7 @@ D;1
RS;1
Inst
-param_manager_inst/param_rotate/N102_11/gateop_perm;gopLUT5
+param_manager_inst/param_modify_S/N63_mux8_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -65172,7 +64941,7 @@ D;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/N152_6/gateop_perm;gopLUT5
+param_manager_inst/param_modify_V/N151_19/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -65182,7 +64951,7 @@ L3;1
L4;1
Inst
-param_manager_inst/N9_mux4_3/gateop_perm;gopLUT5
+param_manager_inst/N9_mux9_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -65452,14 +65221,20 @@ D;1
RS;1
Inst
-param_manager_inst/param_offsetX/N72/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[16]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/offsetY_flags_ff0/opit_0;gopQ
@@ -65506,20 +65281,14 @@ D;1
RS;1
Inst
-param_manager_inst/param_offsetX/value[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_S/N148_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/osd_char_height_flags_ff0/opit_0;gopQ
@@ -65566,14 +65335,20 @@ D;1
RS;1
Inst
-param_manager_inst/param_offsetX/N156_1/gateop_perm;gopLUT5
+param_manager_inst/osd_char_width_load/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/osd_char_width_flags_ff0/opit_0;gopQ
@@ -65620,7 +65395,7 @@ D;1
RS;1
Inst
-param_manager_inst/param_osd_char_width/N63_mux10_4/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/N148_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -65674,14 +65449,20 @@ D;1
RS;1
Inst
-param_manager_inst/param_offsetX/N148_3/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/pressed/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/osd_startY_flags_ff0/opit_0;gopQ
@@ -65728,7 +65509,7 @@ D;1
RS;1
Inst
-param_manager_inst/param_osd_startY/N149_49/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/N156_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -65851,7 +65632,7 @@ I3;1
I4;1
Inst
-param_manager_inst/param_filiter1_mode/cnt[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_start_i_ff/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -65867,7 +65648,23 @@ L4;1
RS;1
Inst
-param_manager_inst/N33_mux3_1/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/cnt[7]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+param_manager_inst/param_filiter1_mode/N116/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -65893,7 +65690,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_H/cnt[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -65909,23 +65706,17 @@ L4;1
RS;1
Inst
-param_manager_inst/selected[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/N161_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_filiter1_mode/cnt[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startY/value[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -65941,17 +65732,23 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter2_mode/N153/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_filiter1_mode/N153/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/N153_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -65961,17 +65758,23 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_V/N150_1/gateop_perm;gopLUT5
+param_manager_inst/selected[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_filiter1_mode/N153_1/gateop_perm;gopLUT5
+param_manager_inst/param_filiter2_mode/N153/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -65981,23 +65784,17 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/flags[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate_A/N156_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_fsm[6:0]_34/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/N102_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66007,7 +65804,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/cnt[0]/opit_0_L5Q;gopL5Q
+param_manager_inst/param_filiter1_mode/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66039,7 +65836,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/cnt[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66055,7 +65852,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/cnt[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/cnt[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66071,33 +65868,26 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_10/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-param_manager_inst/param_filiter1_mode/cnt[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/cnt[11]/opit_0_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/cnt[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/cnt[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66139,24 +65929,31 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_char_height/cnt[11]/opit_0_AQ_perm;gopAQ
+param_manager_inst/param_filiter1_mode/cnt[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
-Cout;2
Q;2
RSOUT;2
-Y;2
+Z;2
CE;1
CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
+Inst
+param_manager_inst/param_filiter1_mode/N122/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
param_manager_inst/param_filiter1_mode/cnt[11]/opit_0_L5Q_perm;gopL5Q
Pin
@@ -66174,7 +65971,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_5/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/N76_mux7_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66184,26 +65981,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate/cnt[11]/opit_0_AQ_perm;gopAQ
-Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
-
-Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/N47_6/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/N88/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66213,7 +65991,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/N47_7/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/N47_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66223,7 +66001,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66239,39 +66017,27 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/change/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/N87/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/pressed/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/N89_5[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/pressed/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/value[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66287,7 +66053,7 @@ L4;1
RS;1
Inst
-u_zoom_image/cnt_h[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66303,7 +66069,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/selected[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66319,7 +66085,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66351,7 +66117,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/N20_mux4_1/gateop_perm;gopLUT5
+param_manager_inst/param_modify_S/N76_mux8_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66361,7 +66127,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66376,6 +66142,16 @@ L3;1
L4;1
RS;1
+Inst
+param_manager_inst/param_modify_H/N63_mux5_5/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
param_manager_inst/param_filiter1_mode/key_debounce_inst1/key_ff0/opit_0;gopQ
Pin
@@ -66399,7 +66175,7 @@ D;1
RS;1
Inst
-param_manager_inst/param_rotate/N102_12/gateop_perm;gopLUT5
+param_manager_inst/param_modify_S/N154/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66409,7 +66185,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/N20_mux4_1/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/N47_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66419,7 +66195,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/N87/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N102_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66429,7 +66205,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/N47_7/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/N87/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66439,7 +66215,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66455,7 +66231,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/N89_5[2]/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/N88/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66465,23 +66241,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/N89_5[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/N88/gateop_perm;gopLUT5
+udp_wr_mem_inst/N204/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66491,14 +66261,20 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/N47_6/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/pluse/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[1]/opit_0_L5Q_perm;gopL5Q
@@ -66533,7 +66309,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66549,7 +66325,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[3]/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/N47_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66559,7 +66335,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+param_manager_inst/param_modify_H/N72/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66591,7 +66367,7 @@ D;1
RS;1
Inst
-param_manager_inst/param_modify_H/N102_10/gateop_perm;gopLUT5
+udp_wr_mem_inst/N244/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66601,31 +66377,30 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter2_mode/N152_1/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/pluse/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_filiter1_mode/value[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
+image_filiter_inst/hybrid_filter_inst/N106_90/gateop_perm;gopLUT5
Pin
-CEOUT;2
-F;2
-Q;2
-RSOUT;2
-CE;1
-CLK;1
-I0;1
-I1;1
-I2;1
-I3;1
-RS;1
-S0;1
-S1;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
param_manager_inst/param_filiter1_mode/value[1]/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -66644,6 +66419,16 @@ RS;1
S0;1
S1;1
+Inst
+u_zoom_image/N238_0/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
param_manager_inst/param_filiter1_mode/value[2]/opit_0_MUX4TO1Q;gopMUX4TO1Q
Pin
@@ -66682,7 +66467,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_H/N102_8/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/N72/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66692,7 +66477,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/N122/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/N152_5_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66702,7 +66487,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_char_height/N102_11/gateop_perm;gopLUT5
+param_manager_inst/param_modify_V/N142/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66783,7 +66568,7 @@ I13;1
I14;1
Inst
-param_manager_inst/param_modify_H/N63_mux5_6/gateop_perm;gopLUT5
+param_manager_inst/param_modify_H/N76_mux5_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66793,7 +66578,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_H/N76_mux5_5/gateop_perm;gopLUT5
+param_manager_inst/param_modify_H/N154/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66803,39 +66588,27 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startX/N153_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/N76_mux6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10/gateop_perm;gopLUT5
+param_manager_inst/param_modify_H/N156_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66845,17 +66618,23 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_H/N76_mux8_3/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_modify_H/N154_2/gateop_perm;gopLUT5
+param_manager_inst/param_modify_H/N120/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66865,42 +66644,27 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_H/pluse/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startY/N139/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_modify_H/cnt[11]/opit_0_AQ_perm;gopAQ
+param_manager_inst/param_offsetX/N122/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-param_manager_inst/ms_cnt[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/pluse/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -66916,7 +66680,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_H/N122/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/N63_mux11_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66926,23 +66690,17 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/change/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/N154_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_modify_H/N150_1/gateop_perm;gopLUT5
+udp_wr_mem_inst/N424/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -66952,7 +66710,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_V/N151_19/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/N153_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67042,7 +66800,7 @@ I13;1
I14;1
Inst
-udp_wr_mem_inst/flags[19]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/selected[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67058,17 +66816,33 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_H/N156_1/gateop_perm;gopLUT5
+param_manager_inst/param_modify_H/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_modify_V/value[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startX/N148_5/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/change/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67084,7 +66858,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_H/cnt[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67126,7 +66900,7 @@ I14;1
RS;1
Inst
-param_manager_inst/param_modify_H/cnt[2]/opit_0_L5Q;gopL5Q
+param_manager_inst/param_modify_H/cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67158,17 +66932,23 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/N20_mux2/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_rotate/cnt[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67264,7 +67044,7 @@ I14;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/N88/gateop_perm;gopLUT5
+param_manager_inst/param_modify_H/N102_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67274,7 +67054,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_S/N150_1/gateop_perm;gopLUT5
+param_manager_inst/param_modify_V/N63_mux8_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67284,23 +67064,17 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_H/value[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_S/N151_32/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/ms7200_ctl/state_reg[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/value[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67348,7 +67122,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_H/value[5]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/flags[20]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67412,7 +67186,27 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_S/value[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_S/N76_mux8_8/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+param_manager_inst/param_modify_S/N151_19/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+param_manager_inst/param_modify_S/value[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67428,7 +67222,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_S/N76_mux8_9/gateop_perm;gopLUT5
+param_manager_inst/param_modify_S/N140/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67438,7 +67232,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_S/N76_mux8_8/gateop_perm;gopLUT5
+param_manager_inst/param_modify_S/N142/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67448,39 +67242,27 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_S/value[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate_A/N148_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[2]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N484/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_modify_S/N149/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N46_mux9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67490,7 +67272,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_V/N149/gateop_perm;gopLUT5
+param_manager_inst/param_offsetY/N150_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67500,7 +67282,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_S/N151_19/gateop_perm;gopLUT5
+param_manager_inst/param_modify_S/N150_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67510,14 +67292,20 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/N116/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[21]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/param_modify_S/N151_10_1/gateop_A2;gopA2
@@ -67600,7 +67388,7 @@ I13;1
I14;1
Inst
-udp_wr_mem_inst/flags[21]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_S/value[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67616,7 +67404,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N133_7/gateop_perm;gopLUT5
+param_manager_inst/param_modify_H/N149/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67626,17 +67414,39 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetX/N63_mux11_4/gateop_perm;gopLUT5
+param_manager_inst/zoom_load/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_modify_S/value[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_S/value[5]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+param_manager_inst/param_modify_S/value[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67684,7 +67494,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_S/value[8]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_S/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67700,7 +67510,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_S/value[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_S/value[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67732,17 +67542,23 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_H/N120/gateop_perm;gopLUT5
+param_manager_inst/rotate_A_load/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_modify_H/N102_9/gateop_perm;gopLUT5
+param_manager_inst/param_rotate_A/N142/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67752,23 +67568,17 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_H/cnt[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_V/N76_mux8_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10_cpy/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N102_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67778,7 +67588,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_V/value[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_V/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -67794,17 +67604,23 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_V/N76_mux8_9/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_modify_S/N63_mux8_6/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/N72/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67814,7 +67630,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetY/N76_mux8_3/gateop_perm;gopLUT5
+param_manager_inst/param_modify_V/N150_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67824,23 +67640,17 @@ L3;1
L4;1
Inst
-param_manager_inst/selected[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_V/N149/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_filiter2_mode/N152_6/gateop_perm;gopLUT5
+param_manager_inst/param_modify_V/N154/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67850,20 +67660,14 @@ L3;1
L4;1
Inst
-param_manager_inst/selected[11]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/N150_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_modify_V/N151_10_1/gateop_A2;gopA2
@@ -67946,7 +67750,7 @@ I13;1
I14;1
Inst
-param_manager_inst/param_modify_V/N154/gateop_perm;gopLUT5
+udp_wr_mem_inst/N504/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67956,23 +67760,17 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/flags[23]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/N119/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_filiter1_mode/N102_8/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/N148_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -67982,23 +67780,17 @@ L3;1
L4;1
Inst
-param_manager_inst/param_modify_V/value[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter2_mode/N157_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_modify_V/value[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_V/value[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68030,7 +67822,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_V/value[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68046,17 +67838,23 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_S/N154/gateop_perm;gopLUT5
+param_manager_inst/param_modify_V/value[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_modify_V/value[8]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68088,7 +67886,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_V/value[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68104,20 +67902,14 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_S/value[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N58_mux9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_offsetX/N26_1.fsub_1/gateop_A2;gopA2
@@ -68160,23 +67952,17 @@ I13;1
I14;1
Inst
-u_rotate_image/cnt_w[0]/opit_0_inv_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/N63_mux6_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_rotate_image/cnt_h[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/value[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68192,27 +67978,39 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetX/N154_2/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/value[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_modify_V/N156_1/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_modify_V/N148_1/gateop_perm;gopLUT5
+param_manager_inst/param_offsetY/N76_mux8_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -68222,7 +68020,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetX/N102_12/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/N102_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -68232,7 +68030,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetX/N122/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/N102_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -68242,17 +68040,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_18/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_restore/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_filiter1_mode/cnt[9]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68268,7 +68072,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_7/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/N153/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -68278,7 +68082,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68294,17 +68098,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetX/N150_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-param_manager_inst/param_osd_char_height/N76_mux8_1/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/N151_19/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -68414,40 +68208,39 @@ I13;1
I14;1
Inst
-param_manager_inst/param_offsetX/N151_19/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/value[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_char_height/N149_28/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[15]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N35.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-param_manager_inst/param_osd_char_height/N148_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N257_13_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -68457,7 +68250,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetX/cnt[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/cnt[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68473,23 +68266,17 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/N102_11/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_osd_char_height/cnt[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68505,20 +68292,14 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_height/cnt[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/N102_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_offsetX/cnt[11]/opit_0_AQ_perm;gopAQ
@@ -68621,7 +68402,7 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_15/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/N63_mux10_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -68631,36 +68412,24 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_char_height/pluse/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N84/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_offsetX/value[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/N150_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_offsetX/value[2]/opit_0_L5Q_perm;gopL5Q
@@ -68695,20 +68464,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetX/N151_10_11/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-param_manager_inst/param_offsetX/value[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/value[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68724,23 +68480,17 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetX/value[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/N63_mux6_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_offsetX/value[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/value[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68756,7 +68506,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_height/value[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetX/value[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -68788,49 +68538,43 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetX/value[10]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/N139_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_offsetX/value[11]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N163_mux2_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_offsetX/N149/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/value[11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_offsetY/N76_mux6_4/gateop_perm;gopLUT5
+u_rotate_image/N131_mux1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -68840,7 +68584,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetY/N63_mux9_5/gateop_perm;gopLUT5
+param_manager_inst/param_offsetY/N63_mux5_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -68850,23 +68594,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/N63_mux9_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_offsetY/N151_10_11/gateop_perm;gopA
+param_manager_inst/param_rotate/N155_8_7/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -68879,7 +68617,7 @@ I3;1
I4;1
Inst
-param_manager_inst/param_osd_startY/N63_mux10_7/gateop_perm;gopLUT5
+u_rotate_image/N131_mux9_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -68889,7 +68627,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetY/N149/gateop_perm;gopLUT5
+param_manager_inst/param_offsetY/N76_mux6_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -68899,20 +68637,14 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/flags[17]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/N148_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_offsetY/N151_19/gateop_perm;gopLUT5
@@ -68924,6 +68656,22 @@ L2;1
L3;1
L4;1
+Inst
+param_manager_inst/selected[9]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
Inst
param_manager_inst/param_offsetY/N151_10_1/gateop_A2;gopA2
Pin
@@ -69025,7 +68773,20 @@ I13;1
I14;1
Inst
-param_manager_inst/param_osd_startY/value[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/N151_10_11/gateop;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+udp_wr_mem_inst/flags[18]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69041,17 +68802,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetY/N154_2/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-param_manager_inst/param_offsetX/value[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69067,7 +68818,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetY/value[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/value[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69083,7 +68834,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetY/value[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/value[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69099,7 +68850,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetY/value[8]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/value[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69115,23 +68866,17 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetY/value[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/N63_mux3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_offsetY/value[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/value[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69147,7 +68892,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetY/value[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/value[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69179,7 +68924,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetY/value[11]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/value[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69195,7 +68940,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetY/value[9]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/value[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69211,7 +68956,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetY/value[10]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_offsetY/value[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69227,17 +68972,23 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetY/N148_1/gateop_perm;gopLUT5
+param_manager_inst/param_offsetY/value[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_offsetY/value[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate/value[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69313,17 +69064,7 @@ I13;1
I14;1
Inst
-param_manager_inst/param_osd_char_height/N76_mux4_3/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-param_manager_inst/osd_char_width_load/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/value[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69339,23 +69080,17 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetX/value[8]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/N76_mux4_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_osd_char_height/N138/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux7_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -69365,7 +69100,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_char_height/value[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate/cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69381,7 +69116,17 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/flags[15]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/N154_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69397,7 +69142,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_height/N122/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/N102_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -69407,7 +69152,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_ac4/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/N102_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -69417,23 +69162,17 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_char_height/cnt[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/N122/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_osd_char_height/N102_12/gateop_perm;gopLUT5
+param_manager_inst/param_modify_V/N156_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -69443,7 +69182,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_char_width/N156_1/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/N149_28/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -69453,7 +69192,7 @@ L3;1
L4;1
Inst
-param_manager_inst/selected[5]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/flags[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69468,16 +69207,6 @@ L3;1
L4;1
RS;1
-Inst
-param_manager_inst/param_osd_char_height/N72/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
param_manager_inst/param_osd_char_height/N149_8_1/gateop_A2;gopA2
Pin
@@ -69579,17 +69308,7 @@ I13;1
I14;1
Inst
-param_manager_inst/param_osd_char_height/N154_2/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_wr_mem_inst/N264/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/N153/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -69599,17 +69318,23 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate_A/N156_1/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_char_width/N148_4/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux7_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -69635,7 +69360,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_height/cnt[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/cnt[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69651,39 +69376,54 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetX/N102_9/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_char_height/N102_9/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_char_height/cnt[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/cnt[11]/opit_0_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
@@ -69703,14 +69443,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_15/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/param_osd_char_height/cnt[8]/opit_0_A2Q21;gopA2Q2
@@ -69767,7 +69513,7 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_22/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/N102_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -69777,7 +69523,7 @@ L3;1
L4;1
Inst
-param_manager_inst/selected[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/selected[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69793,20 +69539,14 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_height/value[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/N63_mux10_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_osd_char_height/value[2]/opit_0_L5Q_perm;gopL5Q
@@ -69841,17 +69581,23 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/N344/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/value[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_char_height/value[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69867,7 +69613,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_height/value[8]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/value[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69883,7 +69629,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_height/value[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/value[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -69915,20 +69661,14 @@ L4;1
RS;1
Inst
-param_manager_inst/osd_char_height_load/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/N138_mux4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_osd_char_height/value[10]/opit_0_L5Q_perm;gopL5Q
@@ -69947,33 +69687,33 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_height/N153/gateop_perm;gopLUT5
+u_sync_vg/pos_x[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_width/N76_mux4_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_osd_char_width/N76_mux4_3/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/N63_mux10_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -69983,7 +69723,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_char_width/N149_28/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N63_mux10_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -69993,14 +69733,20 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_char_width/N76_mux9_2/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/value[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/param_osd_char_width/N76_mux9_4/gateop_perm;gopLUT5
@@ -70013,7 +69759,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/flags[10]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_width/value[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70029,7 +69775,17 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate_A/N139_1/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/N149_28/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+param_manager_inst/param_offsetX/N148_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70139,17 +69895,23 @@ I13;1
I14;1
Inst
-param_manager_inst/param_osd_char_width/N153/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_wr_mem_inst/N64/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/N156_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70159,23 +69921,17 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_char_width/value[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_width/N139/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_filiter1_mode/N152_5_3/gateop_perm;gopLUT5
+param_manager_inst/param_rotate_A/N139_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70185,7 +69941,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_char_width/value[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_width/value[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70233,7 +69989,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_width/value[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_width/value[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70249,20 +70005,17 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_width/value[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N483_11/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
param_manager_inst/param_osd_char_width/value[6]/opit_0_L5Q_perm;gopL5Q
@@ -70297,7 +70050,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/N144/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/N63_mux10_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70307,33 +70060,33 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_char_width/N63_mux10_8/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/value[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_char_width/value[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N416_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_offsetX/cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70389,17 +70142,23 @@ I13;1
I14;1
Inst
-param_manager_inst/param_rotate/N152_1/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_startX/N76_mux8_4/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N76_mux4_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70409,39 +70168,27 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startX/value[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startX/N76_mux8_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_osd_startX/pluse/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N591_14_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_osd_startX/cnt[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70457,7 +70204,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N70_ac2/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N122/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70467,7 +70214,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startX/N102_11/gateop;gopLUT5
+param_manager_inst/param_rotate/N102_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70477,17 +70224,23 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startX/N102_10/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[12]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_startX/N153_1/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N149_38/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70497,20 +70250,14 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startX/N156_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_osd_startX/N149_10_1/gateop_A2;gopA2
@@ -70613,7 +70360,7 @@ I13;1
I14;1
Inst
-param_manager_inst/param_osd_startX/N149_49/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N149_43_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70623,7 +70370,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startX/N154/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N149_49/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70633,7 +70380,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/flags[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startX/value[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70649,7 +70396,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startX/N156_3/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N154/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70659,7 +70406,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_32/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/N76_mux9_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70669,7 +70416,17 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/flags[6]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N144/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+param_manager_inst/param_osd_startX/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70685,7 +70442,17 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startX/cnt[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/N122/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+param_manager_inst/param_osd_startX/cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70717,33 +70484,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startX/cnt[2]/opit_0_L5Q;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-param_manager_inst/param_osd_startX/N122/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-param_manager_inst/param_zoom/value[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startX/cnt[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70858,17 +70599,23 @@ I14;1
RS;1
Inst
-param_manager_inst/N30/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/selected[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/selected[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70884,7 +70631,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startX/value[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startX/value[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70900,7 +70647,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startX/value[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startX/value[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70916,17 +70663,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N483_11/gateop_perm;gopA
+param_manager_inst/param_osd_startX/value[9]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
param_manager_inst/param_osd_startX/value[4]/opit_0_L5Q_perm;gopL5Q
@@ -70945,7 +70695,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/N244/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N374/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -70955,7 +70705,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startX/value[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startX/value[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70971,7 +70721,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startX/value[8]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startX/value[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -70987,7 +70737,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startX/value[9]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startX/value[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -71003,7 +70753,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startX/N63_mux10_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N432_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71029,49 +70779,53 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_width/N154/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/value[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_startY/value[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_restore/N20_mux2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/selected[10]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/N76_mux8_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[8]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/N50_mux2_7/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+param_manager_inst/param_osd_startY/value[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -71087,7 +70841,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startY/N76_mux7_4/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/N149_38/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71097,27 +70851,20 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N522_11/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-param_manager_inst/param_osd_startY/N156_6/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/param_osd_startY/N149_10_1/gateop_A2;gopA2
@@ -71220,7 +70967,7 @@ I13;1
I14;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux7_6/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/N154/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71230,7 +70977,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/N69_8/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/N149_49/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71240,17 +70987,23 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startY/N154/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/key_debounce_key_restore/pressed/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -71266,7 +71019,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/N364/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/N149_43_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71276,7 +71029,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startY/value[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startY/value[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -71308,17 +71061,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N23_mux7_3/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/value[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_startY/value[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startY/value[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -71334,17 +71093,23 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_V/N139_1/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/value[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_startY/value[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startY/value[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -71360,7 +71125,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/N184/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startY/N76_mux7_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71386,7 +71151,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startY/value[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -71418,20 +71183,14 @@ L4;1
RS;1
Inst
-param_manager_inst/osd_startY_load/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_startY/N63_mux10_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_rotate/N26_1.fsub_1/gateop_A2;gopA2
@@ -71474,7 +71233,7 @@ I13;1
I14;1
Inst
-udp_osd_inst/eth_udp_inst/N72_24/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/N63_mux7_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71484,7 +71243,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate/N63_mux7_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N422_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71494,7 +71253,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N124/gateop_perm;gopLUT5
+udp_wr_mem_inst/N64/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71504,27 +71263,39 @@ L3;1
L4;1
Inst
-u_zoom_image/N715_7/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_rotate/N122/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/cnt[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/N857_8[1]/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/N72/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71534,7 +71305,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate/N102_9/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/N122/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -71544,7 +71315,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate/value[7:0]_e_1/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/N152_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71554,17 +71325,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux10/gateop_perm;gopLUT5
+param_manager_inst/selected[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_rotate/N152_5_10/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/N152_5_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71574,7 +71351,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux7_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_58/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_wr_mem_inst/N524_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71644,14 +71431,20 @@ I13;1
I14;1
Inst
-param_manager_inst/param_osd_startX/N63_mux10_7/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/value[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/param_rotate/value[7:0]_e/gateop_perm;gopLUT5
@@ -71680,7 +71473,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate/cnt[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate/cnt[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -71696,7 +71489,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate/cnt[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/pluse/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -71738,52 +71531,43 @@ I14;1
RS;1
Inst
-param_manager_inst/param_rotate/cnt[5]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N184/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_image/cnt_w[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate/cnt[11]/opit_0_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/N20_mux4_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_rotate/cnt[8]/opit_0_A2Q21;gopA2Q2
@@ -71840,17 +71624,23 @@ I14;1
RS;1
Inst
-param_manager_inst/N9_mux9_4/gateop_perm;gopLUT5
+param_manager_inst/osd_char_height_load/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_zoom/N149_49/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -71876,20 +71666,14 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate/value[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate/value[7:0]_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_rotate/value[3]/opit_0_L5Q_perm;gopL5Q
@@ -71908,7 +71692,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate/value[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate/value[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -71924,21 +71708,40 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate/value[4]/opit_0_MUX4TO1Q;gopMUX4TO1Q
+param_manager_inst/param_rotate/value[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
-F;2
Q;2
RSOUT;2
+Z;2
CE;1
CLK;1
-I0;1
-I1;1
-I2;1
-I3;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
-S0;1
-S1;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N310_7_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+param_manager_inst/param_rotate/N152_5_8/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
param_manager_inst/param_rotate/value[7]/opit_0_L5Q_perm;gopL5Q
@@ -71957,24 +71760,17 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate/value[6]/opit_0_MUX4TO1Q;gopMUX4TO1Q
+param_manager_inst/param_rotate/value[7:0]_e_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-F;2
-Q;2
-RSOUT;2
-CE;1
-CLK;1
-I0;1
-I1;1
-I2;1
-I3;1
-RS;1
-S0;1
-S1;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/flags[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -71990,7 +71786,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/N164/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_35/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72000,17 +71796,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/N72_16/gateop_perm;gopLUT5
+param_manager_inst/param_rotate_A/value[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_rotate_A/N63_mux9_9/gateop_perm;gopLUT5
+param_manager_inst/param_rotate_A/N154/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72020,7 +71822,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/N14_6/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/N63_mux10_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72030,36 +71832,24 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetX/cnt[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate_A/N149_38/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N164/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_zoom/N156_1/gateop_perm;gopLUT5
@@ -72165,7 +71955,7 @@ I3;1
I4;1
Inst
-param_manager_inst/param_rotate_A/N149_49/gateop_perm;gopLUT5
+param_manager_inst/param_rotate_A/N149_43_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72185,7 +71975,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N324/gateop_perm;gopLUT5
+param_manager_inst/param_rotate_A/N156_23/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72195,7 +71985,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N304/gateop_perm;gopLUT5
+param_manager_inst/param_rotate_A/N156_20/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72205,17 +71995,23 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/N152_1/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_rotate_A/N156_21/gateop_perm;gopLUT5
+param_manager_inst/param_rotate_A/N156_26/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72225,17 +72021,23 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_53/gateop_perm;gopLUT5
+param_manager_inst/selected[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_rotate_A/N156_25/gateop_perm;gopLUT5
+udp_wr_mem_inst/N304/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72245,7 +72047,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate_A/value[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72261,7 +72063,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate_A/value[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate_A/value[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72309,7 +72111,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate_A/value[4]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate_A/value[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72325,7 +72127,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate_A/value[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate_A/value[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72341,7 +72143,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate_A/value[8]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate_A/value[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72357,17 +72159,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate_A/N149_38/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-param_manager_inst/param_rotate_A/N149_43_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_33/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72377,7 +72169,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate_A/value[9]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate_A/value[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72393,7 +72185,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N1918/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72403,7 +72195,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_zoom/N156_19/gateop_perm;gopLUT5
+param_manager_inst/param_rotate_A/N63_mux9_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72413,7 +72205,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_zoom/N148_1/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/N156_20/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72423,7 +72215,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_zoom/N148_5/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/N149_38/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72433,17 +72225,23 @@ L3;1
L4;1
Inst
-param_manager_inst/param_zoom/N149_43_1/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_wr_mem_inst/N484/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/N148_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72452,6 +72250,19 @@ L2;1
L3;1
L4;1
+Inst
+param_manager_inst/param_zoom/N149_10_9/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
Inst
param_manager_inst/param_zoom/N149_10_1/gateop_A2;gopA2
Pin
@@ -72533,17 +72344,23 @@ I13;1
I14;1
Inst
-param_manager_inst/param_zoom/N154/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/value[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_zoom/N149_38/gateop;gopLUT5
+param_manager_inst/param_zoom/N156_22/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72553,7 +72370,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_zoom/N156_25/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/N149_49/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72563,7 +72380,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_zoom/N156_22/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/N154/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72573,7 +72390,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_zoom/N156_21/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/N156_23/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72583,7 +72400,17 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/flags[14]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate_A/N149_49/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+param_manager_inst/param_zoom/value[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72599,7 +72426,7 @@ L4;1
RS;1
Inst
-u_zoom_image/N227_1_sum1_2/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/N156_26/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72609,7 +72436,7 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_left/N87/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/N142/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72635,17 +72462,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/N106_91/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-param_manager_inst/param_zoom/value[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_zoom/value[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72661,7 +72478,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_zoom/value[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_zoom/value[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72677,7 +72494,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_zoom/value[5]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_zoom/value[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72709,30 +72526,30 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/N727/gateop_perm;gopLUT5
+param_manager_inst/param_zoom/value[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_rotate/pluse/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/N30/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/param_zoom/value[7]/opit_0_L5Q_perm;gopL5Q
@@ -72751,7 +72568,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_zoom/value[8]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_zoom/value[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72767,36 +72584,24 @@ L4;1
RS;1
Inst
-param_manager_inst/param_zoom/value[9]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/N33_mux3_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/key_debounce_key_left/pressed/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_zoom/N149_43_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/rotate_A_flags_ff0/opit_0;gopQ
@@ -72843,7 +72648,7 @@ D;1
RS;1
Inst
-udp_wr_mem_inst/N549_21/gateop_perm;gopLUT5
+udp_wr_mem_inst/N444/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72885,23 +72690,17 @@ L3;1
L4;1
Inst
-param_manager_inst/selected[7]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N384/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/selected[6]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/selected[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -72917,7 +72716,7 @@ L4;1
RS;1
Inst
-u_zoom_image/N850_inv/gateop_perm;gopLUT5
+udp_wr_mem_inst/N524_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72927,7 +72726,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startX/N149_38/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_28/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72937,27 +72736,39 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/N161_1/gateop_perm;gopLUT5
+param_manager_inst/selected[11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_wr_mem_inst/N384/gateop_perm;gopLUT5
+param_manager_inst/selected[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_offsetX/N102_11/gateop_perm;gopLUT5
+param_manager_inst/param_offsetY/N148_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -72967,33 +72778,33 @@ L3;1
L4;1
Inst
-param_manager_inst/selected[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_15_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_sync_vg/N59_mux6/gateop_perm;gopLUT5
+param_manager_inst/selected[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/selected[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -73009,7 +72820,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_height/N63_mux4/gateop_perm;gopLUT5
+param_manager_inst/param_offsetY/N149/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -73019,7 +72830,7 @@ L3;1
L4;1
Inst
-param_manager_inst/selected[13]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/osd_startX_load/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -73035,7 +72846,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startX/cnt[0]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_modify_H/value[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -73051,14 +72862,20 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/N106_91/gateop_perm;gopLUT5
+param_manager_inst/key_debounce_key_left/pressed/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
param_manager_inst/zoom_flags_ff0/opit_0;gopQ
@@ -73105,7 +72922,7 @@ D;1
RS;1
Inst
-udp_wr_mem_inst/N104/gateop_perm;gopLUT5
+param_manager_inst/param_modify_S/N149/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -73579,7 +73396,7 @@ I4;1
RS;1
Inst
-u_ov5640/u_mix_image/N311_8/gateop_perm;gopLUT5
+N24_mux18_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -73610,7 +73427,7 @@ IN;1
MI;1
Inst
-ms72xx_ctl/ms7200_ctl/N1879_7/gateop_perm;gopLUT5
+param_manager_inst/N9_mux4_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -73649,20 +73466,14 @@ IN;1
MI;1
Inst
-image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv;gopCLKDIV
@@ -73693,7 +73504,7 @@ CLK;1
DIN;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N12_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -73836,7 +73647,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -73868,7 +73679,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -73884,7 +73695,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -73900,7 +73711,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -73949,7 +73760,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -73965,7 +73776,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -73981,7 +73792,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -74014,14 +73825,20 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cas_n/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -74074,7 +73891,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_resp_r/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -74124,23 +73941,14 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[15]/opit_0_inv_AQ_perm;gopAQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N175_8[0]/gateop;gopMUX4TO1
@@ -74308,7 +74116,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/N1_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N282_6_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74318,7 +74126,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N233_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N309_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74328,7 +74136,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N274/gateop_perm;gopLUT5
+u_axi_ddr_top/N93_mux8_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74338,7 +74146,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N282_6_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74348,7 +74156,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74358,55 +74166,37 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_16/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[30]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[89]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/N6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_10[2]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74416,7 +74206,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N228_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_12[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74426,7 +74216,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_13/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_16/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74436,17 +74226,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_16/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/fifo_vld/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -74462,7 +74258,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_10[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_4[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74472,7 +74268,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_12[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_7[2]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74492,7 +74288,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N0/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74502,7 +74298,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_4[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -74512,7 +74308,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -74528,7 +74324,107 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmrd_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[9]/opit_0_inv_AQ_perm;gopAQ
+Pin
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[2]/opit_0_inv_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[4]/opit_0_inv_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[6]/opit_0_inv_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmod_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -74544,7 +74440,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[2]/opit_0_inv_A2Q21;gopA2Q2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[0]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[7]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[2]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -74571,7 +74499,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[4]/opit_0_inv_A2Q21;gopA2Q2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[4]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -74598,136 +74526,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[6]/opit_0_inv_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmod_pass/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[0]/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[2]/opit_0_inv_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[4]/opit_0_inv_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[6]/opit_0_inv_A2Q21;gopA2Q2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[6]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -74862,7 +74661,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[88]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -74878,19 +74677,22 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[0]/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[15]/opit_0_inv_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
@@ -75083,7 +74885,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N124_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N113_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -75093,7 +74895,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_18/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N274/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -75103,17 +74905,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_8[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_txpr_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75129,7 +74937,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75253,27 +75061,39 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/N1_2_cpy/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N291_17/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75289,7 +75109,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75321,7 +75141,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75353,7 +75173,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[134]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75369,7 +75189,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75385,20 +75205,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[8]/opit_0_inv_L5Q_perm;gopL5Q
@@ -75417,7 +75231,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75433,7 +75247,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75481,7 +75295,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75497,7 +75311,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75513,23 +75327,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75545,7 +75353,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cs_n/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75572,7 +75380,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75604,7 +75412,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_7[2]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -75625,39 +75433,24 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cke_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_12[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[9]/opit_0_inv_AQ_perm;gopAQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_10[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_8[1]/gateop;gopMUX4TO1
@@ -75671,7 +75464,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_10[2]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -75681,7 +75474,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N309_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_11[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -75691,23 +75484,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_12[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_8[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -75717,7 +75504,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -75727,7 +75514,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_11[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -75737,30 +75524,39 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/axi_fifo_full0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[15]/opit_0_inv_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N530_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv;gopQ
@@ -75774,7 +75570,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75790,7 +75586,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75806,7 +75602,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/init_start/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75822,7 +75618,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75838,23 +75634,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N285/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75870,7 +75660,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -75886,7 +75676,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N235_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N232_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -75912,7 +75702,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N235_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -75965,7 +75755,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cs_n/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76036,7 +75826,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76084,14 +75874,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/wrlvl_start/opit_0_inv_L5Q_perm;gopL5Q
@@ -76110,23 +75906,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N141_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N176_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76136,23 +75926,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_tmod_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N124_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/dbg_wrlvl_or[1]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/dbg_wrlvl_or[0]_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76162,7 +75946,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/dbg_wrlvl_or[0]_8/gateop_perm;gopLUT5
+u_axi_ddr_top/wr_sta_fsm[3:0]_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76172,22 +75956,19 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[7]/opit_0_inv_AQ_perm;gopAQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_tmod_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
-Cout;2
Q;2
RSOUT;2
-Y;2
+Z;2
CE;1
CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
@@ -76288,14 +76069,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/N84_10[1]_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_twldqsen_pass/opit_0_inv;gopQ
@@ -76329,27 +76116,39 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5
+u_axi_ddr_top/cnt_wr_num[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_odt/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76365,7 +76164,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76381,7 +76180,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76397,17 +76196,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[3]_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76423,7 +76228,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[5]/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76439,23 +76244,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[7]/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[96]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76471,7 +76270,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76487,7 +76286,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76503,7 +76302,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76535,7 +76334,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[41]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76551,7 +76350,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_odt/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_resp_r/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76567,7 +76366,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n/opit_0_inv_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76594,7 +76393,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_odt/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76610,7 +76409,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76626,7 +76425,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt_trfc_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76642,7 +76441,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76658,7 +76457,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_79/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76700,20 +76499,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N141_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
@@ -76732,27 +76525,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N176_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N10_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/wr_enable/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76768,7 +76557,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N781_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N124_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76778,7 +76567,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N671/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_25/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76788,7 +76577,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N530_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76798,7 +76587,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_25/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N530_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76808,7 +76597,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N370_2_or[0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76818,7 +76607,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76828,17 +76617,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt_trfc_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N819_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76848,17 +76643,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_9/gateop_perm;gopLUT5
+u_axi_ddr_top/N180_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76868,7 +76669,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76878,17 +76679,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N679_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[168]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N679_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76898,23 +76705,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ras_n/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N38_12/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N760_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76924,7 +76725,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N671/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76934,7 +76735,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N679_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76944,7 +76745,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76954,7 +76755,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -76970,7 +76771,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_78/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76980,7 +76781,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N685/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -76990,7 +76791,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/N84_10[1]_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77000,7 +76801,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_34/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/N84_10[2]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77010,17 +76811,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77030,44 +76837,43 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_success/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_45_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_68/gateop;gopMUX4TO1
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N265_11/gateop_perm;gopLUT5
Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/N84_10[2]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N781_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77077,7 +76883,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77103,17 +76909,34 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N760_1/gateop;gopMUX4TO1
+Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[15:0]_622_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77123,7 +76946,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N1814/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77133,7 +76956,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/N18/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77143,40 +76966,55 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N819_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -77195,7 +77033,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N685/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_21/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77420,7 +77258,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_79/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77430,7 +77268,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rddata_cal/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ras_n/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77446,14 +77284,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[1]/opit_0_inv;gopQ
@@ -77478,23 +77322,17 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_34/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_64/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_74/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77504,7 +77342,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/reinit_adj_rdel/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[209]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77520,7 +77358,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ba[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77547,7 +77385,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cs_n/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ba[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77579,7 +77417,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cs_n/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77595,7 +77433,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rddata_cal/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77611,14 +77449,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N440_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_odt/opit_0_inv;gopQ
@@ -77632,7 +77476,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_29/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77642,17 +77486,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_44/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77662,7 +77512,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77678,7 +77528,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_65/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77688,7 +77538,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77715,7 +77565,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77742,7 +77592,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77785,7 +77635,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77817,7 +77667,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77833,7 +77683,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77849,17 +77699,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N674_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[16]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N679_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77896,20 +77752,14 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[16]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N674_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[17]/opit_0_inv_L5Q_perm;gopL5Q
@@ -77928,7 +77778,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_76/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -77938,39 +77788,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_calibration/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_inv/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N238/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[106]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[32]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -77986,7 +77824,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[160]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[64]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78002,7 +77840,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[102]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78018,17 +77856,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N409/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[35]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[36]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[160]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78044,7 +77888,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78086,7 +77930,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[100]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[32]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78102,7 +77946,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[164]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[40]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78118,7 +77962,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/wr_enable/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[175]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78134,7 +77978,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78161,7 +78005,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_45_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N679_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -78187,7 +78031,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_68/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -78229,7 +78073,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_60/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -78239,33 +78083,33 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_72/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[147]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/dbg_wrlvl_or[1]_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N10_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -78275,17 +78119,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_313/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cas_n/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -78295,23 +78145,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[5]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N232_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -78332,17 +78176,20 @@ D;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[0]/opit_0_inv;gopQ
@@ -78653,7 +78500,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[30]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78669,17 +78516,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78695,7 +78548,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[33]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78711,7 +78564,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[41]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78727,7 +78580,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78743,33 +78596,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[16]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[3]_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78785,7 +78638,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78801,23 +78654,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2048_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78833,7 +78680,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[31]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78849,7 +78696,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78865,7 +78712,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78881,7 +78728,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_act/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78897,7 +78744,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[33]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[32]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78913,7 +78760,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_l/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78929,7 +78776,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[36]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -78945,20 +78792,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[37]/opit_0_inv_L5Q_perm;gopL5Q
@@ -78993,7 +78834,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[19]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -79009,7 +78850,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -79041,24 +78882,36 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N524_7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[0]/opit_0_inv;gopQ
@@ -79127,23 +78980,17 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N167_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N233_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -79153,20 +79000,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1025_1_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[8]/opit_0_inv_L5Q_perm;gopL5Q
@@ -79185,7 +79026,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cwl_3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N544_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -79195,20 +79036,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n[0]/opit_0_inv;gopQ
@@ -79233,7 +79068,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -79249,7 +79084,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -79276,7 +79111,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[108]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -79314,19 +79149,22 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[7]/opit_0_inv_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
@@ -79384,20 +79222,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_odt/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n[0]/opit_0_inv;gopQ
@@ -79422,17 +79254,23 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -79470,7 +79308,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -79486,14 +79324,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cke/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[0]/opit_0_inv;gopQ
@@ -82312,7 +82156,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[35]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82328,7 +82172,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[97]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[103]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82344,7 +82188,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[71]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82360,7 +82204,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[68]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[131]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82376,7 +82220,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[34]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82392,17 +82236,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[132]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[70]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82418,7 +82268,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[65]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[130]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82434,7 +82284,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[72]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82450,7 +82300,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[237]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82466,7 +82316,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[136]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82482,7 +82332,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[205]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[75]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82498,7 +82348,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[204]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[72]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82514,17 +82364,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N252/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[73]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[75]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[78]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82540,7 +82396,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[207]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82556,7 +82412,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[17]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[144]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82572,7 +82428,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[20]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[145]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82588,7 +82444,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[145]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[82]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82604,7 +82460,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[23]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[85]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[21]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82635,6 +82507,22 @@ L3;1
L4;1
RS;1
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[86]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[83]/opit_0_inv_L5Q_perm;gopL5Q
Pin
@@ -82652,7 +82540,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[150]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[89]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82668,7 +82556,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[85]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[95]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82684,7 +82572,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[25]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[27]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82700,7 +82588,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[222]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[157]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82716,7 +82604,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[28]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[29]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82732,7 +82620,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[95]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[221]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82748,7 +82636,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[158]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[179]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82780,7 +82668,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[31]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[160]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82796,7 +82684,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[159]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[227]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82812,7 +82700,55 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[160]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[98]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[38]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[106]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[128]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82844,7 +82780,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[98]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82860,7 +82796,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[96]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[168]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82876,7 +82812,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[42]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[74]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82892,7 +82828,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[99]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[100]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82908,7 +82844,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[129]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[45]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82924,7 +82860,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[166]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[108]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82940,7 +82876,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[104]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[46]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82972,7 +82908,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[234]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[204]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -82988,7 +82924,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[45]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[60]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83004,7 +82940,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[168]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83020,23 +82956,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[169]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3402/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[74]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[55]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83052,7 +82982,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[76]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[53]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83068,7 +82998,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[112]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[116]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83084,7 +83014,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[240]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[120]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83100,7 +83030,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[53]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[56]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83116,7 +83046,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[55]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[244]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83132,7 +83062,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[54]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[59]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83148,23 +83078,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[180]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[178]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[63]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83180,7 +83104,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[179]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[121]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83196,7 +83120,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[58]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[62]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83212,7 +83136,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[126]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[189]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83228,7 +83152,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[188]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[185]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83244,7 +83168,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[63]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[66]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83260,7 +83184,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[122]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[69]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83276,7 +83200,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[123]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[71]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83292,7 +83216,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[125]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[70]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83308,7 +83232,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[253]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[129]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83324,7 +83248,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[68]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[192]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83340,7 +83264,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[194]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[198]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83356,7 +83280,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[128]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[196]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83372,7 +83296,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[195]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[76]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83388,17 +83312,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N124_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[131]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[201]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83414,7 +83328,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[134]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[138]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83430,7 +83344,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[193]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[139]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83446,7 +83360,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[111]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83462,7 +83376,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[77]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[137]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83478,7 +83392,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[137]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[142]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83494,23 +83408,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[78]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[109]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[81]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83526,7 +83434,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[142]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[18]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83542,7 +83450,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[206]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[210]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83558,7 +83466,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[143]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[87]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83574,17 +83482,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[208]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83600,7 +83498,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[86]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[151]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83616,7 +83514,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[87]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[150]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83632,7 +83530,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[144]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83648,7 +83546,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[215]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[90]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83664,7 +83562,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[210]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[91]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83680,7 +83578,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[147]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[92]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83696,23 +83594,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[223]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[217]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[156]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83728,17 +83623,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[93]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[217]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83754,7 +83639,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[216]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[155]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83770,7 +83655,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[221]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[122]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83786,17 +83671,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N232_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[153]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83812,7 +83687,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[161]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83828,7 +83703,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[225]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[162]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83844,7 +83719,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[101]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83860,7 +83735,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[101]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[228]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83876,7 +83751,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[228]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[163]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83892,7 +83767,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[167]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[229]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83908,7 +83783,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[103]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[166]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83924,7 +83799,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[230]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[171]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83940,7 +83815,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[105]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[110]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83956,7 +83831,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[164]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83972,7 +83847,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[170]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[47]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -83988,7 +83863,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[171]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[172]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84004,17 +83879,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[136]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[169]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84030,7 +83895,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[235]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[111]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84046,7 +83911,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[174]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[233]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84062,7 +83927,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[241]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[113]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84078,23 +83943,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[114]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[115]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[246]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84110,7 +83969,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[242]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[117]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84126,7 +83985,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[117]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[241]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84142,7 +84001,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[118]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[184]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84174,7 +84033,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[124]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84190,7 +84049,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[248]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[180]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84206,7 +84065,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[127]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[251]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84222,7 +84081,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[124]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[188]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84238,7 +84097,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[187]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84254,7 +84113,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[252]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[222]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84270,7 +84129,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[183]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[126]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84286,7 +84145,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[127]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84302,7 +84161,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[191]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[253]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84318,23 +84177,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[132]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[165]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[135]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84350,7 +84203,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[192]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84366,23 +84219,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[197]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[229]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[133]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84398,7 +84245,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[135]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[99]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84414,7 +84261,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[198]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[195]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84430,23 +84277,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[200]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84462,7 +84303,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[200]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[205]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84510,23 +84351,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[202]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[201]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[143]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84542,7 +84377,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[207]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[206]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84558,23 +84393,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[148]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84590,7 +84419,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[146]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84606,23 +84435,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[16]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[208]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84638,7 +84461,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[213]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[212]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84654,7 +84477,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[151]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84670,7 +84493,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[52]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[214]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84686,23 +84509,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[211]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[153]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84718,7 +84535,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[155]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[186]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84734,7 +84551,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[156]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[158]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84750,17 +84567,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[216]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[157]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[26]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84776,7 +84599,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[94]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[159]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84792,7 +84615,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3376/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -84802,7 +84625,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[219]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[95]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84818,7 +84641,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[161]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[224]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84834,7 +84657,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[163]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[225]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84850,7 +84673,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[224]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[226]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84866,7 +84689,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[96]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[165]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84882,7 +84705,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[170]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84898,7 +84721,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[231]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N228_10/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[167]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84914,7 +84747,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[227]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84930,17 +84763,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_12/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[232]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[232]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[237]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84956,7 +84795,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N475/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -84966,7 +84805,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[172]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[173]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84982,7 +84821,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[175]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[236]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -84998,7 +84837,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[44]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[174]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85014,17 +84853,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85040,7 +84869,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[200]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85056,17 +84885,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_316/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[183]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[181]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[249]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85082,7 +84917,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[182]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[181]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85098,7 +84933,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[219]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85114,7 +84949,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[182]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85130,7 +84965,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[243]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[250]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85146,7 +84981,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[178]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[241]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85162,7 +84997,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[251]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[248]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85178,7 +85013,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[186]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[245]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85194,7 +85029,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -85204,23 +85039,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[250]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3410/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[189]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[191]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85236,7 +85065,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85268,7 +85097,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[255]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[123]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85284,33 +85113,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[249]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[15:0]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[197]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[199]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[194]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85326,23 +85155,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[196]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136_7/gateop_perm;gopLUT5
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -85352,7 +85175,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85368,17 +85191,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[193]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[192]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[199]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85394,7 +85223,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[37]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[64]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85410,7 +85239,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[73]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[202]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85426,55 +85255,37 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[203]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[233]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start_rst/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85490,7 +85301,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85506,7 +85317,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N633_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -85516,7 +85327,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N637_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -85526,7 +85337,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[209]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[211]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85542,39 +85353,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N13_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[214]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[212]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[84]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85590,23 +85389,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[209]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[18]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85622,7 +85415,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3423/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85638,17 +85441,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N645_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[218]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[218]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[220]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85664,17 +85473,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_13/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[88]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[220]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[252]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85690,7 +85505,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -85700,7 +85515,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[222]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85716,7 +85531,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[90]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[94]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85732,7 +85547,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[31]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85748,17 +85563,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[226]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[34]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85774,7 +85579,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[162]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[229]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85790,7 +85595,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[128]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85806,7 +85611,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[230]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[230]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85822,7 +85627,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[234]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85838,7 +85643,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[38]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85854,17 +85659,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[231]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[227]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[97]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85880,17 +85691,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[235]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[46]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85906,14 +85723,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[44]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[238]/opit_0_inv_L5Q_perm;gopL5Q
@@ -85932,7 +85755,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85948,7 +85771,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start_rst/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -85980,23 +85803,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[74]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[245]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[242]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86012,7 +85829,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[244]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[116]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86028,7 +85845,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[243]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86044,7 +85861,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[246]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[247]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86060,23 +85877,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[49]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N538/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[247]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[52]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86092,23 +85903,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[113]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N279_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[114]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[247]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86124,7 +85929,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[24]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86140,17 +85945,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[255]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[93]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86166,17 +85977,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N151_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[176]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[27]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[88]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86192,23 +86009,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[254]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[187]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86224,23 +86035,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[123]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[128]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86256,17 +86061,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[234]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86282,20 +86093,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[0]/opit_0_inv;gopQ
@@ -86331,7 +86136,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[24]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86347,7 +86152,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[24]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86363,7 +86168,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86379,14 +86184,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_11/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N95_4/gateop;gopMUX4TO1
@@ -86400,20 +86211,14 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N465_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -86476,7 +86281,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N38_12/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N124_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -86556,23 +86361,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86588,7 +86387,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -86598,7 +86397,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[135]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86613,6 +86412,16 @@ L3;1
L4;1
RS;1
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[0]_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm;gopLUT5
Pin
@@ -86624,7 +86433,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -86634,7 +86443,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[15:0]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N382_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -86644,23 +86453,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[130]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[128]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[15:0]_5/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[198]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86676,7 +86489,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N382_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -86686,7 +86499,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86702,7 +86525,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[15:0]_1268/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -86712,23 +86535,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[64]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86744,7 +86561,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cke_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86760,23 +86577,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[171]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N232_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cwl_3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -86786,7 +86597,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -86836,7 +86647,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cas_n/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86961,7 +86772,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -86977,7 +86788,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87009,7 +86820,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87025,7 +86836,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87041,23 +86852,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[67]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87073,7 +86878,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87089,7 +86894,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87105,7 +86910,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87121,17 +86926,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N25_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87147,7 +86942,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87163,17 +86958,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87189,23 +86974,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[15:0]_416_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87221,7 +87000,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87237,7 +87016,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87253,7 +87032,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87269,7 +87048,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87285,7 +87064,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87317,7 +87096,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[195]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87333,7 +87112,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87349,7 +87128,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87365,7 +87144,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87381,7 +87160,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[64]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87413,17 +87208,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87439,7 +87240,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[15:0]_1285/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N124_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87455,7 +87276,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87471,7 +87292,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87487,7 +87308,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87503,7 +87324,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87519,7 +87350,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87535,7 +87366,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87551,7 +87382,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87567,17 +87398,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87593,7 +87430,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87609,7 +87446,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[23]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87625,7 +87462,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1286_4/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87641,7 +87488,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87657,7 +87504,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87673,37 +87520,55 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N265_11/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87719,7 +87584,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87735,7 +87610,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87751,7 +87626,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87767,7 +87652,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[3]/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87783,7 +87668,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87799,7 +87684,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87815,7 +87700,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87831,7 +87716,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87847,7 +87732,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87863,7 +87758,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87879,7 +87774,80 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[0]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29_1_1/gateop_A2;gopA2
+Pin
+Cout;2
+Y0;2
+Y1;2
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29_1_3/gateop_A2;gopA2
+Pin
+Cout;2
+Y0;2
+Y1;2
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29_1_5/gateop_A2;gopA2
+Pin
+Cout;2
+Y0;2
+Y1;2
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29_1_7/gateop;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_101/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -87889,7 +87857,47 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N240_5/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_113/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N241_6_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_104/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87905,7 +87913,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87921,7 +87929,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87937,7 +87945,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[198]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87953,7 +87961,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[102]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87969,7 +87977,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_1_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -87979,7 +87987,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -87995,17 +88003,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_65_3/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_34_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_136/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88015,117 +88013,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_AQ_perm;gopAQ
-Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/opit_0_inv_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]/opit_0_inv_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_1_4/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_neg/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg/opit_0_inv_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88152,20 +88040,14 @@ D;1
RS;1
Inst
-rstn_5s/opit_0_inv_L5Q_perm;gopL5Q
+u_rotate_image/N52_mux6_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N11_1_1/gateop_A2;gopA2
@@ -88348,7 +88230,20 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/s_axi_rdata0[87]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N161.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88364,7 +88259,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_111/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88374,7 +88269,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36_cpy/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88384,7 +88279,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88394,7 +88289,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88410,7 +88305,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88426,7 +88321,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88442,7 +88337,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88458,7 +88353,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88474,7 +88369,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88490,7 +88385,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88506,7 +88401,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88522,7 +88417,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88538,7 +88433,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88570,7 +88465,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88586,7 +88481,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88602,7 +88497,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88618,7 +88513,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88634,7 +88529,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88682,24 +88577,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_15/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N39.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv;gopQ
@@ -88713,23 +88617,17 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_deb_pre/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_29/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88816,17 +88714,23 @@ D;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88847,7 +88751,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_106/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_1_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88857,7 +88761,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_105/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_62/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88867,7 +88771,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_101/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88877,23 +88781,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_129/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N84/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88903,7 +88801,7 @@ L3;1
L4;1
Inst
-_N18115_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_106/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88913,7 +88811,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_39/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -88923,7 +88821,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88939,7 +88837,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -88987,23 +88885,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_65_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89019,7 +88911,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89035,23 +88927,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N84/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89061,7 +88947,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89148,23 +89034,17 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_29/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[33]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89180,7 +89060,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[212]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89196,27 +89076,52 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N21_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA
Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89226,17 +89131,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[96]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/N4_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89246,7 +89157,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_129/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89256,7 +89167,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89339,7 +89250,7 @@ I3;1
I4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_75/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89381,7 +89292,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89391,7 +89302,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89407,7 +89318,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89439,7 +89350,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89455,7 +89366,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89471,39 +89382,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7:0]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/N18/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89513,7 +89412,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89528,16 +89427,6 @@ L3;1
L4;1
RS;1
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0;gopDQS_DDC
Pin
@@ -89775,17 +89664,7 @@ WL_STEP[6];1
WL_STEP[7];1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N265_11/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_82/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89795,17 +89674,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[96]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_115/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89815,7 +89700,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89831,7 +89716,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89847,7 +89732,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89863,7 +89748,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89879,7 +89764,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89889,7 +89774,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_137_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N370_2_or[0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89899,7 +89784,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_137_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89909,7 +89794,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89919,7 +89804,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[80]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89935,23 +89820,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N22/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89961,7 +89840,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -89971,17 +89850,33 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_105/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -89997,7 +89892,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -90013,17 +89908,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[219]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -90039,7 +89940,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -90049,39 +89950,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[121]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[251]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[13]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[14]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -90091,23 +89980,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[15]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[15]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -90117,7 +90000,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[91]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -90573,20 +90456,14 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_113_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -90673,23 +90550,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[13]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -90705,20 +90576,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv;gopQ
@@ -90820,7 +90685,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N161_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -90846,7 +90711,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -90856,7 +90721,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -90866,7 +90731,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_103/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_78/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -90903,17 +90768,23 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -90973,7 +90844,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -90983,7 +90854,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91015,7 +90886,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N306_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91025,7 +90896,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91086,7 +90957,68 @@ S10;1
S11;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[0]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[1]/gateop;gopMUX4TO1
+Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91102,7 +91034,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_109/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N138/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91112,94 +91044,33 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_83/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_131/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[1]/gateop;gopMUX4TO1
-Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91209,7 +91080,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_0/gateop_A2;gopA2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_1/gateop_A2;gopA2
Pin
Cout;2
Y0;2
@@ -91229,7 +91100,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_2/gateop_A2;gopA2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_3/gateop_A2;gopA2
Pin
Cout;2
Y0;2
@@ -91249,27 +91120,20 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_4/gateop_A2;gopA2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_5/gateop;gopA
Pin
Cout;2
-Y0;2
-Y1;2
+Y;2
Cin;1
+I0;1
I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_111/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91279,7 +91143,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91289,7 +91153,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N124_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91299,7 +91163,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N431_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91309,18 +91173,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N328_10/gateop;gopMUX4TO1
-Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91335,6 +91188,16 @@ L3;1
L4;1
RS;1
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
@@ -91368,7 +91231,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91389,17 +91252,23 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91415,7 +91284,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91431,7 +91300,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91458,7 +91327,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[119]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91474,7 +91343,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91490,23 +91359,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91538,14 +91401,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -91564,7 +91433,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91596,14 +91465,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3383/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm;gopL5Q
@@ -91622,14 +91497,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv;gopQ
@@ -91730,7 +91611,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91746,22 +91627,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21;gopA2Q2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/opit_0_inv_A2Q1;gopA2Q1
Pin
CEOUT;2
Cout;2
-Q0;2
-Q1;2
+Q;2
RSOUT;2
Y0;2
Y1;2
@@ -91783,7 +91669,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21;gopA2Q2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -91810,36 +91696,50 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ;gopAQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
-Q;2
+Q0;2
+Q1;2
RSOUT;2
-Y;2
+Y0;2
+Y1;2
CE;1
CLK;1
Cin;1
-I0;1
I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91849,7 +91749,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N409/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91859,39 +91759,38 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[225]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[66]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N72/gateop;gopMUX4TO1
+Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91907,7 +91806,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N124_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91917,7 +91816,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91927,23 +91826,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[133]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N136_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -91953,7 +91846,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -91969,33 +91862,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[37]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92011,7 +91904,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -92021,7 +91914,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92037,39 +91930,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[132]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -92079,7 +91960,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -92089,27 +91970,58 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm;gopAQ
+Pin
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[236]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -92119,7 +92031,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92135,17 +92047,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -92166,17 +92084,23 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N228_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7:0]_388/gateop_perm;gopLUT5
+u_axi_ddr_top/N129/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -92186,7 +92110,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -92212,17 +92136,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[65]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92238,7 +92168,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_9/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[238]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92253,17 +92193,6 @@ L3;1
L4;1
RS;1
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N475_1/gateop;gopMUX4TO1
-Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
-
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q
Pin
@@ -92369,23 +92298,14 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm;gopAQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21;gopA2Q2
@@ -92469,7 +92389,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92485,21 +92405,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
-F;2
Q;2
RSOUT;2
+Z;2
CE;1
CLK;1
-I0;1
-I1;1
-I2;1
-I3;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
-S0;1
-S1;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -92518,7 +92437,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92534,7 +92453,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92550,14 +92469,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N124_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[42]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -92577,40 +92502,46 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7:0]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N124_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1;gopA2Q1
@@ -92820,7 +92751,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -92846,14 +92777,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -92872,7 +92809,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92888,7 +92825,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92904,7 +92841,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92920,17 +92857,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[104]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92962,7 +92905,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92978,7 +92921,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -92994,23 +92937,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -93026,20 +92963,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[67]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N151_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -93059,20 +92990,14 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_377/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -93091,7 +93016,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -93107,7 +93032,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -93165,47 +93090,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_11/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[3]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N232_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N228_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -93215,7 +93100,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -93236,23 +93121,17 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -93268,7 +93147,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -93305,7 +93184,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -93369,20 +93248,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm;gopL5Q
@@ -93401,7 +93274,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -93881,27 +93754,7 @@ MI;1
T;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -93911,7 +93764,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -93931,17 +93784,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_107/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_51/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -93951,7 +93810,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_92/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_35/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -93961,7 +93820,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[34]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -93977,7 +93836,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_56/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_43/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -93987,23 +93846,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_70/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_117/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94013,23 +93866,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_94/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_96/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_125/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94039,7 +93886,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -94055,7 +93902,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_99/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_76/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94065,7 +93912,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_97/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94075,7 +93922,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_69/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_109/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94085,7 +93932,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_52/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_121/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94095,17 +93942,43 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_48/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[129]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_130/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -94121,27 +93994,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_119/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[38]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_123/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[32]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[132]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[230]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -94157,7 +94042,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N16_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_137/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94167,7 +94052,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_84/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_90/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94177,7 +94062,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_64/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_66/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94187,7 +94072,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94197,7 +94082,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N161_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94207,7 +94092,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_55/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -94217,57 +94102,87 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N637_6/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[133]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_76/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[134]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_88/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[35]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -94299,7 +94214,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[85]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -94331,7 +94246,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -94347,20 +94262,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N21_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
@@ -94379,17 +94288,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N669_74_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3453/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N21_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -95103,20 +95018,14 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_cal_vld/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/N18/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv;gopQ
@@ -95130,17 +95039,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N67_1_sum3/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N14/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -95150,7 +95049,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -95166,20 +95065,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[24]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N28_1.fsub_0/gateop_A2;gopA2
@@ -95242,7 +95148,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -95444,20 +95350,14 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N384_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N85_1/gateop_A2;gopA2
@@ -95580,20 +95480,14 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3384/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_0/gateop_A2;gopA2
@@ -95636,23 +95530,17 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -95662,39 +95550,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -95704,17 +95580,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N683_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_inc_dec_n/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -95730,7 +95612,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N446_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -95740,7 +95622,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N451_or[0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -95750,7 +95632,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -95760,23 +95642,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N683_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[202]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -95825,7 +95701,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[73]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[146]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -95841,7 +95717,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -95857,7 +95753,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -95873,7 +95769,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -95883,7 +95779,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N13_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -95893,23 +95789,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3387/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[139]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -95925,7 +95815,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3422/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N669_74_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -95935,17 +95825,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[218]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -95971,113 +95867,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[69]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[85]/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N701_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3393/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -96087,7 +95897,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[217]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96103,17 +95913,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/s_axi_rdata0[109]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96129,7 +95929,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96177,20 +95977,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N28_1.fsub_6/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[0]/opit_0_inv_L5Q_perm;gopL5Q
@@ -96209,23 +96006,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[0]/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96368,20 +96149,17 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3396/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96397,7 +96175,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96413,7 +96191,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[36]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96429,7 +96207,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[21]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96445,14 +96223,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[7]/opit_0_inv_L5Q_perm;gopL5Q
@@ -96471,7 +96255,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96487,23 +96271,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -96620,7 +96398,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96636,7 +96414,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96652,7 +96430,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_inc_dec_n/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96668,7 +96446,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96684,20 +96462,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[89]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96713,17 +96494,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[7]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -96743,17 +96527,23 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96797,7 +96587,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -96845,14 +96635,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv;gopQ
@@ -96899,14 +96692,20 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N446_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[146]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/reinit_adj_rdel_d/opit_0_inv;gopQ
@@ -96920,7 +96719,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97037,7 +96836,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97047,23 +96846,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[67]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3385/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97073,7 +96866,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3446/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3394/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97083,7 +96876,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97093,7 +96886,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97103,7 +96896,102 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3390/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3395/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[253]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3399/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[61]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_865/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97129,7 +97017,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97172,7 +97060,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97188,7 +97076,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97231,7 +97119,17 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_4/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97247,7 +97145,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N637_7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97257,7 +97155,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N252/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97266,19 +97164,6 @@ L2;1
L3;1
L4;1
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21;gopA2Q2
Pin
@@ -97565,7 +97450,7 @@ T[3];1
TCLK;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_68/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97575,7 +97460,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_80/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97585,20 +97470,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N28_1.fsub_6/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97614,7 +97486,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97630,7 +97512,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[36]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97656,7 +97538,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97672,7 +97554,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[97]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97742,16 +97624,6 @@ CLK;1
D;1
RS;1
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5
Pin
@@ -97763,7 +97635,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N228_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97773,7 +97645,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97789,7 +97661,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -97799,7 +97671,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97815,7 +97687,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97831,7 +97703,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97847,20 +97719,24 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[176]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_86/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -97947,7 +97823,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -97979,7 +97855,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98094,7 +97970,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -98120,7 +97996,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -98130,7 +98006,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_47/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -98140,7 +98016,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[51]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98166,7 +98042,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -98198,30 +98074,30 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[129]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_13[3]/gateop;gopMUX4TO1
@@ -98275,7 +98151,7 @@ S10;1
S11;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -98285,23 +98161,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_125/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -98321,7 +98191,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98348,7 +98218,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -98358,23 +98228,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -98444,23 +98308,17 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/s_axi_rdata0[14]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98487,20 +98345,14 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N328_7/gateop;gopMUX4TO1
@@ -98573,7 +98425,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98600,7 +98452,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98616,7 +98468,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98675,17 +98527,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_121/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98701,7 +98543,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98717,7 +98559,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98733,7 +98575,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -98743,17 +98585,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_69/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98769,7 +98617,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98785,7 +98633,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98801,7 +98649,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98817,7 +98665,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98833,7 +98681,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N294_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -98925,7 +98783,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N17_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -98935,7 +98793,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -98951,7 +98809,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99040,7 +98898,7 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -99050,7 +98908,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N1814/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -99060,7 +98918,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N124_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N124_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -99070,23 +98928,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N228_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -99096,17 +98948,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N124_6/gateop_perm;gopLUT5
+u_axi_ddr_top/wr_sta_reg[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[77]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99122,7 +98980,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N151_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_378/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -99132,17 +98990,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N113_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N228_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -99152,17 +99016,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -99172,7 +99042,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[33]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99188,33 +99058,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N265_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[79]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[174]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[136]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99230,7 +99100,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[47]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[200]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99246,7 +99116,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99262,7 +99132,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[203]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99278,7 +99148,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -99288,7 +99158,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N530_7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -99298,46 +99168,40 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[108]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[104]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N377/gateop;gopMUX4TO1
@@ -99351,33 +99215,43 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[109]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99393,7 +99267,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[15]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99409,24 +99283,36 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[15]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N475_1/gateop;gopMUX4TO1
@@ -99440,20 +99326,14 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm;gopAQ
@@ -99556,26 +99436,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm;gopAQ
-Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99591,17 +99452,24 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_and[1][4]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+F;2
+Q;2
+RSOUT;2
+CE;1
+CLK;1
+I0;1
+I1;1
+I2;1
+I3;1
+RS;1
+S0;1
+S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99633,7 +99501,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[40]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99648,6 +99516,16 @@ L3;1
L4;1
RS;1
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N228_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
Pin
@@ -99666,34 +99544,52 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[203]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1;gopA2Q1
@@ -99903,20 +99799,14 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
@@ -99935,7 +99825,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99951,7 +99841,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99967,7 +99857,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -99983,7 +99873,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -100015,7 +99905,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -100025,17 +99915,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -100051,7 +99947,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -100067,17 +99963,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_382/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[215]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -100109,7 +100011,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cke/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -100142,20 +100044,14 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -100190,20 +100086,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -100254,17 +100144,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[79]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -100280,7 +100176,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[163]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -100295,6 +100191,26 @@ L3;1
L4;1
RS;1
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N151_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv;gopQ
Pin
@@ -100307,7 +100223,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[110]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -100323,7 +100239,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/N18/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -100333,7 +100249,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[138]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -100408,7 +100324,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -100472,20 +100388,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO;gopIOMDDRDEL
@@ -100952,7 +100862,7 @@ MI;1
T;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_41/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -100962,7 +100872,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_53/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -100972,7 +100882,57 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[10]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_75/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_40/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_64/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_83/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_calibration/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -100988,7 +100948,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[40]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -101004,17 +100974,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_45/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[110]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_57/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_95/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101024,17 +101000,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N124_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_49/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101044,7 +101026,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_98/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101054,7 +101036,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_44/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101064,7 +101046,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_101/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_63/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101074,17 +101056,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_81/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_34/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_68/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101094,17 +101082,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[137]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_46/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_65/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101114,7 +101108,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[50]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_56/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_60/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[109]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -101130,7 +101144,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_37/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101140,17 +101154,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N21_2/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[138]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_48/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101160,7 +101180,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_113/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_91/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101170,7 +101190,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_133/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_95/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101180,23 +101200,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[47]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101206,7 +101210,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101216,23 +101220,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[79]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_79/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_71/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101242,23 +101240,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_87/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[208]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -101274,37 +101266,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101314,7 +101276,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[145]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -101330,17 +101292,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N21_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -101350,7 +101302,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -101366,17 +101318,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -101408,23 +101350,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N17_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -101440,24 +101376,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv;gopQ
@@ -102164,7 +102096,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_89/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102305,20 +102237,17 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/s_axi_rdata0[39]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_0/gateop_A2;gopA2
@@ -102361,20 +102290,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102384,7 +102300,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N446_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102394,7 +102310,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N384_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102404,7 +102320,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[131]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[78]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -102420,7 +102336,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102430,7 +102346,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N451_or[0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102440,14 +102356,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[210]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N564_20_3/gateop;gopMUX4TO1
@@ -102483,7 +102405,17 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -102499,7 +102431,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[108]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[22]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -102515,17 +102447,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -102541,7 +102479,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N15_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102551,23 +102489,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102577,23 +102509,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_86/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N637_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102603,17 +102529,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[163]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -102629,7 +102561,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3448/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102766,7 +102698,7 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102883,7 +102815,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -102916,7 +102848,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -102932,7 +102864,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -102948,7 +102880,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N669_42/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -102958,14 +102890,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv;gopQ
@@ -103012,7 +102950,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103028,7 +102966,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -103145,55 +103083,37 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/init_adj_rdel/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N446_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3419/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -103203,7 +103123,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N645_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -103213,7 +103133,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103229,7 +103149,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103256,7 +103176,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103272,14 +103192,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
@@ -103298,7 +103224,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103325,7 +103251,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103341,7 +103267,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -103351,33 +103277,24 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N16_4/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -103665,7 +103582,7 @@ T[3];1
TCLK;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -103675,7 +103592,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[228]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103691,7 +103608,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103707,7 +103624,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103723,17 +103640,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/record_data_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -103743,17 +103666,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[12]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103769,14 +103698,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -103811,7 +103746,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103827,23 +103762,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[240]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_52/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[112]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -103943,20 +103872,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm;gopL5Q
@@ -103975,20 +103898,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv;gopQ
@@ -104090,14 +104007,20 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N328_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -104132,7 +104055,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -104142,33 +104065,33 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[44]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N24_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -104200,30 +104123,30 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/ddr_fifo_full0/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_13[3]/gateop;gopMUX4TO1
@@ -104277,7 +104200,7 @@ S10;1
S11;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -104287,17 +104210,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -104307,7 +104236,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -104317,14 +104246,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[1]/gateop;gopMUX4TO1
@@ -104338,7 +104273,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N306_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -104348,30 +104283,30 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[149]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[127]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_0/gateop_A2;gopA2
@@ -104434,7 +104369,38 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301_1/gateop;gopMUX4TO1
+Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -104450,7 +104416,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301_2/gateop;gopMUX4TO1
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N328_10/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -104461,7 +104427,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N265_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -104471,17 +104437,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[22]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -104497,23 +104469,28 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv;gopQ
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+CE;1
+CLK;1
+D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -104529,38 +104506,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N24_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv;gopQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
RSOUT;2
+Z;2
CE;1
CLK;1
-D;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5
-Pin
-Z;2
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -104576,7 +104554,18 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv;gopQ
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+CE;1
+CLK;1
+D;1
+RS;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[214]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -104608,44 +104597,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv;gopQ
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-CE;1
-CLK;1
-D;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N70_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N20_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -104655,7 +104617,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -104671,23 +104633,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N70_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -104703,31 +104659,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
-F;2
Q;2
RSOUT;2
+Z;2
CE;1
CLK;1
-I0;1
-I1;1
-I2;1
-I3;1
-RS;1
-S0;1
-S1;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[4]/gateop_perm;gopLUT5
-Pin
-Z;2
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm;gopL5Q
@@ -104746,20 +104691,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/N7_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm;gopL5Q
@@ -104778,7 +104717,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -104886,7 +104825,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -104896,23 +104835,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ_perm;gopAQ
+u_axi_ddr_top/u_axi_rd_connect/N32_mux8_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21;gopA2Q2
@@ -104969,43 +104899,68 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5
+Pin
+Z;2
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N124_1/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[143]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_fsm[2:0]_13/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[46]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -105015,7 +104970,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105025,23 +104980,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N124_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N228_11/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105051,7 +105000,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105061,7 +105010,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105071,7 +105020,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N124_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105081,7 +105030,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105091,7 +105040,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[16]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105107,7 +105056,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[204]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105123,17 +105072,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_85/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N265_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105143,7 +105082,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105153,23 +105092,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105185,7 +105118,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -105195,27 +105128,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N232_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105225,7 +105138,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_350/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105235,27 +105148,39 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105265,7 +105190,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_83/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105286,7 +105211,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105296,20 +105221,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5
@@ -105322,7 +105241,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[208]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105338,7 +105257,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105354,14 +105273,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N228_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N475_1/gateop;gopMUX4TO1
@@ -105375,7 +105300,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105491,20 +105416,14 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N228_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -105523,22 +105442,6 @@ RS;1
S0;1
S1;1
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
@@ -105556,7 +105459,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N124_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_381/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105566,7 +105469,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[19]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105599,17 +105518,23 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105625,7 +105550,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105742,22 +105667,19 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm;gopAQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[17]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
-Cout;2
Q;2
RSOUT;2
-Y;2
+Z;2
CE;1
CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
@@ -105842,23 +105764,26 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[113]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105874,7 +105799,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N561[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105884,7 +105809,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[116]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105900,7 +105825,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105916,39 +105841,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -105958,7 +105871,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -105974,7 +105887,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -106006,20 +105919,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q
@@ -106070,20 +105977,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -106103,14 +106004,20 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -106145,14 +106052,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[84]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -106203,7 +106116,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[48]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[23]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -106219,17 +106142,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N151_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[164]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_and[1][4]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -106239,23 +106168,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[236]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_335/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[81]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -106282,7 +106205,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[213]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -106298,36 +106221,24 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[19]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[82]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv;gopQ
@@ -106341,7 +106252,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -106357,7 +106268,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -106373,7 +106284,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -106405,7 +106316,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -106437,7 +106348,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -106453,7 +106364,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[149]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -106933,17 +106844,23 @@ MI;1
T;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_73/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -106963,23 +106880,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[82]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_75/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_79/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -106989,7 +106900,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_67/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -106999,7 +106910,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[111]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107015,53 +106926,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_92/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_91/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/s_axi_rdata0[20]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_83/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[178]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[86]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107077,7 +106952,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_119/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_111/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107087,7 +106962,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[19]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[145]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107103,7 +106978,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/N32_mux8_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107113,7 +106988,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_123/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107123,7 +106998,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107133,7 +107008,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[16]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[180]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107149,7 +107024,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[48]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_50/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[52]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107165,7 +107050,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_138/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_58/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107175,33 +107060,33 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[55]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[46]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_127/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_115/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107211,7 +107096,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/ddr_fifo_full0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[18]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107227,7 +107112,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_77/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_54/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107237,7 +107122,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_67/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_122/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -107247,7 +107132,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[44]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[53]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107263,17 +107168,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_79/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_38/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_91/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107283,7 +107194,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_54/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_62/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107293,7 +107204,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_93/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_70/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107303,7 +107214,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_378/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107313,7 +107224,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[54]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[49]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107329,7 +107240,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N21_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_119/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -107339,7 +107250,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107371,14 +107282,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N18_4/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[83]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -107397,7 +107314,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107413,7 +107330,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107429,7 +107346,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[16]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -107445,30 +107362,30 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N17_7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv;gopQ
@@ -108175,7 +108092,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -108316,7 +108233,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/s_axi_rdata0[34]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[248]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -108372,7 +108289,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3452/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -108382,7 +108299,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -108392,65 +108309,63 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[125]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[102]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3447/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -108493,43 +108408,62 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3458/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[32]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[120]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -108545,7 +108479,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[38]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -108561,7 +108495,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -108577,17 +108511,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_99/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -108597,7 +108537,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3418/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -108607,7 +108547,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[149]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -108623,106 +108563,80 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm;gopAQ
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
-Q;2
+Cout;2
+Q0;2
+Q1;2
RSOUT;2
-Z;2
+Y0;2
+Y1;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm;gopAQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
-Q;2
+Q0;2
+Q1;2
RSOUT;2
-Y;2
+Y0;2
+Y1;2
CE;1
CLK;1
Cin;1
-I0;1
I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/opit_0_inv_A2Q20;gopA2Q2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -108776,36 +108690,24 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_114/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1;gopA2Q1
@@ -108861,7 +108763,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21;gopA2Q2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/opit_0_inv_A2Q20;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -108915,7 +108817,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[112]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -108948,7 +108850,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -108964,7 +108866,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -108980,17 +108882,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -109044,7 +108952,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -109054,7 +108962,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -109170,16 +109078,6 @@ I13;1
I14;1
RS;1
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5
Pin
@@ -109191,43 +109089,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/s_axi_rdata0[37]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3426/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -109237,23 +109099,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[206]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -109269,7 +109125,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -109285,7 +109141,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -109312,7 +109168,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -109360,7 +109216,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -109387,7 +109243,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -109403,40 +109259,46 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[254]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3420/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -109724,7 +109586,7 @@ T[3];1
TCLK;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N151_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -109734,23 +109596,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -109760,7 +109616,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -109770,7 +109626,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -109780,7 +109636,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[216]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -109796,7 +109652,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -109806,23 +109662,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[95]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -109832,24 +109682,36 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_16/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
@@ -109868,7 +109730,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -109884,20 +109746,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[26]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_75/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -109968,7 +109824,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110000,17 +109856,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110141,7 +110003,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110157,23 +110019,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[14]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -110183,26 +110039,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[15]/opit_0_inv_AQ_perm;gopAQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_72/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -110212,7 +110059,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -110244,23 +110091,17 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110327,23 +110168,17 @@ S10;1
S11;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N241_4_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -110363,7 +110198,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -110373,14 +110208,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N294_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[1]/gateop;gopMUX4TO1
@@ -110394,7 +110235,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110410,17 +110251,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[98]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[100]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110496,23 +110343,17 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -110533,14 +110374,20 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N328_10/gateop;gopMUX4TO1
@@ -110554,7 +110401,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110602,14 +110449,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv;gopQ
@@ -110623,7 +110476,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110639,7 +110492,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_64/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110655,7 +110518,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N18_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -110665,34 +110528,34 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv;gopQ
Pin
CEOUT;2
Q;2
RSOUT;2
-Z;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv;gopQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
RSOUT;2
+Z;2
CE;1
CLK;1
-D;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -110702,7 +110565,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110718,14 +110581,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
@@ -110744,17 +110613,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N21_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -110764,17 +110623,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_71/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110806,14 +110671,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm;gopL5Q
@@ -110832,7 +110703,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110930,7 +110801,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -110946,17 +110817,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N570[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N306_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -111039,7 +110916,7 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -111049,20 +110926,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[152]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5
@@ -111075,7 +110946,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[29]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111091,7 +110962,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[30]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111107,18 +110978,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N72/gateop;gopMUX4TO1
-Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N232_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N136_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -111128,7 +110988,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111144,7 +111004,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N232_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -111154,7 +111014,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -111164,7 +111024,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -111174,7 +111034,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N136_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -111184,7 +111044,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[250]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[238]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111200,17 +111060,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[177]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111226,33 +111092,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111268,7 +111134,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -111278,53 +111144,65 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[252]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N279_7/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[222]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[72]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111340,7 +111218,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N475/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -111361,7 +111239,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -111371,7 +111249,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_cal_vld/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111387,7 +111265,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N84_ac1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -111397,7 +111275,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111413,23 +111291,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[121]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N14/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[117]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[203]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111445,20 +111317,15 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[56]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N475_1/gateop;gopMUX4TO1
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q
@@ -111577,30 +111444,31 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[94]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N15_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+F;2
+Q;2
+RSOUT;2
+CE;1
+CLK;1
+I0;1
+I1;1
+I2;1
+I3;1
+RS;1
+S0;1
+S1;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -111635,36 +111503,24 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[61]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -111684,7 +111540,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111700,17 +111556,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N124_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[60]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[114]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111833,14 +111695,23 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm;gopAQ
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21;gopA2Q2
@@ -111924,22 +111795,19 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ;gopAQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
-Cout;2
Q;2
RSOUT;2
-Y;2
+Z;2
CE;1
CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
@@ -111959,7 +111827,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[57]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -111975,23 +111843,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112007,17 +111869,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112033,24 +111901,36 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N14/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N265_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -112069,7 +111949,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112085,7 +111965,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112101,7 +111981,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/reinit_adj_rdel/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112117,17 +111997,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N136_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[215]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112160,7 +112046,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112176,33 +112062,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -112260,7 +112146,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[249]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112276,24 +112162,36 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[80]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv;gopQ
@@ -112307,7 +112205,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[184]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112323,7 +112221,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112339,20 +112237,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[185]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_fsm[2:0]_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv;gopQ
@@ -112366,7 +112258,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112382,7 +112274,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112398,7 +112290,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112430,7 +112322,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112478,7 +112370,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[24]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[240]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -112958,37 +112850,55 @@ MI;1
T;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_54/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_35/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[21]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_42/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[91]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[153]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[26]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -113004,7 +112914,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_38/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_52/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113014,7 +112924,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113024,23 +112934,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_40/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_92/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113050,7 +112954,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_123/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_122/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113060,7 +112964,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_75/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_48/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113070,7 +112974,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_131/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_78/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113080,7 +112984,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_87/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_110/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113090,23 +112994,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[62]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_106/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_98/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_90/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113116,7 +113014,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_79/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113126,7 +113024,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[31]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_102/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_98/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[59]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -113142,27 +113060,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_119/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_135/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_134/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113172,7 +113102,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_111/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113182,17 +113112,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_115/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[61]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_126/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113212,7 +113148,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_103/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_137/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113222,17 +113158,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_138/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113242,27 +113168,39 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_107/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[62]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[93]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[57]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -113278,7 +113216,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_50/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_56/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -113288,23 +113226,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[24]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_97/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[124]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[127]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -113320,27 +113252,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_34/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_99/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[56]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[152]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -113356,7 +113284,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -113372,7 +113300,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -113388,7 +113316,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -113436,17 +113364,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_127/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[169]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -113462,14 +113396,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N21_2/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[117]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv;gopQ
@@ -114176,14 +114116,20 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv;gopQ
@@ -114317,7 +114263,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[211]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[152]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -114373,39 +114319,27 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[144]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N456/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -114415,7 +114349,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_865/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3414/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -114425,7 +114359,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -114441,14 +114375,36 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[57]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[50]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N564_20_3/gateop;gopMUX4TO1
@@ -114494,7 +114450,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -114504,17 +114460,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N669_42/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -114524,7 +114486,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[49]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -114540,23 +114502,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3409/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3419/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -114566,7 +114522,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[178]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -114582,33 +114538,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_5/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N633_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3454/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3417/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -114618,7 +114558,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -114634,14 +114574,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm;gopAQ
@@ -114771,7 +114717,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3413/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -114781,7 +114727,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -114898,7 +114844,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -114947,7 +114893,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -114979,20 +114925,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv;gopQ
@@ -115039,7 +114979,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_113_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -115049,7 +114989,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -115166,33 +115106,33 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[210]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[177]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3457/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -115202,7 +115142,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[54]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115218,17 +115158,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[79]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115244,7 +115190,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115260,7 +115206,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3449/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N67_1_sum3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -115270,37 +115216,52 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3385/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3386/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[125]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N265_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[48]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115316,7 +115277,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[224]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[240]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115332,17 +115293,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[253]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115358,7 +115325,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115385,7 +115352,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115460,7 +115427,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115476,7 +115443,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115492,17 +115459,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[58]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[25]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115803,7 +115776,7 @@ T[3];1
TCLK;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[213]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115819,33 +115792,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[51]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N232_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -115861,7 +115834,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -116798,20 +116771,14 @@ T[3];1
TCLK;1
Inst
-u_axi_ddr_top/s_axi_rdata0[235]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/N1_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[0]/opit_0_inv;gopQ
@@ -119630,7 +119597,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -119646,7 +119613,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -119662,7 +119629,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[104]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -119678,7 +119645,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -119694,17 +119661,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_success/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -119720,7 +119693,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3424/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -119806,20 +119779,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[0]/opit_0_inv;gopQ
@@ -120339,33 +120306,24 @@ D;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N107.lt_2/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N33_mux7/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N172/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N37_1_1/gateop_A2;gopA2
@@ -120488,7 +120446,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/N28/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_36/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -120498,23 +120456,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_11/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N253_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -120524,20 +120476,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N267_or[0]_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N201/gateop;gopMUX4TO1
@@ -120562,7 +120508,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_28/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N267_or[0]_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -120572,7 +120518,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N267_or[0]_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -120582,7 +120528,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N80/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_19/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -120592,33 +120538,33 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N253_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N69_0_ac5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_fsm[2:0]_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -120628,7 +120574,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_28/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -120638,7 +120584,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[17]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[15]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120654,7 +120620,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_valid/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[6]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120670,7 +120646,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -120680,7 +120656,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[19]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[16]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120696,7 +120672,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N282/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -120706,7 +120682,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -120716,7 +120692,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[13]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[17]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120732,7 +120718,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N417_14/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N26_mux3_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -120742,7 +120728,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N262/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -120752,23 +120738,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[26]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[11]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_valid/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120784,23 +120764,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[39]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N414_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120832,7 +120816,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_rotate_image/image_blank_valid/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120848,17 +120832,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_33/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120874,7 +120864,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120890,7 +120880,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120906,7 +120896,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_write/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120922,17 +120912,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg_46/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -120980,7 +120976,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_20/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[14]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -121245,7 +121241,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121261,7 +121257,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121277,7 +121273,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_write/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121293,17 +121289,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10/gateop_perm;gopLUT5
+u_axi_ddr_top/rd_ddr_idle/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121336,7 +121338,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -121413,30 +121415,30 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N33_mux5_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N254/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/N8_4/gateop;gopMUX4TO1
@@ -121472,72 +121474,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/N792_4/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[0]/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ
-Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/ND1[1]_4/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_19/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N417_27/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N317/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -121563,7 +121500,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121579,7 +121516,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121595,7 +121532,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121611,7 +121548,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121627,7 +121564,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121643,7 +121580,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N172/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N20/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -121653,7 +121590,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/ND1[1]_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N80/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -121663,7 +121600,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_cmd_ready/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121711,7 +121648,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121727,7 +121664,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121743,20 +121680,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N33_mux5_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q
@@ -121775,7 +121706,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121791,7 +121722,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121807,14 +121738,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N33_mux7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[10]/opit_0_inv_L5Q_perm;gopL5Q
@@ -121849,7 +121786,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121865,20 +121802,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N109.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_cmd_ready/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121894,7 +121818,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121910,7 +121834,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[15]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121926,7 +121850,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[19]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121942,17 +121866,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N473_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[18]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[18]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[22]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121968,17 +121898,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N62/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[21]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[20]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[25]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -121994,17 +121930,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/N182_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[20]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[21]/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -122052,23 +121994,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[25]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[26]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -122084,7 +122020,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[12]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -122100,7 +122046,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N317/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -122110,7 +122056,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_tworw/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -122126,7 +122072,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N258_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N410/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -122209,30 +122155,30 @@ I3;1
I4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_20/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N491_0/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N371/gateop;gopMUX4TO1
@@ -122246,23 +122192,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[0]/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N417_23/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N417_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -122272,17 +122202,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N416/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N458_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N418/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -122292,7 +122228,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N414_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N417_23/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -122302,27 +122238,39 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N458/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N414_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[39]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -122338,7 +122286,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/ND1[2]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9:0]_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -122348,27 +122296,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N57/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[2]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -122378,20 +122306,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N26_mux3_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[3]/opit_0_inv_L6Q_perm;gopL6Q
@@ -122433,7 +122355,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N418/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N39_mux3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -122475,7 +122397,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -122485,7 +122407,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -122517,7 +122439,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -122533,7 +122455,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N458_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -122543,7 +122465,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -122559,23 +122481,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -122826,32 +122752,35 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[12]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
-Cout;2
Q;2
RSOUT;2
-Y;2
+Z;2
CE;1
CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
@@ -122899,7 +122828,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -123223,7 +123152,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_done/opit_0_inv_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -123239,7 +123168,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -123255,23 +123184,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -123303,7 +123226,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N281/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg_2_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123313,7 +123236,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N270/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N57/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123323,30 +123246,40 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5]/opit_0_inv;gopQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
RSOUT;2
+Z;2
CE;1
CLK;1
-D;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N491_0/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5]/opit_0_inv;gopQ
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+CE;1
+CLK;1
+D;1
RS;1
Inst
@@ -123361,17 +123294,25 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N50_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N136_1_or[0]_1_9_muxf6_perm;gopLUT6
Pin
+Y0;2
+Y1;2
Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+A0;1
+A1;1
+A2;1
+A3;1
+A4;1
+B0;1
+B1;1
+B2;1
+B3;1
+B4;1
+M;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -123398,7 +123339,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N148_1_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123408,14 +123349,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N14_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N216/gateop_perm;gopLUT5
@@ -123428,7 +123375,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N252/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N248/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123438,7 +123385,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N224_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N220_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123448,23 +123395,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N224_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N47/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N59_mux4_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123474,7 +123415,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N276_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123484,7 +123425,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123494,17 +123435,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N31_0_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1205/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123514,17 +123461,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1169/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N0/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N5[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123534,7 +123487,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[38]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -123550,7 +123503,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N248/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N8_mux3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123560,7 +123513,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N208/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244_4_cpy/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123570,7 +123523,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_accepted_m_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_accepted_m_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123602,7 +123555,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N71_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_62/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123612,7 +123565,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N589[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123622,7 +123575,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N8_mux3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N598[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123632,7 +123585,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N607[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123642,7 +123595,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/N35[2]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N616[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123682,59 +123635,59 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N652[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123744,23 +123697,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/N117_mux7_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123770,23 +123717,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N55_mux6_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123858,17 +123799,23 @@ S10;1
S11;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N106_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N50_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123878,7 +123825,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N50_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1202/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123888,23 +123835,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N55_mux6_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N534[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123914,7 +123855,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N50_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1206/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123924,7 +123865,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N50_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123934,23 +123875,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N31_0_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N50_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123960,7 +123895,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N55_mux6_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123980,7 +123915,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N50_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N61_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -123990,23 +123925,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N99_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -124016,17 +123945,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N99_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N91_9[0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -124036,20 +123971,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/N117_mux7_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
@@ -124068,7 +123997,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124084,7 +124013,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124100,7 +124029,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124132,7 +124061,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124148,7 +124077,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124180,7 +124109,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N61_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N589[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -124206,20 +124135,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
@@ -124238,7 +124161,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124254,7 +124177,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -124264,7 +124187,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -124294,17 +124217,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[19]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124320,7 +124249,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N50_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -124330,17 +124259,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_0_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124356,7 +124291,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124388,7 +124323,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124404,7 +124339,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124420,7 +124355,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124468,23 +124403,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N525[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124500,7 +124429,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124516,23 +124445,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124548,7 +124471,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124584,7 +124507,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N99_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N69_mux6_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -124604,23 +124527,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N99_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N607[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -124630,7 +124547,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124662,7 +124579,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124678,7 +124595,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124710,7 +124627,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124726,7 +124643,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124742,7 +124659,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124758,7 +124675,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124774,7 +124691,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124790,7 +124707,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124806,7 +124723,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124822,7 +124739,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124838,7 +124755,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1203/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -124848,7 +124765,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N69_mux6_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -124858,14 +124775,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N61_3/gateop_perm;gopLUT5
@@ -124888,23 +124811,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N99_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N99_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -124914,7 +124831,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124930,7 +124847,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124946,7 +124863,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124962,7 +124879,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -124994,23 +124911,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125026,7 +124937,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125042,7 +124953,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125058,7 +124969,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125074,7 +124985,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125106,7 +125017,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125122,27 +125033,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1202/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N616[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N61_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125152,20 +125075,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N99_2/gateop_perm;gopLUT5
@@ -125178,17 +125095,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N61_3/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125214,17 +125121,36 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_perm;gopA
Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125234,7 +125160,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125250,7 +125176,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125266,7 +125192,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125282,7 +125208,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125298,7 +125224,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125314,7 +125240,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125330,7 +125256,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125362,23 +125288,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N552[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125394,17 +125314,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125420,25 +125330,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N136_1_or[0]_1_9_muxf6_perm;gopLUT6
-Pin
-Y0;2
-Y1;2
-Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
-M;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N50_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125448,7 +125340,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1203/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125458,7 +125350,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125468,7 +125360,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N61_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125478,7 +125370,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N50_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N61_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125488,7 +125380,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/fifo3_data_full/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125504,7 +125396,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125520,7 +125412,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N50_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N99_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125530,7 +125422,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125546,14 +125458,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1204/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -125572,7 +125490,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125588,7 +125506,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125604,7 +125522,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125636,7 +125554,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125652,7 +125570,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125668,7 +125586,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125684,23 +125602,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125716,7 +125628,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N99_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N561[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125726,7 +125638,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N50_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125746,17 +125658,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N61_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N99_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N61_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125766,7 +125684,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N99_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125776,7 +125694,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N534[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125786,7 +125704,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N69_mux6_1/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -125796,7 +125714,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_rotate_image/data_out_valid2/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125828,7 +125746,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125844,17 +125762,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1206/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125870,7 +125794,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125886,7 +125810,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125902,7 +125826,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125918,7 +125842,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125934,20 +125858,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N570[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -125966,7 +125884,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -125982,33 +125900,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N50_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1205/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N55_mux6_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N31_0_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -126018,7 +125936,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -126028,23 +125946,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N99_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -126054,7 +125966,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -126064,27 +125976,39 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N99_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[16]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126100,7 +126024,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N473_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -126110,14 +126034,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -126136,17 +126066,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126162,7 +126098,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126194,23 +126130,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126226,17 +126156,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126252,7 +126188,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126268,14 +126204,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N652[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -126326,7 +126268,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126390,7 +126332,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126406,7 +126348,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126422,7 +126364,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126438,7 +126380,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126454,23 +126396,25 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N136_1_or[0]_1_8_muxf6_perm;gopLUT6
Pin
-CEOUT;2
-Q;2
-RSOUT;2
+Y0;2
+Y1;2
Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+A0;1
+A1;1
+A2;1
+A3;1
+A4;1
+B0;1
+B1;1
+B2;1
+B3;1
+B4;1
+M;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126486,7 +126430,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126502,7 +126446,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126518,20 +126462,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N50_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -126582,17 +126520,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126608,7 +126552,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126624,7 +126568,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126640,17 +126584,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126698,7 +126648,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126762,7 +126712,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126788,20 +126738,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N50_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
@@ -126819,22 +126763,6 @@ L3;1
L4;1
RS;1
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
@@ -126852,7 +126780,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126884,7 +126812,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126910,7 +126838,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126926,20 +126854,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -126958,7 +126880,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -126990,20 +126912,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5
@@ -127016,7 +126932,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127032,23 +126948,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N50_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127096,23 +127006,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N29/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -127122,7 +127026,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N5[1]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -127132,7 +127036,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127164,7 +127068,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127180,17 +127084,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N598[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N525[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N469_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -127200,17 +127110,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/N43_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -127220,25 +127136,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N136_1_or[0]_1_8_muxf6_perm;gopLUT6
-Pin
-Y0;2
-Y1;2
-Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
-M;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127254,7 +127152,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127270,7 +127168,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127286,43 +127184,49 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -127332,17 +127236,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1201/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127357,6 +127267,16 @@ L3;1
L4;1
RS;1
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
@@ -127374,7 +127294,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N552[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N50_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -127394,7 +127314,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N471_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -127404,20 +127324,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -127468,7 +127382,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127494,17 +127408,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/axi_data_valid0/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127520,7 +127440,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127536,20 +127456,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
@@ -127568,7 +127482,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127594,23 +127508,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N31_0_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127626,7 +127534,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127642,7 +127550,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127674,7 +127582,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127690,33 +127598,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N31_0_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -127726,27 +127634,39 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N31_0_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127762,7 +127682,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127778,7 +127698,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127794,7 +127714,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127826,7 +127746,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127842,7 +127762,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N25_mux6_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -127852,17 +127772,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N25_mux6_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N50/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -127872,7 +127798,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127888,7 +127814,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127904,7 +127830,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127920,7 +127846,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127936,7 +127862,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -127952,20 +127878,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
@@ -127978,7 +127898,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N31_0_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -127988,7 +127908,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128004,7 +127924,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N240_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N50_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -128030,7 +127960,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128062,7 +127992,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128078,7 +128008,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -128088,7 +128018,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N25_mux6_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N579[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -128098,7 +128028,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -128108,7 +128038,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1204/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -128118,7 +128048,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128134,7 +128064,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128150,20 +128080,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
@@ -128182,7 +128106,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128198,17 +128122,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N31_0_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -128218,7 +128132,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N31_0_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -128228,7 +128142,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -128254,7 +128168,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128302,7 +128216,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128318,7 +128232,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -128328,20 +128242,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[12]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
@@ -128354,23 +128262,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[11]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128386,7 +128288,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128402,17 +128304,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N25_mux6_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128428,7 +128336,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128444,23 +128352,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N13_mux3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N31_0_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -128470,17 +128372,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N31_0_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[19]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[18]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128496,7 +128404,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128528,7 +128436,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -128576,14 +128484,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/N27_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[17]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[1]/opit_0_inv;gopQ
@@ -129068,23 +128982,17 @@ S10;1
S11;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_accepted_m_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_accepted_m_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_47_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -129105,7 +129013,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129121,14 +129029,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N197/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_m/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/N106/gateop_perm;gopLUT5
@@ -129151,17 +129065,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N27_mux2/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N55_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N52_mux5_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -129188,7 +129092,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_l/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129221,7 +129125,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129237,7 +129141,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129253,7 +129157,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129269,7 +129173,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129285,23 +129189,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_m/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N14_mux2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129317,20 +129215,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[0]/opit_0_inv;gopQ
@@ -129729,7 +129621,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129745,7 +129637,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129761,7 +129653,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[40]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129777,7 +129669,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[18]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[38]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129793,7 +129685,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129809,7 +129701,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[20]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129825,7 +129717,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[20]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129841,23 +129733,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129873,7 +129759,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[24]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129889,7 +129775,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[19]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129905,7 +129791,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[19]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129921,7 +129807,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[35]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[30]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129937,7 +129823,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[27]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[18]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129953,7 +129839,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[30]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129969,7 +129855,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[33]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -129985,23 +129871,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[25]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N210/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[27]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130033,7 +129913,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[21]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[23]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130065,7 +129945,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[19]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[26]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130081,7 +129961,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[36]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[29]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130097,7 +129977,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[29]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[25]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130113,7 +129993,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[26]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130129,17 +130009,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N531_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[15]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[29]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130155,7 +130041,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[30]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130171,7 +130057,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[31]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130187,7 +130073,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[15]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130219,7 +130105,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[35]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130235,7 +130121,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[34]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130251,23 +130137,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N149_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[36]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130283,7 +130163,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[31]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130299,7 +130179,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[42]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[39]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130315,7 +130195,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[40]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130331,7 +130211,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[41]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_valid/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130347,7 +130227,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_valid/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[42]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130363,7 +130243,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N10/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130373,7 +130253,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N220_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N208/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130383,7 +130263,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130393,23 +130273,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N516[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130419,24 +130293,36 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N543[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -130487,7 +130373,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N124_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/N43_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130507,7 +130393,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130587,7 +130473,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/N35[2]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130597,30 +130483,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N13_mux6_2/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
@@ -130687,7 +130570,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[15:0]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130713,7 +130596,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd3_addr_ctr/N34_mux3_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130723,23 +130606,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_sum3_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_0_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130749,7 +130629,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N45_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130809,27 +130689,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_47_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_0_8/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -130845,33 +130705,36 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[39]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/N1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_50[3]_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[7]/opit_0_inv_AQ_perm;gopAQ
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N45_mux6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_51/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130903,7 +130766,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244_4_cpy/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_50[3]_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130913,7 +130776,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -130923,30 +130786,50 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_54/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_63/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_0_10/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
@@ -130981,23 +130864,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/N27_mux6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N7_mux6_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N225_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131056,7 +130933,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N221/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_sum3_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131066,7 +130943,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N59_mux4_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N27_mux2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131076,7 +130953,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd3_data_en0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131092,36 +130969,34 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[32]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N7_mux6_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N276_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N220_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[1]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -131141,7 +131016,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2]/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131157,7 +131032,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131173,30 +131048,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q
@@ -131215,7 +131099,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131231,7 +131115,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131279,7 +131163,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N221/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131289,7 +131173,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N13_mux3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N15/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131299,14 +131183,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N22/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N27_mux6/gateop_perm;gopLUT5
@@ -131319,7 +131209,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N27_mux3_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N35_mux4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131329,7 +131219,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N35_mux4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N50_12_maj1_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131339,20 +131229,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N29/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N50_10[3]/gateop_perm;gopLUT5
@@ -131365,7 +131249,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N15/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N50_15[3]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131391,17 +131275,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N50_12_maj1_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131417,7 +131291,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131433,7 +131307,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N220_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N13_mux6_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131443,23 +131317,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131475,7 +131343,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131491,7 +131359,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131507,7 +131375,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131523,7 +131391,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N50_15[0]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N27_mux3_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131533,7 +131401,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N212/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131543,17 +131411,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N98/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/N27_mux6_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N106_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -131563,14 +131437,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N210/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/cmd_wr_pass/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -131606,17 +131486,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N50/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -131632,23 +131518,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -132396,7 +132276,7 @@ WD;1
WE;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -132416,7 +132296,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N26_mux3_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -132426,17 +132306,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N42/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -132446,7 +132332,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -132456,17 +132342,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[24]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -132502,7 +132394,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -132578,7 +132470,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -132668,19 +132560,22 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
@@ -132774,17 +132669,23 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -132800,20 +132701,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -133637,7 +133532,7 @@ WD;1
WE;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -133647,23 +133542,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N4_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -133673,14 +133562,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N26_mux3_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[1]/gateop_perm;gopLUT5
@@ -133693,7 +133591,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -133703,7 +133601,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N4_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -133713,7 +133611,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/rd3_data_en0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -133749,14 +133647,20 @@ I13;1
I14;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N24_1.fsub_1/gateop_A2;gopA2
@@ -133819,20 +133723,17 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/poll/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N30.fsub_1/gateop_A2;gopA2
@@ -133915,22 +133816,19 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
-Cout;2
Q;2
RSOUT;2
-Y;2
+Z;2
CE;1
CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
@@ -134024,34 +133922,52 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -134127,7 +134043,7 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N25_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -134137,20 +134053,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N30_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[2]/opit_0_inv_L5Q_perm;gopL5Q
@@ -134169,33 +134079,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N10_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[41]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N10_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[10]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N42/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -134205,20 +134115,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[26]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N46_1_1/gateop_A2;gopA2
@@ -134281,7 +134185,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N458/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -134291,7 +134195,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[1]/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -134301,7 +134205,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[2]/gateop;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -134311,7 +134215,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[3]/gateop;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -134321,7 +134225,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -134331,17 +134235,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -134351,39 +134261,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[22]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[62]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N274/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -134393,7 +134291,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -134403,17 +134301,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -134429,43 +134333,49 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[13]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/ctrl_back_rdy/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[20]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_b_valid/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -134481,23 +134391,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[17]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N197/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_b_valid/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -134530,14 +134434,20 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N30_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/poll/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[1]/opit_0_inv;gopQ
@@ -135442,7 +135352,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135458,7 +135368,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135485,7 +135395,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[39]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135501,7 +135411,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135517,7 +135427,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[38]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[40]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135533,7 +135443,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[18]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[33]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135549,7 +135459,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[21]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[21]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135565,7 +135475,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[25]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135581,7 +135491,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[19]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135597,7 +135507,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[15]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135613,7 +135523,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135629,7 +135539,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135645,7 +135555,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135661,7 +135571,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[22]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135677,7 +135587,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[16]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135709,7 +135619,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[30]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[16]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135725,7 +135635,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[17]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135741,7 +135651,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[26]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135757,7 +135667,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[20]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135773,7 +135683,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[31]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[23]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135789,7 +135699,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[42]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[21]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135805,7 +135715,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[28]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[32]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135821,7 +135731,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[33]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[24]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135837,7 +135747,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[24]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[26]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135853,7 +135763,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[36]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[25]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135869,7 +135779,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[29]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135885,7 +135795,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[29]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135901,7 +135811,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[22]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[28]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135917,7 +135827,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[30]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135933,7 +135843,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[32]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135949,7 +135859,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[31]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[18]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135965,23 +135875,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[40]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N524_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -135997,7 +135901,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[38]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136029,7 +135933,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[36]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136045,23 +135949,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[23]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2070_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[39]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_valid/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136093,23 +135991,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[42]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136125,7 +136017,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_valid/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136141,7 +136033,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -136151,7 +136043,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N526_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136167,17 +136069,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1792_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N232_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N545_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -136187,7 +136095,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136203,7 +136111,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136219,7 +136127,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136235,7 +136143,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136251,7 +136159,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136267,7 +136175,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136283,7 +136191,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136299,7 +136207,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136315,7 +136223,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136331,7 +136239,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[194]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136347,7 +136255,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[33]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136363,7 +136271,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136379,7 +136287,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136395,7 +136303,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136411,7 +136319,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136427,7 +136335,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[24]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136443,7 +136351,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136459,7 +136367,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136475,7 +136383,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[15]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[34]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136491,7 +136399,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136507,7 +136415,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[15:0]_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[21]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136523,7 +136441,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136539,7 +136457,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[17]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[15:0]_1161/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136555,7 +136483,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136571,7 +136499,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136587,17 +136515,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N100_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136613,17 +136547,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N530_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136639,7 +136579,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136655,7 +136595,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1025_1_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N544_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -136665,7 +136605,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[34]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136681,7 +136621,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136697,7 +136637,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wvld[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136713,7 +136653,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_l/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N100_6/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136729,7 +136679,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_l/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136745,27 +136695,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2193_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2048_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136781,17 +136743,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N148_1_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_m/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136807,7 +136775,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136823,17 +136791,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N544_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136849,7 +136823,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136865,7 +136839,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136881,17 +136855,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N238_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136907,7 +136887,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136939,7 +136919,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136955,7 +136935,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136971,7 +136951,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -136987,7 +136967,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rvld/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137003,7 +136983,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rvld/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137019,23 +136999,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N291_17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N171_7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137045,7 +137019,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N285/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N171_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137055,55 +137029,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_m/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N532_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N531_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N549_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2051/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137113,39 +137059,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1792_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2053/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2070_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1796/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137155,7 +137089,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2051/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N547_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137165,7 +137099,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2053/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N749/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137175,7 +137109,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137191,17 +137125,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N545_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1025_1_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N549_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137211,7 +137135,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N93_mux8_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N771_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137221,7 +137145,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137237,47 +137161,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2207_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/N129/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N771_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N749/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N761_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137287,17 +137203,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N761_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N547_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2207_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137307,17 +137229,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1286_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[17]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137333,17 +137261,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N544_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137353,7 +137287,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[22]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137369,23 +137303,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1796/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2193_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137395,7 +137323,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137421,17 +137349,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N532_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N149_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N530_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137441,7 +137375,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N754/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N238_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137451,23 +137385,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N754/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137483,7 +137411,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137499,7 +137427,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137515,7 +137443,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137531,7 +137459,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137547,7 +137475,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137563,7 +137491,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137595,7 +137523,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N526_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137605,7 +137533,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[31]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137621,39 +137549,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[15:0]_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137685,7 +137601,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137701,7 +137617,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[16]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[19]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137717,7 +137633,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[18]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[23]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137733,7 +137649,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[18]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137749,7 +137665,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[24]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[26]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137781,7 +137697,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[21]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[24]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137797,7 +137713,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[23]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[22]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137813,7 +137729,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[26]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137829,7 +137745,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137845,7 +137761,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137878,7 +137794,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1025_1_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -137920,7 +137836,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -137968,23 +137884,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -138000,7 +137910,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -138016,7 +137926,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -138032,7 +137942,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -138048,7 +137958,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -138081,7 +137991,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -138097,7 +138007,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -138113,30 +138023,30 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N167_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[0]/opit_0_inv;gopQ
@@ -138557,23 +138467,17 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N297_mux4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -138661,7 +138565,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -138670,25 +138574,6 @@ L2;1
L3;1
L4;1
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[7]/opit_0_inv_AQ_perm;gopAQ
-Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
-
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q
Pin
@@ -138705,6 +138590,19 @@ L3;1
L4;1
RS;1
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp;gopRAM16X1D
Pin
@@ -138777,6 +138675,16 @@ WCLK;1
WD;1
WE;1
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[1]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[2]/gateop_perm;gopLUT5
Pin
@@ -138798,7 +138706,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -138808,7 +138716,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_2/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[5]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -138821,23 +138739,7 @@ I3;1
I4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[10]/opit_0_inv_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -138847,7 +138749,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -138857,7 +138759,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -138873,39 +138775,47 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_txpr_pass/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/fifo_vld/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_0/gateop_A2;gopA2
+Pin
+Cout;2
+Y0;2
+Y1;2
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_0/gateop_A2;gopA2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop_A2;gopA2
Pin
Cout;2
Y0;2
@@ -138925,7 +138835,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -138935,11 +138845,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop_A2;gopA2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_13/gateop_perm;gopLUT5
Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21;gopA2Q2
+Pin
+CEOUT;2
Cout;2
+Q0;2
+Q1;2
+RSOUT;2
Y0;2
Y1;2
+CE;1
+CLK;1
Cin;1
I0X;1
I1X;1
@@ -138953,22 +138879,75 @@ I11;1
I12;1
I13;1
I14;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_2/gateop;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21;gopA2Q2
Pin
+CEOUT;2
Cout;2
-Y;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
Cin;1
-I0;1
I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[5]/opit_0_inv_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv;gopQ
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+CE;1
+CLK;1
+D;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -138984,119 +138963,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[5]/opit_0_inv_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv;gopQ
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-CE;1
-CLK;1
-D;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[3]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[5]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21;gopA2Q2
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -139221,33 +139098,33 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_arid[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_24/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N63/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N228/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139268,7 +139145,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N228/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139278,7 +139155,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_27/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N266/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139288,7 +139165,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_32/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N278/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139418,7 +139295,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -139444,7 +139321,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N147/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N282/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139454,7 +139331,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N266/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139464,23 +139341,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N270/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N278/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N274/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139490,23 +139361,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N69_0_ac5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_36/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139516,14 +139381,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/ND1[1]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/column_addr_end_1_2/gateop_A2;gopA2
@@ -139586,20 +139457,14 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N14/gateop_perm;gopLUT5
@@ -139612,17 +139477,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N261_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_12/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3:0]_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139632,7 +139503,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N256_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_16/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139642,7 +139513,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -139658,27 +139529,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3:0]_4/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_19/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/rd1_cnt_num[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[15]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -139694,23 +139561,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/N866_2_or[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_28/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_20/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139720,7 +139581,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[15]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[19]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -139736,7 +139597,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_24/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_22/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139746,7 +139607,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N244/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_25/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139756,23 +139617,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_araddr[18]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_27/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37:0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139782,33 +139637,33 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[16]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_29/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_29/gateop_perm;gopLUT5
+u_axi_ddr_top/N412_mux15_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139818,7 +139673,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -139834,17 +139689,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_34/gateop_perm;gopLUT5
+u_axi_ddr_top/rd1_ddr_done0/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139854,23 +139715,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_32/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139880,33 +139735,33 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[31]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/record_araddr_valid/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N147/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[24]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -139922,7 +139777,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -139938,7 +139793,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[5]/opit_0_inv_L5Q;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[23]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -139970,7 +139825,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_valid_0/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -139980,7 +139835,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140012,7 +139867,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140028,17 +139883,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/N400_mux15_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[27]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140054,7 +139915,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[20]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[13]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140070,7 +139931,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[16]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140086,43 +139947,49 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[18]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_34/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N84_ac1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[16]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/N412_mux15_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[25]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[19]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[30]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140154,7 +140021,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[29]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[20]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140170,17 +140037,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_21/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_araddr[13]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[23]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[32]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140212,7 +140085,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[31]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[27]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140228,7 +140101,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[28]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[26]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140244,7 +140117,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[35]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[34]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140260,7 +140133,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[32]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[29]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140276,7 +140149,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[30]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[28]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140292,7 +140165,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_28/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_araddr[17]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140308,7 +140191,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[34]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[31]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140324,14 +140207,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N69_0_ac4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[35]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[33]/opit_0_inv_L5Q_perm;gopL5Q
@@ -140350,7 +140239,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_21/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -140360,7 +140249,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140376,14 +140265,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[12]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[37]/opit_0_inv;gopQ
@@ -140397,7 +140292,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140413,7 +140308,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[23]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140429,7 +140324,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140445,17 +140340,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[9]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140471,7 +140372,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140487,7 +140388,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140503,23 +140404,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_arid[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140535,7 +140430,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[27]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[15]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140551,7 +140446,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[20]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140567,7 +140462,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[16]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140583,7 +140478,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[18]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140599,7 +140494,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[21]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140615,14 +140510,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_17/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[30]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[19]/opit_0_inv_L5Q_perm;gopL5Q
@@ -140641,7 +140542,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[25]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[20]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140657,7 +140558,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[29]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[33]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140673,7 +140574,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[23]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[22]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140689,7 +140590,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[30]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[26]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140705,7 +140606,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[26]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[27]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140721,7 +140622,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[31]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[25]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140737,30 +140638,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_13/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[29]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N24.eq_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[28]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[24]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140776,7 +140670,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[33]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[28]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140792,23 +140686,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[32]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[34]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140824,23 +140712,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[35]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[34]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[32]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140856,7 +140738,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[35]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140872,7 +140754,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[12]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -140888,7 +140770,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_26/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -140898,17 +140780,33 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N412_mux15_7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[18]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N19_3/gateop_perm;gopLUT5
+u_axi_ddr_top/N440/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/N589/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -141016,20 +140914,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N63/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][0]/opit_0_inv;gopQ
@@ -142352,7 +142244,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -142368,7 +142260,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[5]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -142384,23 +142276,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -142432,14 +142318,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[14]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[7]/opit_0_inv_L5Q_perm;gopL5Q
@@ -142458,7 +142350,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[19]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -142743,46 +142635,33 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[4]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[27]/opit_0_inv_AQ;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[1]/opit_0_inv_L5Q_perm;gopL5Q
@@ -142801,17 +142680,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -142827,23 +142696,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/N296_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[14]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -142859,7 +142722,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[1]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
Pin
CEOUT;2
F;2
@@ -142876,7 +142739,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[2]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[1]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
Pin
CEOUT;2
F;2
@@ -142893,7 +142756,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -142908,6 +142771,16 @@ L3;1
L4;1
RS;1
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N10/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
Pin
@@ -142926,7 +142799,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -142942,23 +142815,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/fifo0_data_full/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N867/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -142968,23 +142835,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[5]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N262/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N62/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -142994,7 +142855,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/ND1[1]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N69_0_ac4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -143004,36 +142865,34 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N281/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_tworw/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_18/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N335_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[0]/opit_0_inv;gopQ
@@ -143443,14 +143302,20 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_18/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[40]/opit_0_inv_MUX8TO1Q;gopMUX8TO1Q
@@ -144412,17 +144277,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N416/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -144432,7 +144303,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -144464,20 +144335,14 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wvld[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram16x1d;gopRAM16X1D
@@ -144516,7 +144381,7 @@ WD;1
WE;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N55_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -144526,7 +144391,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N225_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -144536,7 +144401,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/N6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -144546,7 +144411,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N240_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N25_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -144566,7 +144431,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -144576,7 +144441,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -144592,14 +144457,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/N7_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop_A2;gopA2
@@ -144705,23 +144576,17 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N25_mux6_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -144731,7 +144596,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -144825,17 +144690,23 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/ctrl_back_rdy/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[193]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[194]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -144851,7 +144722,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[197]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[192]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -144867,7 +144738,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[130]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[195]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -144883,7 +144754,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[65]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[131]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -144899,7 +144770,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[66]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[197]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -144915,7 +144786,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[135]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[132]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -144931,23 +144802,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[70]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[67]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[130]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -144963,7 +144828,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[204]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[202]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -144979,7 +144844,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[203]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[204]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -144995,7 +144860,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[76]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[74]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145011,7 +144876,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[77]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[207]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145027,7 +144892,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[72]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[137]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145043,7 +144908,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[75]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[141]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145059,7 +144924,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[78]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[75]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145075,7 +144940,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[79]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[139]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145091,7 +144956,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[84]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[211]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145123,23 +144988,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[212]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3386/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[213]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[144]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145155,7 +145014,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[145]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[82]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145171,7 +145030,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[83]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[20]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145203,7 +145062,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[210]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[85]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145235,7 +145094,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[218]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[93]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145251,7 +145110,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[222]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[221]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145283,7 +145142,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[155]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[223]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145315,7 +145174,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[92]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[156]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145331,7 +145190,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[89]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[155]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145347,7 +145206,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[160]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[226]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145363,7 +145222,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[229]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[103]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145379,7 +145238,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[96]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[98]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145395,7 +145254,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[97]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[102]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145427,7 +145286,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[161]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[160]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145491,7 +145350,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[235]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[169]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145523,7 +145382,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[237]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[171]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145539,7 +145398,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[238]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[172]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145555,7 +145414,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[173]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145571,7 +145430,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[172]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[175]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145587,7 +145446,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[109]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[107]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145603,7 +145462,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[241]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[179]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145619,7 +145478,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[247]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[242]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145635,7 +145494,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[244]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[243]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145651,7 +145510,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[245]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[176]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145667,7 +145526,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[246]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[245]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145683,7 +145542,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[179]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[246]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145715,7 +145574,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[181]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[250]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145731,7 +145590,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[120]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[252]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145747,7 +145606,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[254]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[249]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145763,7 +145622,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[122]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[117]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145779,7 +145638,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[253]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[255]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145795,7 +145654,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[186]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[184]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145811,7 +145670,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[187]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[254]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -145827,7 +145686,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[255]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[187]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -147289,7 +147148,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[104]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -147316,7 +147175,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[24]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -147332,7 +147191,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -148046,7 +147905,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[71]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[65]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148062,7 +147921,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[131]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[198]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148078,7 +147937,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[194]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[68]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148110,7 +147969,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[192]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[194]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148126,7 +147985,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[196]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[70]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148142,7 +148001,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[134]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[71]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148158,7 +148017,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[99]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[67]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148174,7 +148033,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[140]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[76]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148190,7 +148049,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[136]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[77]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148222,7 +148081,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[142]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[203]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148238,7 +148097,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[137]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[200]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148254,7 +148113,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[201]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[143]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148270,7 +148129,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[206]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[142]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148286,7 +148145,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[143]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[207]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148302,7 +148161,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[208]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[83]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148318,7 +148177,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[82]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[145]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148334,7 +148193,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[215]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[148]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148350,7 +148209,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[149]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[208]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148366,7 +148225,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[148]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[87]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148382,7 +148241,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[87]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[151]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148414,7 +148273,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[149]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[212]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148446,7 +148305,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[216]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[91]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148462,7 +148321,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[91]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[92]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148478,7 +148337,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[218]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[152]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148494,7 +148353,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[93]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[220]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148510,23 +148369,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[158]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[152]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_en/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148542,7 +148395,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[153]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148558,7 +148411,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[98]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[224]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148574,7 +148427,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[163]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[99]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148590,7 +148443,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[162]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[226]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148622,7 +148475,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[164]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[162]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148638,7 +148491,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[102]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[227]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148654,7 +148507,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[230]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[165]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148670,7 +148523,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[227]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[161]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148686,7 +148539,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[168]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[173]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148702,7 +148555,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[107]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[111]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148734,7 +148587,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[233]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[108]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148750,7 +148603,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[105]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[235]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148766,7 +148619,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[237]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[110]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148782,7 +148635,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[111]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[237]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148798,7 +148651,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[175]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[233]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148814,7 +148667,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[116]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[114]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148830,7 +148683,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[242]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[115]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148846,7 +148699,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[115]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148862,7 +148715,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[241]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148878,7 +148731,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[240]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[183]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148894,7 +148747,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[243]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[188]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148926,7 +148779,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[124]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148942,7 +148795,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[125]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148958,7 +148811,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[190]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[123]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -148974,7 +148827,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[188]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[186]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149006,7 +148859,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[184]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[118]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149022,7 +148875,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[253]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[126]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149038,7 +148891,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[249]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[189]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149054,7 +148907,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[191]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[248]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149086,7 +148939,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[133]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[134]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149102,7 +148955,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N382_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -149112,7 +148965,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[193]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[199]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149128,7 +148981,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[64]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[133]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149144,7 +148997,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[7]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[230]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149160,7 +149013,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[198]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N25.eq_4/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[196]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149176,17 +149042,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[15:0]_3/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[141]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[72]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149202,7 +149058,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[139]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[140]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149218,7 +149074,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[202]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[201]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149234,7 +149090,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[205]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[14]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149250,17 +149106,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[206]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[200]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[201]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149276,23 +149138,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[203]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_91/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[207]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149324,7 +149180,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[146]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[209]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149340,7 +149196,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[22]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[149]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149356,7 +149212,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[151]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[148]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149372,7 +149228,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[212]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[210]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149388,20 +149244,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[84]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[214]/opit_0_inv_L5Q_perm;gopL5Q
@@ -149420,7 +149270,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[208]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[213]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149436,7 +149286,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[153]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[34]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149452,7 +149302,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[223]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[222]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149484,7 +149334,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[156]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N258_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[158]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149500,7 +149360,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[221]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[216]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149532,7 +149392,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[220]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[219]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149548,17 +149408,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[225]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[224]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[231]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149574,7 +149440,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[165]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[228]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149590,7 +149456,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[64]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[33]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149606,7 +149472,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[225]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[234]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149622,7 +149488,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[228]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[230]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149638,7 +149504,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[226]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[167]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149654,7 +149520,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[167]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[227]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149670,7 +149536,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[224]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149686,7 +149552,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[169]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[236]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149702,7 +149568,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[232]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[234]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149718,7 +149584,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[234]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[174]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149734,7 +149600,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[173]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[239]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149750,7 +149616,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[236]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[43]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149766,17 +149632,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_21/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[232]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[110]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[235]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149792,23 +149664,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[238]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[177]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[178]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149824,7 +149690,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[241]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[28]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149840,7 +149706,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[182]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[181]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149856,7 +149722,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[183]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[122]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149872,7 +149738,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[243]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[182]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149888,7 +149754,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[59]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[30]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149904,7 +149770,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[242]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[244]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149920,17 +149786,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[11]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[115]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[248]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[191]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149946,27 +149818,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[250]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[190]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[189]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[113]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149982,7 +149866,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[250]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[249]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -149998,7 +149882,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[126]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[251]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150014,7 +149898,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[255]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[193]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150030,7 +149924,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[254]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[197]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150062,7 +149956,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[196]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[68]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150078,7 +149972,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[197]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150094,23 +149988,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[199]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[69]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[199]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150126,7 +150014,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[66]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150142,7 +150030,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[199]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[202]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150158,14 +150046,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[205]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[205]/opit_0_inv_L5Q_perm;gopL5Q
@@ -150184,7 +150078,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[207]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[206]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150200,7 +150094,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[204]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[73]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150216,20 +150110,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N538/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -150239,52 +150120,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[201]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[209]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[211]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150300,23 +150156,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[211]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[214]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150332,7 +150182,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[213]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[209]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150348,7 +150198,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[215]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[215]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150364,7 +150214,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[214]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/init_adj_rdel/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150380,7 +150230,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[50]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150396,7 +150246,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -150406,7 +150256,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[219]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[218]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150422,7 +150272,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N61_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -150432,7 +150282,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[217]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[222]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150447,16 +150297,6 @@ L3;1
L4;1
RS;1
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N579[7]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[221]/opit_0_inv_L5Q_perm;gopL5Q
Pin
@@ -150474,7 +150314,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[88]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[216]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150490,27 +150330,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N516[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[226]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[223]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150526,7 +150359,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[32]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[219]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150542,7 +150375,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[224]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150574,7 +150407,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[32]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[228]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150590,7 +150423,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[231]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[15:0]_418_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N265_11/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[224]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150606,7 +150459,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[103]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[225]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150622,17 +150475,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[15:0]_1278/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[224]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[239]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[105]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150648,7 +150507,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[235]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[239]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150664,7 +150523,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[236]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[232]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150680,17 +150539,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[105]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[232]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[109]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150706,7 +150571,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[239]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[238]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150722,7 +150587,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[43]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[41]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150738,7 +150603,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[41]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150754,7 +150619,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[244]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[242]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150770,7 +150635,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[245]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[243]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150802,17 +150667,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[244]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[176]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[245]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150828,14 +150699,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[240]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[247]/opit_0_inv_L5Q_perm;gopL5Q
@@ -150854,7 +150731,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[62]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[112]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150870,7 +150747,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[252]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[51]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150902,17 +150779,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_9/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[252]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[248]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[255]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150928,7 +150811,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[92]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[94]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150944,7 +150827,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[124]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[254]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150960,17 +150843,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[10]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[121]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[120]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[177]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -150997,7 +150886,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cas_n/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[237]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -151370,14 +151259,20 @@ RST;1
RSTODIV;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/axi_fifo_full0/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/N104.lt_0/gateop_A2;gopA2
@@ -151433,23 +151328,17 @@ I3;1
I4;1
Inst
-u_axi_ddr_top/record_data_valid/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N373_1_or[0][2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[4]/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/rd_ddr_addr_valid1/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -151465,23 +151354,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/cnt_wr_num[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N297_mux4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/wr_sta_fsm[3:0]_3/gateop_perm;gopLUT5
+u_axi_ddr_top/N792_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151491,17 +151374,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_16/gateop_perm;gopLUT5
+u_axi_ddr_top/rd_importance/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -151517,7 +151406,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/fifo1_data_full/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -151533,7 +151422,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151543,7 +151432,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N18/gateop_perm;gopLUT5
+u_axi_ddr_top/N878/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151553,7 +151442,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N412_mux15_10/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_or[13]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151563,17 +151452,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N867/gateop_perm;gopLUT5
+u_axi_ddr_top/record_addr_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/N866_2_or[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_or[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151583,7 +151478,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_or[13]/gateop_perm;gopLUT5
+u_axi_ddr_top/N412_mux15_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151593,23 +151488,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/rd0_ddr_done0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N866_2_or[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N448_6/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N18/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151619,7 +151508,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N132/gateop_perm;gopLUT5
+u_axi_ddr_top/N855_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151639,7 +151528,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N928_8/gateop_perm;gopLUT5
+u_axi_ddr_top/N928_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151649,7 +151538,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/delay_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/delay_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -151665,7 +151554,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/rd1_ddr_done0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -151681,20 +151570,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/N866_2_and[26][0]_1/gateop_perm;gopLUT5
@@ -151707,7 +151590,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_or[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_and[28][0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151717,7 +151600,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_and[27][0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/rd0_done_cnt[2:0]_e/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151727,7 +151610,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_and[28][0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_or[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151737,7 +151620,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_and[30][0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_and[31][0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151747,7 +151630,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_and[35][0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_and[32][0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151757,14 +151640,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_and[31][0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/rd0_done_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/N866_2_and[33][0]_1/gateop_perm;gopLUT5
@@ -151777,7 +151666,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_and[29][0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_or[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151787,7 +151676,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_or[11]/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_and[36][0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151797,23 +151686,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/rd1_done_cnt[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N866_2_and[35][0]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/N866_2_and[36][0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N574_9[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151823,17 +151706,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_and[37][0]_1/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/N866_2_and[34][0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_or[15]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151843,39 +151732,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr/opit_0_inv_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd0_addr_ctr/N20_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N866_2_or[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/rd0_done_cnt[2:0]_e/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_or[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151885,23 +151762,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/rd0_done_cnt[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N866_2_or[14]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/N882/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_or[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151911,7 +151782,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N871/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_or[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151921,17 +151792,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_or[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/rd0_cnt_num[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/rd0_addr_start_fall/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd1_cnt_num[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -151957,7 +151834,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd0_ddr_done0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -151973,7 +151850,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/N866_2_or[14]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N249_13/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -151983,55 +151860,37 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA
+u_axi_ddr_top/N866_2_or[12]/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[27]/opit_0_AQ_perm;gopAQ
+u_axi_ddr_top/N871/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_axi_ddr_top/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N866_2_and[37][0]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/N866_2_or[15]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N574_3_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -152041,20 +151900,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/record_addr_valid/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N889/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/N866_6_0/gateop_A2;gopA2
@@ -152277,7 +152130,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/N889/gateop_perm;gopLUT5
+u_axi_ddr_top/N863_0_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -152287,7 +152140,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_or[10]/gateop_perm;gopLUT5
+u_axi_ddr_top/N882/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -152297,7 +152150,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N574_9[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -152307,23 +152160,17 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done_rise/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/N264_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/N863_0_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N264_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -152343,7 +152190,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd0_time_permit/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -152359,49 +152206,43 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N866_2_and[29][0]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_rotate_image/rd_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N928_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/N928_10/gateop_perm;gopLUT5
+u_axi_ddr_top/rd1_time_permit/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/rd1_time_permit/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done_rise/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -152559,7 +152400,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N264_8/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_and[27][0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -152695,7 +152536,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_and[24][0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -152737,7 +152578,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/delay_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -152753,7 +152604,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/delay_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/delay_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -152769,7 +152620,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/delay_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/delay_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -152785,20 +152636,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N161.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/delay_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/delay_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -152814,7 +152652,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N188_40/gateop_perm;gopLUT5
+u_axi_ddr_top/N296_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -152824,14 +152662,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_or[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/rx3_addr_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/rd0_addr_start_valid0/opit_0;gopQ
@@ -152856,7 +152700,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/N400_mux15_6/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_or[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -153074,23 +152918,17 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/rx_rd0_addr_valid/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N400_mux15_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done1/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/rx_rd0_addr_valid/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -153798,7 +153636,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/N152_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_and[30][0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -153808,7 +153646,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_or[12]/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_and[38][1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -153818,7 +153656,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N733_8/gateop_perm;gopLUT5
+u_axi_ddr_top/N412_mux15_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -153828,20 +153666,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/rd1_addr_start_fall/opit_0_L5Q;gopL5Q
+N108_0.fsub_11/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/rd1_addr_start_valid0/opit_0;gopQ
@@ -153866,14 +153701,20 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N249_12/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_araddr[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/rd1_cnt_num[2]/opit_0_A2Q21;gopA2Q2
@@ -154084,7 +153925,7 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/rd_all_full/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/record_araddr_valid/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -154100,7 +153941,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -154686,20 +154527,17 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N155.lt_2/gateop_perm;gopA
+u_ddr_addr_ctr/u_wr3_addr_ctr/N108/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N294_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -154709,20 +154547,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/rd3_data_en1/opit_0;gopQ
@@ -154747,7 +154579,7 @@ D;1
RS;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -155413,7 +155245,7 @@ S20;1
S21;1
Inst
-u_axi_ddr_top/rx_rd1_addr_valid/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155429,7 +155261,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155445,14 +155277,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/axi_addr_valid0/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/rd_sta0_reg0/opit_0;gopQ
@@ -155499,7 +155337,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd_sta_reg[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155547,7 +155385,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/rd_sta_reg[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155563,27 +155401,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/N855_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/rx_rd1_addr_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37:0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/rd_sta_reg[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd_all_full/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155610,37 +155460,55 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmrd_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N87/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N406_3[0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -155661,39 +155529,27 @@ D;1
RS;1
Inst
-u_axi_ddr_top/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/N249_14/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/N598/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[11]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155709,7 +155565,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[17]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[18]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155725,7 +155581,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155758,7 +155614,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/s_axi_araddr[12]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155790,23 +155646,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[13]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/s_axi_araddr[14]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155822,7 +155662,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/N412_mux15_12/gateop_perm;gopLUT5
+u_axi_ddr_top/N412_mux15_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -155832,7 +155672,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[3]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155848,7 +155688,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[20]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[26]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155864,7 +155704,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[24]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[16]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155880,7 +155720,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[21]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[19]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155896,7 +155736,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[29]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[20]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155912,7 +155752,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[22]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[21]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155928,17 +155768,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N575/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/s_axi_araddr[28]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[22]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155970,7 +155800,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[27]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[28]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -155986,7 +155816,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[25]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[22]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156002,7 +155832,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[26]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156018,7 +155848,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[22]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[25]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156034,36 +155864,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_20/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_araddr[29]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[27]/opit_0_inv_AQ_perm;gopAQ
-Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[22]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_araddr[27]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156079,56 +155896,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_arid[0]/opit_0;gopQ
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-CE;1
-CLK;1
-D;1
-RS;1
-
-Inst
-u_axi_ddr_top/s_axi_arid[1]/opit_0;gopQ
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-CE;1
-CLK;1
-D;1
-RS;1
-
-Inst
-u_axi_ddr_top/s_axi_arid[2]/opit_0;gopQ
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-CE;1
-CLK;1
-D;1
-RS;1
-
-Inst
-u_axi_ddr_top/s_axi_arlen[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_18/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_23/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -156138,7 +155916,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[64]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[18]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156154,55 +155932,40 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[133]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_arid[0]/opit_0;gopQ
Pin
CEOUT;2
Q;2
RSOUT;2
-Z;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+D;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_arid[1]/opit_0;gopQ
Pin
CEOUT;2
Q;2
RSOUT;2
-Z;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+D;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[97]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_arid[2]/opit_0;gopQ
Pin
CEOUT;2
Q;2
RSOUT;2
-Z;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+D;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_arlen[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156218,7 +155981,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[197]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156234,7 +155997,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[21]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156266,7 +156029,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[15]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156282,7 +156045,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[12]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156298,7 +156061,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[104]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[68]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156314,7 +156077,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[72]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156330,7 +156093,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[139]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[132]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156346,7 +156109,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[77]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[71]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156362,7 +156125,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[73]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156378,7 +156141,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[136]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156394,7 +156157,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[182]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156410,7 +156173,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[18]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[75]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156426,7 +156189,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[49]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[74]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156442,7 +156205,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[42]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156458,7 +156221,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[86]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[78]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156474,7 +156237,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[117]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[73]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156490,17 +156253,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/s_axi_rdata0[55]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[22]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156516,7 +156269,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[30]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[19]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156532,7 +156285,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[27]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[20]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156548,7 +156301,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[59]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[81]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156564,7 +156317,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[89]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[82]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156580,7 +156333,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[92]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[23]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156596,7 +156349,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[95]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[85]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156612,7 +156365,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[255]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[247]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156644,7 +156397,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[89]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156660,7 +156413,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[229]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[90]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156676,7 +156429,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[35]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[155]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156692,7 +156445,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[162]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_70/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[31]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156708,7 +156471,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[101]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[157]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156724,7 +156487,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[167]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[94]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156740,7 +156503,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[100]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[37]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156756,7 +156519,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[103]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[102]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156772,7 +156535,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[41]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[99]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156788,7 +156551,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[146]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[36]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156804,17 +156567,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_135/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[161]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[112]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[160]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156830,7 +156599,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[234]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[39]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156846,7 +156615,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[83]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[166]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156862,7 +156631,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[171]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[45]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156878,7 +156647,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[110]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[42]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156894,7 +156663,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[80]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[170]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156910,7 +156679,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[81]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[107]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156926,7 +156695,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[246]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[105]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156942,7 +156711,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[147]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[173]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156958,7 +156727,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[148]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[136]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156974,7 +156743,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[134]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[200]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -156990,7 +156759,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[113]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[112]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157006,7 +156775,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[183]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[113]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157022,7 +156791,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[248]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[114]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157038,7 +156807,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[58]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[178]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157054,7 +156823,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[185]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[244]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157070,7 +156839,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[251]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[243]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157086,7 +156855,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[187]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[182]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157102,7 +156871,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[184]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[115]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157118,7 +156887,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[63]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[184]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157134,7 +156903,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[190]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[121]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157150,7 +156919,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[96]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[60]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157166,7 +156935,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[68]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[188]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157182,7 +156951,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[194]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[250]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157198,7 +156967,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[98]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[190]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157214,7 +156983,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[70]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[63]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157230,7 +156999,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[165]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[189]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157246,7 +157015,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[130]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[65]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157262,7 +157031,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[135]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[69]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157278,7 +157047,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[75]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[67]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157294,7 +157063,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[207]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157310,7 +157079,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[76]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_34_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[70]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157326,7 +157105,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[200]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157342,7 +157121,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[138]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[128]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157358,7 +157137,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[141]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[77]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157374,7 +157153,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[142]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[76]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157390,7 +157169,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[140]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[142]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157406,7 +157185,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[176]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157422,7 +157201,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_50/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N265_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -157432,23 +157211,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[84]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N151_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[115]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[79]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157464,7 +157237,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[177]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157480,7 +157253,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[151]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[80]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157496,27 +157269,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_103/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[84]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_71/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[48]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[191]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[144]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157532,23 +157317,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[91]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_63/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[122]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[87]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157564,7 +157343,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[26]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[125]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157580,7 +157379,37 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[154]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_66/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_44/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[93]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157596,7 +157425,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[152]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[156]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157612,7 +157441,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[94]/opit_0_L5Q;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[95]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157628,7 +157457,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[61]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[28]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157644,27 +157473,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[97]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[225]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[99]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[101]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157680,17 +157521,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N637_5/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[162]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[160]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[164]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157706,7 +157553,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[225]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[103]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157722,7 +157569,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[164]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[163]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157738,7 +157585,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[231]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[165]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157754,7 +157601,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[11]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[106]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157770,7 +157617,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[106]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[171]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157786,7 +157633,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[107]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[43]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157802,7 +157649,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[210]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[172]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157818,7 +157665,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[172]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[168]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157834,7 +157681,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[128]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_67/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[111]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157850,7 +157707,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[174]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[108]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157866,7 +157723,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[176]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157898,7 +157755,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[114]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[118]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157914,17 +157771,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_90/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/s_axi_rdata0[237]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[179]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157940,7 +157787,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[144]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[177]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157956,7 +157803,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[236]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[119]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -157972,23 +157819,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[169]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[213]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[181]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158004,7 +157845,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[123]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[122]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158020,7 +157861,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[137]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[185]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158036,7 +157877,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[249]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[123]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158052,7 +157893,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[216]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[248]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158068,7 +157909,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[156]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[120]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158100,7 +157941,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[158]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[124]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158116,7 +157957,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[159]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[254]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158132,23 +157973,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[71]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[131]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158164,7 +157999,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[135]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158180,17 +158015,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[193]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[193]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[196]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158206,7 +158047,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[195]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[130]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158222,7 +158063,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[181]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[195]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158238,7 +158079,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[199]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[192]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158254,17 +158095,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[47]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[155]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[139]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158280,7 +158127,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[202]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[140]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158296,7 +158143,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[203]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[201]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158312,7 +158159,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[143]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[141]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158328,20 +158175,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[205]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_87/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/s_axi_rdata0[204]/opit_0_L5Q_perm;gopL5Q
@@ -158360,7 +158201,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[78]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[202]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158376,7 +158217,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[118]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[17]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158392,7 +158233,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[150]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[147]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158408,7 +158249,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[168]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[208]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158424,23 +158265,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[179]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_107/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[170]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[211]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158456,7 +158291,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[175]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[150]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158472,7 +158307,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[214]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[151]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158488,7 +158323,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[247]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[215]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158504,17 +158339,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_67/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[153]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[217]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[25]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158530,7 +158371,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[218]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[216]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158546,7 +158387,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[201]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[219]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158578,7 +158419,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[221]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[158]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158594,7 +158435,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[222]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[159]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158610,7 +158451,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_130/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -158620,17 +158461,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[229]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[161]/opit_0_L5Q;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[224]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158646,7 +158493,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[36]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[226]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158662,7 +158509,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[166]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[227]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158678,7 +158525,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[230]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[228]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158694,7 +158541,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[231]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158710,7 +158557,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[226]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[167]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158726,17 +158573,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[105]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[174]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158752,7 +158605,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[232]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[233]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158768,7 +158621,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[180]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[234]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158784,7 +158637,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[173]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[235]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158800,7 +158653,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[192]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[236]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158816,7 +158669,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[212]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[237]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158832,7 +158685,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[238]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[175]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158848,7 +158701,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[239]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N124_5/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[240]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158864,7 +158727,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_107/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_63/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -158874,7 +158737,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[240]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[241]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158890,23 +158753,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[241]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_46/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[211]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[51]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158922,7 +158779,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[43]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[183]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158938,7 +158795,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[245]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[246]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158954,7 +158811,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[242]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_103/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/s_axi_rdata0[186]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158970,7 +158837,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[198]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[249]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -158986,7 +158853,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[250]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[187]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159002,7 +158869,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[186]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[58]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159018,7 +158885,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[60]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[251]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159034,7 +158901,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[188]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[191]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159066,7 +158933,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_82/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159076,7 +158943,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[254]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[199]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159092,7 +158959,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[56]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[194]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159108,7 +158975,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[53]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159124,7 +158991,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[196]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[197]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159140,27 +159007,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[64]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[65]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[198]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159176,37 +159039,55 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N701_7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/N4_4/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[232]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[207]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159222,17 +159103,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[205]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[157]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159248,7 +159135,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[74]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159280,7 +159167,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[120]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159296,7 +159183,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[13]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159312,7 +159199,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[223]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[209]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159328,7 +159215,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[209]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[210]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159344,27 +159231,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_105/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_71/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159374,17 +159241,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[212]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[215]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[213]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159400,17 +159273,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_64/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[146]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_98/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159420,7 +159299,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[29]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[148]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159436,7 +159315,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[219]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[217]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159452,7 +159331,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[90]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[218]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159468,23 +159347,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[25]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[28]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[221]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159500,7 +159373,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_46/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159510,17 +159383,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[29]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[125]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[223]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159536,7 +159415,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N456/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159546,23 +159425,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[227]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N21_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[228]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159578,23 +159451,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N20_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[41]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159610,7 +159477,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/N1_2_cpy/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159626,7 +159503,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159642,7 +159519,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3377/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_35/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159652,7 +159529,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[233]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[239]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159668,39 +159545,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[40]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_99/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[244]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_95/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[23]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[27]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159716,7 +159581,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[45]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[92]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159732,7 +159597,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_115/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159742,7 +159607,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_97/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159752,7 +159617,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[243]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159768,7 +159633,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_117/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_66/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159778,7 +159643,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[17]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[242]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159794,27 +159659,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_75/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[54]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N564_35/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[245]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[52]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[154]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159840,17 +159717,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_136/gateop_perm;gopLUT5
+u_axi_ddr_top/s_axi_rdata0[24]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159860,7 +159743,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_36/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159870,39 +159753,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[57]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[252]/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[252]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159918,23 +159789,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/s_axi_rdata0[189]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_74/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[255]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -159950,7 +159815,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_118/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -159960,7 +159825,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_83/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -163066,27 +162931,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163102,7 +162979,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163118,7 +162995,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -163128,7 +163005,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163144,7 +163021,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163160,17 +163037,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163186,20 +163069,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0;gopQ
@@ -163496,7 +163373,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163528,7 +163405,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163544,7 +163421,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163576,7 +163473,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163592,7 +163489,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163608,17 +163505,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163634,7 +163521,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163650,17 +163537,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163808,7 +163685,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -163818,7 +163695,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -163828,7 +163705,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -163838,27 +163715,39 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -163868,17 +163757,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -163914,17 +163809,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -163934,23 +163835,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_11/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -163960,23 +163855,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -163986,7 +163875,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -164006,7 +163895,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -164022,17 +163911,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -164042,17 +163937,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[17]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_35/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -164062,7 +163963,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -164072,7 +163973,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -164082,43 +163983,49 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N151_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -164128,7 +164035,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -164138,7 +164045,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -164154,7 +164061,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N151_2/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -165484,7 +165391,7 @@ WR_EOP;1
WR_ERR;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165494,7 +165401,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_31/gateop_perm;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165504,23 +165411,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/cnt_times[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165530,7 +165431,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165540,20 +165441,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N21.eq_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_19/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165563,7 +165451,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_22/gateop_perm;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165573,7 +165461,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165583,36 +165471,24 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_araddr[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[21]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_33/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
@@ -165625,7 +165501,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N448_7/gateop_perm;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165635,23 +165511,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165661,7 +165531,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_30/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165671,39 +165541,43 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[25]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N21.eq_4/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[8]/gateop;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N24.eq_4/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165713,14 +165587,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_3_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2;gopA2
@@ -165763,20 +165643,14 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_31/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2;gopA2
@@ -165819,7 +165693,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_25/gateop_perm;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -165975,7 +165849,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_30/gateop_perm;gopLUT5
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166359,7 +166233,7 @@ WR_EOP;1
WR_ERR;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N21_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166369,7 +166243,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[33]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -166401,7 +166275,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/N32_mux8_9/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166411,7 +166285,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -166437,36 +166311,24 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/cnt_times[0]/opit_0_inv_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
@@ -166479,17 +166341,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/N85/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_empty0/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/N134_78/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166599,20 +166467,14 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_full0/opit_0_L5Q_perm;gopL5Q
@@ -166631,17 +166493,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/cnt1_w[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/rd1_data_valid0/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -166657,24 +166525,36 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_6/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[19]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
@@ -166725,7 +166605,7 @@ L4;1
RS;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/N114_mux5_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166789,17 +166669,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_1_7/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/N45_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166819,30 +166689,23 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N111.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[3]/gateop;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166852,7 +166715,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -166878,7 +166741,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[7]/gateop;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/N188_40/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166888,20 +166751,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/N155.fsub_5/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst/hybrid_filter_inst/N146_mux2_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166911,37 +166761,68 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
+image_filiter_inst2/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N39.lt_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166951,7 +166832,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166961,7 +166842,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166971,7 +166852,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[3]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166981,7 +166862,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -166991,7 +166872,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -167001,7 +166882,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/N118_mux3_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -167021,100 +166902,44 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2;gopA2
-Pin
-Cout;2
-Y0;2
-Y1;2
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-
-Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2;gopA2
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5
Pin
-Cout;2
-Y0;2
-Y1;2
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21;gopA2Q2
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N167.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
+Y;2
Cin;1
+I0;1
I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21;gopA2Q2
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2;gopA2
Pin
-CEOUT;2
Cout;2
-Q0;2
-Q1;2
-RSOUT;2
Y0;2
Y1;2
-CE;1
-CLK;1
Cin;1
I0X;1
I1X;1
@@ -167128,20 +166953,13 @@ I11;1
I12;1
I13;1
I14;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21;gopA2Q2
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2;gopA2
Pin
-CEOUT;2
Cout;2
-Q0;2
-Q1;2
-RSOUT;2
Y0;2
Y1;2
-CE;1
-CLK;1
Cin;1
I0X;1
I1X;1
@@ -167155,10 +166973,9 @@ I11;1
I12;1
I13;1
I14;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21;gopA2Q2
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -167185,7 +167002,88 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21;gopA2Q2
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -167257,7 +167155,7 @@ I14;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/N142_mux4_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -167771,33 +167669,33 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -167807,20 +167705,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
@@ -167839,14 +167731,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q
@@ -167865,7 +167763,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168152,17 +168050,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -168178,7 +168082,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -168220,7 +168124,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -168236,30 +168140,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N35.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N287_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0;gopQ
@@ -168382,7 +168283,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168392,7 +168293,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168402,7 +168303,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168412,7 +168313,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -168428,7 +168329,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168454,27 +168365,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_3/gateop_perm;gopLUT5
@@ -168487,17 +168391,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168507,7 +168417,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_7/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168517,7 +168427,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168527,17 +168437,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168547,7 +168463,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168557,7 +168473,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168567,23 +168483,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168593,23 +168503,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N17_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168629,7 +168536,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168639,33 +168546,30 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/N45_8/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168675,23 +168579,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -168747,7 +168645,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N287_5/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -168797,20 +168695,17 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/N99.fsub_5/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0;gopQ
@@ -169194,20 +169089,14 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -169372,7 +169261,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -169404,7 +169293,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -169436,7 +169335,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -169446,7 +169345,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -169462,7 +169361,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -169477,16 +169376,6 @@ L3;1
L4;1
RS;1
-Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q
Pin
@@ -169504,7 +169393,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -169759,7 +169648,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -169775,7 +169664,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -169791,23 +169680,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -169823,17 +169706,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -169843,14 +169732,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
@@ -169885,14 +169780,23 @@ L4;1
RS;1
Inst
-u_rotate_image/N44_mux7_7/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_AQ_perm;gopAQ
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0;gopQ
@@ -170025,39 +169929,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170067,7 +169959,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170077,17 +169969,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170097,7 +169995,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N287_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170107,7 +170005,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170117,7 +170015,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_4/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/u1/N256_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170127,17 +170025,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_perm;gopA
+u_ov5640/coms1_reg_config/N1193_3/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_7/gateop_perm;gopLUT5
@@ -170150,7 +170045,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170160,7 +170055,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -170186,7 +170081,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170196,7 +170091,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170206,7 +170101,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -170222,7 +170117,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170232,7 +170127,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170242,7 +170137,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170262,7 +170157,7 @@ L3;1
L4;1
Inst
-u_rotate_image/N44_mux7_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170272,7 +170167,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[3]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170282,17 +170177,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -170308,7 +170209,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170318,7 +170219,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -170374,7 +170275,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N287_5/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -170504,20 +170405,14 @@ I13;1
I14;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[12]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/N85/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0;gopQ
@@ -171255,7 +171150,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -171265,7 +171160,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -171275,7 +171170,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -171295,7 +171190,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N22.eq_4/gateop_perm;gopA
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -171308,7 +171203,7 @@ I3;1
I4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_38/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -171318,7 +171213,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_rdata0[121]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/s_axi_rdata0[50]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -171334,7 +171229,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -171344,23 +171239,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -171380,7 +171269,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -171390,17 +171279,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N109.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/N32_mux8_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -171420,14 +171312,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N22.eq_4/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
@@ -171440,7 +171335,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -171450,30 +171345,27 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[10]/gateop;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N111.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N22.eq_0/gateop_A2;gopA2
@@ -171516,7 +171408,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -171765,14 +171657,20 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -173956,7 +173854,7 @@ WR_EOP;1
WR_ERR;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N576_inv/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N244/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -173966,7 +173864,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N196_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N448_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -173986,23 +173884,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/s_axi_araddr[16]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/u_axi_wr_connect/N294_8/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174012,7 +173894,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_9[11]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N249_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174022,7 +173904,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_9[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N574_9[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174032,17 +173914,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N294_13/gateop_perm;gopLUT5
+u_axi_ddr_top/rd0_ddr_done1/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N469_4/gateop_perm;gopLUT5
+u_axi_ddr_top/N866_2_and[34][0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174052,7 +173940,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N598/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N565/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174062,7 +173950,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N264_13/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N574_9[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174072,7 +173960,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N264_14/gateop_perm;gopLUT5
+u_axi_ddr_top/N261_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174098,7 +173986,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_9[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N264_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174108,7 +173996,26 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_9[10]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[27]/opit_0_AQ_perm;gopAQ
+Pin
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
+
+Inst
+u_axi_ddr_top/u_axi_wr_connect/N574_9[19]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174128,17 +174035,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_9[19]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_35/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N448_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174148,7 +174061,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[26]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174174,75 +174087,79 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N565/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N61_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_addr_valid0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/rd_sta_reg[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[11]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/N256_5/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174258,7 +174175,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N592/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N574_9[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174268,7 +174185,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_9[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N574_9[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174278,7 +174195,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done0/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174294,7 +174211,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_9[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N574_9[20]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174304,7 +174221,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_9[12]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N574_9[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174314,7 +174231,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174330,7 +174247,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_18/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N575/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174340,23 +174257,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/rx0_addr_valid/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/N574_9[12]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done1/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174372,27 +174283,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/N866_2_or[4]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/u_axi_wr_connect/N249_13/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/rx0_addr_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/N20_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N592/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -174468,23 +174375,17 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[15]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/N196_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[24]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/cnt_times[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174500,17 +174401,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N610/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/s_axi_araddr[10]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/rx1_addr_valid/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174526,14 +174433,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N249_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/axi_addr0[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -174838,7 +174751,17 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_valid0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174854,7 +174777,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[51]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174870,7 +174793,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[16]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174886,7 +174809,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174902,7 +174825,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[19]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174918,7 +174841,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[18]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174934,7 +174857,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[23]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174950,7 +174873,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[22]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[20]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174966,7 +174889,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[7]/opit_0_L5Q;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174982,7 +174905,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[28]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[62]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -174998,7 +174921,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[9]/opit_0_L5Q;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175014,7 +174937,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[11]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175030,7 +174953,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[40]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175046,7 +174969,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[13]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175062,7 +174985,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[42]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/N99.fsub_5/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[59]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175078,7 +175014,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[15]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[49]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175094,7 +175030,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[56]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[34]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175110,7 +175046,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[20]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[36]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175126,7 +175062,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[35]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[21]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175142,7 +175078,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[32]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[22]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175174,7 +175110,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[39]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[23]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175190,7 +175126,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[34]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[32]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175206,7 +175142,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[25]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175222,7 +175158,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[27]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175238,7 +175174,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[25]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[29]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175254,7 +175190,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[27]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[61]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175270,7 +175206,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[31]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[30]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175286,7 +175222,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[30]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[57]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175302,7 +175238,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[44]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[31]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175318,7 +175254,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[45]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[58]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175334,7 +175270,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[10]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[42]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175350,7 +175286,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[8]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[35]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175366,7 +175302,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[50]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[54]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175382,17 +175318,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N254/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[55]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[37]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175408,7 +175350,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[36]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[52]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175424,7 +175366,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[53]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[39]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175440,7 +175382,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[37]/opit_0_L5Q;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[48]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175456,7 +175398,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[48]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[41]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175472,7 +175414,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[38]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[44]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175488,7 +175430,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[41]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[43]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175504,7 +175446,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[14]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[46]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175520,7 +175462,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[43]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[45]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175536,7 +175478,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[10]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[26]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175552,7 +175494,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[58]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[47]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175568,7 +175510,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[46]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[40]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175584,7 +175526,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[47]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[51]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175600,7 +175542,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[50]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175616,7 +175558,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[49]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[53]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175632,23 +175574,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[54]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[21]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[38]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175664,7 +175600,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175680,7 +175616,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[52]/opit_0_L5Q;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[55]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175696,39 +175632,27 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/delay_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[17]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[60]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175744,7 +175668,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[57]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175760,17 +175684,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/wr_sta_fsm[3:0]_7/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N35.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[59]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_deb_pre/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175786,7 +175713,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[60]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[28]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175802,7 +175729,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[61]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[63]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175818,7 +175745,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[12]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175834,7 +175761,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[63]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -175850,34 +175777,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[4]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_26/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/cnt_times[2]/opit_0_A2Q21;gopA2Q2
@@ -175988,7 +175901,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -176015,7 +175928,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_9[20]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr0_addr_ctr/N7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -176078,7 +175991,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -176109,6 +176022,16 @@ L3;1
L4;1
RS;1
+Inst
+u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[2:0]_e/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[2]/opit_0_L5Q_perm;gopL5Q
Pin
@@ -176126,7 +176049,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -176142,7 +176065,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/rd0_ddr_done1/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -176158,7 +176081,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -176174,7 +176097,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2:0]_e/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr3_addr_ctr/N1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -176184,7 +176107,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd0_addr_start_fall/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -176200,17 +176123,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N249_14/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -176220,7 +176133,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -176230,7 +176143,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N440/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -176402,7 +176315,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -176434,23 +176347,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -176508,7 +176415,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -176518,23 +176425,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -176816,14 +176717,20 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
@@ -176842,20 +176749,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
@@ -176874,7 +176775,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -176890,17 +176791,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -176932,7 +176839,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177062,7 +176969,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177072,7 +176979,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177082,7 +176989,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177092,23 +176999,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/rd_importance/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177134,7 +177035,7 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/N86_mux4_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177144,14 +177045,20 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/N90_mux2_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
@@ -177164,33 +177071,23 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/N99.fsub_5/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177200,7 +177097,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177210,30 +177107,30 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5
@@ -177246,7 +177143,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177256,23 +177153,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177282,23 +177173,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177308,7 +177193,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -177324,23 +177209,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177350,7 +177229,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/N106_72/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177360,17 +177239,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[56]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177393,27 +177278,39 @@ I3;1
I4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/N114_mux5_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[24]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -177423,7 +177320,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_8/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -177533,14 +177446,20 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5.fsub_1/gateop_A2;gopA2
@@ -177583,14 +177502,17 @@ I13;1
I14;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N161.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1;gopA2Q1
@@ -178382,7 +178304,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -178565,7 +178487,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -178581,20 +178503,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
@@ -178613,23 +178529,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -178645,34 +178555,52 @@ L4;1
RS;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[11]/gateop_perm;gopLUT5
+u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0;gopQ
@@ -178947,7 +178875,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -178979,17 +178907,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -179021,14 +178955,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N471_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
@@ -179047,7 +178987,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -179063,7 +179003,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N39_mux3/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179073,7 +179013,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179203,7 +179143,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179213,7 +179153,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179233,7 +179173,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179243,7 +179183,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N258/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179253,33 +179193,33 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[16]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N404/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179289,7 +179229,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N132/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179309,17 +179249,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N410/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179329,7 +179275,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -179345,7 +179301,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179355,7 +179311,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179375,23 +179331,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179401,7 +179351,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179411,7 +179361,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179421,7 +179371,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179431,7 +179381,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179441,17 +179391,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179461,7 +179417,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd3_data_valid0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -179477,7 +179433,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179487,17 +179443,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5
+u_rotate_image/rd_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179507,7 +179469,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179517,7 +179479,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179537,23 +179499,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/fifo1_data_full/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -179663,14 +179609,17 @@ I13;1
I14;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N161.eq_4/gateop;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5.fsub_1/gateop_A2;gopA2
@@ -179713,7 +179662,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -180512,7 +180461,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -180679,7 +180628,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -180695,7 +180644,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -180711,17 +180660,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -180747,20 +180702,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
@@ -180779,23 +180728,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181076,6 +181019,16 @@ I13;1
I14;1
RS;1
+Inst
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
@@ -181093,17 +181046,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -181119,7 +181078,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181129,7 +181088,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -181145,23 +181104,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -181177,7 +181130,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181187,7 +181140,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -181202,16 +181155,6 @@ L3;1
L4;1
RS;1
-Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0;gopQ
Pin
@@ -181323,7 +181266,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181333,7 +181276,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181343,7 +181286,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181353,7 +181296,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181363,17 +181306,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181383,7 +181332,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -181399,27 +181358,39 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/fifo0_data_full/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181429,17 +181400,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -181455,7 +181432,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181465,7 +181442,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -181481,7 +181458,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181491,7 +181468,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181501,7 +181478,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181511,7 +181488,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -181527,7 +181504,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181537,7 +181514,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181547,20 +181524,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N161.eq_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/N296_8/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_25/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181570,7 +181534,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181580,7 +181544,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181590,7 +181554,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181600,33 +181564,30 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/fifo3_data_full/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N155.lt_2/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/median_finder9_r/N188_40/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181636,20 +181597,14 @@ L3;1
L4;1
Inst
-u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5
@@ -181662,7 +181617,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -181672,14 +181627,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N161.eq_4/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_0/gateop_A2;gopA2
@@ -181782,7 +181740,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -181838,7 +181796,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/N589/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -182720,7 +182678,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -182753,27 +182711,23 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N258/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_23/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -182789,7 +182743,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N87/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -182799,23 +182753,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[17]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/N576_inv/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/rx3_addr_valid/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -182847,7 +182795,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/cnt0_times[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -182862,6 +182810,16 @@ L3;1
L4;1
RS;1
+Inst
+u_axi_ddr_top/u_axi_wr_connect/N249_8/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[2]/opit_0_A2Q21;gopA2Q2
Pin
@@ -183071,7 +183029,7 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -183087,7 +183045,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done1/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -183301,14 +183259,20 @@ D;1
RS;1
Inst
-u_axi_ddr_top/N878/gateop_perm;gopLUT5
+u_axi_ddr_top/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[2]/opit_0_A2Q21;gopA2Q2
@@ -183519,30 +183483,30 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/N866_2_or[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done1/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/N264_12/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[13]/opit_0;gopQ
@@ -183743,7 +183707,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N264_12/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N610/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -183961,17 +183925,23 @@ I4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_9[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N294_12/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N574_7_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -184139,14 +184109,20 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -184311,17 +184287,23 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -184331,20 +184313,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
@@ -184379,7 +184355,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -184395,17 +184371,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -184421,7 +184403,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -184463,14 +184445,20 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0;gopQ
@@ -184783,7 +184771,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -184815,7 +184803,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -184825,20 +184813,14 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
@@ -184857,17 +184839,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -184899,7 +184887,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -184915,7 +184903,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -184931,20 +184919,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0;gopQ
@@ -185079,7 +185061,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -185089,17 +185071,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185109,49 +185097,43 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185161,7 +185143,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185171,23 +185153,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N240_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185197,7 +185173,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185207,7 +185183,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185217,7 +185193,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185227,7 +185203,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185237,7 +185213,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -185253,7 +185229,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185263,7 +185239,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185273,7 +185249,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185283,7 +185259,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
+u_axi_ddr_top/wr_sta_fsm[3:0]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185293,23 +185269,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_10/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185319,52 +185289,34 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1169/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5
@@ -185377,7 +185329,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N252/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185387,7 +185339,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185397,7 +185349,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N212/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -185407,56 +185359,56 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
+u_axi_ddr_top/wr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_10/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N167.eq_0/gateop_A2;gopA2
@@ -185948,7 +185900,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -186099,37 +186051,55 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186139,7 +186109,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -186171,7 +186141,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -186187,43 +186157,40 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N150.eq_4/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_1/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0;gopQ
@@ -186471,7 +186438,7 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -186487,7 +186454,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -186503,30 +186470,30 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
@@ -186545,23 +186512,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -186577,20 +186538,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/rd3_data_valid0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
@@ -186609,14 +186564,20 @@ L4;1
RS;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0;gopQ
@@ -186729,7 +186690,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186739,7 +186700,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186749,7 +186710,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186759,7 +186720,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186769,23 +186730,30 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_7/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N147.eq_4/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186795,7 +186763,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186805,23 +186773,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186831,7 +186793,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N276_5/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186841,30 +186803,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N147.eq_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N154_mux6_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186884,7 +186839,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186894,7 +186849,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186904,7 +186859,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186914,17 +186869,36 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N150.eq_4/gateop_perm;gopA
Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186934,7 +186908,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186944,7 +186918,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -186960,7 +186934,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186970,7 +186944,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_4/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1201/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186980,7 +186954,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -186990,23 +186964,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N276_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -187022,30 +186990,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_8/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N147.eq_0/gateop_A2;gopA2
@@ -187088,14 +187040,20 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N154_mux6_6/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N150.eq_0/gateop_A2;gopA2
@@ -187138,17 +187096,23 @@ I13;1
I14;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/N296_9/gateop_perm;gopLUT5
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -187178,20 +187142,14 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N543[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0;gopQ
@@ -187636,7 +187594,7 @@ WEA;1
WEB;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -187646,23 +187604,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -187682,27 +187634,39 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[193]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[192]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -187712,14 +187676,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
@@ -187732,46 +187702,33 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N25.eq_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[1]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -187787,7 +187744,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cas_n/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -187803,7 +187760,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N373_1_or[0][2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -187813,27 +187770,39 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[128]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N406_3[0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -187853,7 +187822,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/init_start/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -187869,7 +187838,23 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[196]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[96]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -187985,7 +187970,7 @@ I13;1
I14;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_77/gateop_perm;gopLUT5
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -188152,7 +188137,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N238/gateop_perm;gopLUT5
+u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -190371,17 +190356,23 @@ WR_EOP;1
WR_ERR;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/N1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/N180_5/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -190402,7 +190393,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/wr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/wr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -190418,7 +190409,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/wr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_act/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -190434,23 +190425,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/wr_sta_reg[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -190476,7 +190461,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/N73_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -190508,7 +190493,7 @@ D;1
RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N229_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_26/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -190540,7 +190525,7 @@ D;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/N142_mux4_3/gateop_perm;gopLUT5
+u_ddr_addr_ctr/N72_16/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -190550,7 +190535,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/N69_10/gateop_perm;gopLUT5
+u_ddr_addr_ctr/N76_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -190560,7 +190545,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/vs_30hz/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -190592,30 +190577,23 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N107.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_ddr_addr_ctr/N69_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N93_mux7_12/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N619_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -190868,34 +190846,7 @@ I14;1
RS;1
Inst
-u_ddr_addr_ctr/clk_cnt[20]/opit_0_A2Q21;gopA2Q2
-Pin
-CEOUT;2
-Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
-
-Inst
-u_ddr_addr_ctr/clk_cnt[21]/opit_0_AQ;gopAQ
+u_ddr_addr_ctr/clk_cnt[19]/opit_0_AQ;gopAQ
Pin
CEOUT;2
Cout;2
@@ -190925,7 +190876,7 @@ D;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/N20_9/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd0_addr_ctr/N152_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -190945,7 +190896,7 @@ L3;1
L4;1
Inst
-u_hdm_in_rst/rst/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -190977,20 +190928,14 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt0/opit_0;gopQ
@@ -191047,23 +190992,17 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/vs_15hz/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/N294_12/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/N866_2_and[24][0]_1/gateop_perm;gopLUT5
+u_axi_ddr_top/N400_mux15_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -191316,7 +191255,7 @@ I14;1
RS;1
Inst
-u_rotate_image/N131_mux1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/N574_9[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -191348,7 +191287,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/N866_2_and[38][1]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd0_addr_ctr/N20_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -191358,42 +191297,54 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_wr_connect/N294_13/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[7]/opit_0_AQ_perm;gopAQ
+u_hdmi_in_top/N46/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[2]/opit_0_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
-Q;2
+Q0;2
+Q1;2
RSOUT;2
-Y;2
+Y0;2
+Y1;2
CE;1
CLK;1
Cin;1
-I0;1
I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[2]/opit_0_A2Q21;gopA2Q2
+u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[4]/opit_0_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -191420,7 +191371,7 @@ I14;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[4]/opit_0_A2Q21;gopA2Q2
+u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[6]/opit_0_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -191447,42 +191398,24 @@ I14;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[6]/opit_0_A2Q21;gopA2Q2
+u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[7]/opit_0_AQ;gopAQ
Pin
CEOUT;2
Cout;2
-Q0;2
-Q1;2
+Q;2
RSOUT;2
-Y0;2
-Y1;2
+Y;2
CE;1
CLK;1
Cin;1
+I0;1
I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
-Inst
-u_axi_ddr_top/N866_2_and[25][0]_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[0]/opit_0;gopQ
Pin
@@ -191539,7 +191472,7 @@ D;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid1/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -191555,7 +191488,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/N16/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -191565,36 +191498,33 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid0/opit_0_inv_L5Q_perm;gopL5Q
@@ -191645,14 +191575,20 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ddr_addr_ctr/u_rd1_addr_ctr/gen_start_addr3[19]/opit_0;gopQ
@@ -192006,17 +191942,14 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA
+u_rotate_image/rotate_sta_fsm[2:0]_1/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_ddr_addr_ctr/u_rd1_addr_ctr/rd3_image_cnt[0]/opit_0;gopQ
@@ -192232,17 +192165,20 @@ L4;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N83.lt_2/gateop_perm;gopA
+vs_down_delay_cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done0/opit_0;gopQ
@@ -192278,30 +192214,24 @@ D;1
RS;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
+u_ov5640/u_mix_image/N417/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N87.lt_2/gateop_perm;gopA
+u_ov5640/u_mix_image/rd_sta_fsm[4:0]_5/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs0/opit_0;gopQ
@@ -192326,7 +192256,7 @@ D;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/N206/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192336,7 +192266,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192346,43 +192276,34 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/N109.lt_2/gateop_perm;gopA
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
@@ -192395,7 +192316,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192405,7 +192326,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[6]/gateop;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/N206/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192415,7 +192336,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192425,7 +192346,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192435,7 +192356,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192445,7 +192366,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192455,7 +192376,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192465,7 +192386,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192475,26 +192396,23 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_AQ_perm;gopAQ
+u_ov5640/u_mix_image/data_out1[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
-Cout;2
Q;2
RSOUT;2
-Y;2
+Z;2
CE;1
CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192504,7 +192422,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N427/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192514,7 +192432,7 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/N259/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -192524,14 +192442,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid1/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2;gopA2
@@ -192717,7 +192641,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/N271_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -193120,17 +193044,23 @@ D;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/rd1_ddr_done1/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[0]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -193162,7 +193092,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[19]/opit_0_L5Q_perm;gopL5Q
+u_hdmi_in_top/hs_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -193188,7 +193118,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd3_addr_ctr/N44_mux4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -193208,17 +193138,14 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N35.lt_2/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_ddr_addr_ctr/u_rd3_addr_ctr/N56_1_1/gateop_A2;gopA2
@@ -193779,20 +193706,14 @@ D;1
RS;1
Inst
-u_rotate_image/image_blank_valid/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[21]/opit_0;gopQ
@@ -194591,20 +194512,23 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/N0.eq_2/gateop_perm;gopA
+u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[18]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[11]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -194652,7 +194576,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[14]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -194668,7 +194592,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[18]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -194684,7 +194608,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[21]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[16]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -194716,7 +194640,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[19]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -194732,7 +194656,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[15]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[22]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -194764,17 +194688,23 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/N130_inv/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[21]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[22]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -194790,7 +194720,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/N7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -195159,7 +195089,7 @@ D;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[2]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195175,7 +195105,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195223,7 +195153,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195261,7 +195191,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195297,7 +195227,7 @@ I13;1
I14;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195478,7 +195408,7 @@ D;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[1]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195549,17 +195479,23 @@ D;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/N108/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd1_ddr_done1/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195575,7 +195511,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr3_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195639,23 +195575,17 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr1_addr_ctr/N7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[2]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195671,17 +195601,23 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/N132/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[3]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195713,7 +195649,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195729,14 +195665,20 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/N7/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[19]/opit_0;gopQ
@@ -195827,7 +195769,7 @@ D;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195843,7 +195785,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
+vs_pos_delay_cnt[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195908,7 +195850,7 @@ D;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195924,17 +195866,36 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/N130_inv/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/N0.eq_2/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+u_axi_ddr_top/u_axi_rd_connect/rd1_fifo_full0/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -195950,20 +195911,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/N0.eq_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[0]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -196011,23 +195959,17 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done0/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr1_addr_ctr/N130_inv/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[0]/opit_0_L5Q;gopL5Q
+u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -196075,7 +196017,7 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/N866_2_or[1]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr1_addr_ctr/N132/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -196085,20 +196027,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/rx1_addr_valid/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/N0.eq_2/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/N0.eq_0/gateop_A2;gopA2
@@ -196121,7 +196060,7 @@ I13;1
I14;1
Inst
-u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[1]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -196357,17 +196296,23 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_7_1/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_fsm[1:0]_16/gateop_perm;gopLUT5
+N104_mux11_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -196546,7 +196491,7 @@ D;1
RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[2:0]_e/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_ac4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -196556,23 +196501,17 @@ L3;1
L4;1
Inst
-u_ddr_addr_ctr/u_wr3_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr3_addr_ctr/N103/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm;gopL5Q
+u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -196588,20 +196527,14 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_fsm[1:0]_16/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm;gopL5Q
@@ -196652,14 +196585,20 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr3_addr_ctr/N108/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[1]/opit_0_L5Q_perm;gopL5Q
@@ -196694,7 +196633,7 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -196792,7 +196731,7 @@ D;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr3_addr_ctr/N103/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr0_addr_ctr/N130_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -196834,14 +196773,20 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5
+u_ddr_addr_ctr/vs_15hz/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs0/opit_0;gopQ
@@ -196877,7 +196822,7 @@ D;1
RS;1
Inst
-u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr0_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -196893,20 +196838,23 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA
+u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall0/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-image_filiter_inst2/multiline_buffer_inst/N229_9/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_26[0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -196916,7 +196864,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N464/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_11_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -196948,7 +196896,7 @@ D;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd1_addr_ctr/N271_inv/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_40/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -196958,7 +196906,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N866_2_or[2]/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/u1/N25[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -196990,23 +196938,17 @@ D;1
RS;1
Inst
-image_filiter_inst/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm;gopL5Q
+N299_11/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+u_hdmi_in_top/N55/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -197268,7 +197210,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2:0]_e/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -197575,7 +197517,7 @@ D;1
RS;1
Inst
-u_hdmi_in_top/N55/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr0_addr_ctr/N108/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -197585,27 +197527,36 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N83.lt_2/gateop_perm;gopA
+vs_pos_delay_cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-u_hdmi_in_top/N46/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_hdmi_in_top/hs_cnt[1]/opit_0_L5Q;gopL5Q
@@ -197910,23 +197861,17 @@ D;1
RS;1
Inst
-u_hdmi_rst/rst/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N183/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_sync_vg/N50_mux2_7/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/N154_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -198228,14 +198173,20 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/N1/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/cmos1_8_16bit/pdata_i0[0]/opit_0;gopQ
@@ -198744,7 +198695,7 @@ D;1
RS;1
Inst
-u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q;gopL5Q
+u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -199496,7 +199447,7 @@ D;1
RS;1
Inst
-u_ov5640/coms1_reg_config/N26_mux2/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/N8_mux7_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -199506,7 +199457,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/N12/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/N8_mux10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -199516,7 +199467,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/N1114[0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -199626,7 +199577,7 @@ I13;1
I14;1
Inst
-u_ov5640/coms1_reg_config/N1114[0]_1/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/N1114[0]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -199636,23 +199587,17 @@ L3;1
L4;1
Inst
-u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_ov5640/coms1_reg_config/N26_mux6_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/coms1_reg_config/u1/N267_21/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/u1/N8_mux3_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -199662,30 +199607,30 @@ L3;1
L4;1
Inst
-u_ov5640/coms1_reg_config/N8_mux7_3/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_vary0/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/coms1_reg_config/u1/cyc_count[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_ov5640/coms1_reg_config/u1/N239/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/coms1_reg_config/N1169/gateop_perm;gopLUT5
@@ -199698,7 +199643,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms1_reg_config/N1193_3/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -199708,7 +199653,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/u1/N25[0]/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/u1/N267_21/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -200155,7 +200100,7 @@ WR_EOP;1
WR_ERR;1
Inst
-u_ov5640/coms1_reg_config/N12/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -200273,7 +200218,7 @@ I14;1
RS;1
Inst
-u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm;gopL5Q
+u_ov5640/coms1_reg_config/u1/sclk/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -200289,7 +200234,7 @@ L4;1
RS;1
Inst
-u_ov5640/coms1_reg_config/u1/N25[0]/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/N1134_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -200309,7 +200254,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms1_reg_config/u1/N256_2_2/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/u1/N195_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -200319,7 +200264,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms1_reg_config/u1/N256_4/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/u1/N256_2_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -200339,7 +200284,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetY/N150_1/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/u1/N256_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -200349,7 +200294,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms1_reg_config/u1/N256_3/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/N1134/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -200359,7 +200304,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms1_reg_config/u1/sclk/opit_0_inv_L5Q_perm;gopL5Q
+u_ov5640/coms1_reg_config/reg_conf_done_reg/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -200375,14 +200320,20 @@ L4;1
RS;1
Inst
-u_ov5640/coms1_reg_config/N1134/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/cnt0_w[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/coms1_reg_config/u1/N262_46_3/gateop;gopMUX4TO1
@@ -200396,14 +200347,20 @@ S0;1
S1;1
Inst
-u_ov5640/coms2_reg_config/u1/N195_inv/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/coms1_reg_config/u1/N267_18_muxf7;gopMUX16TO1
@@ -200441,14 +200398,20 @@ S20;1
S21;1
Inst
-u_ov5640/coms1_reg_config/N1134_1/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/u1/cyc_count[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/coms1_reg_config/u1/N267_24/gateop;gopMUX4TO1
@@ -200473,20 +200436,14 @@ S0;1
S1;1
Inst
-u_ov5640/coms1_reg_config/reg_conf_done_reg/opit_0_inv_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/coms1_reg_config/u1/N267_36/gateop;gopMUX4TO1
@@ -200573,14 +200530,20 @@ I14;1
RS;1
Inst
-u_ov5640/coms2_reg_config/u1/N146_8/gateop_perm;gopLUT5
+u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
@@ -200600,7 +200563,7 @@ S0;1
S1;1
Inst
-u_ov5640/power_on_delay_inst/N15_mux15_4/gateop_perm;gopLUT5
+u_ov5640/coms1_reg_config/N26_mux2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -200610,14 +200573,20 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/u1/N8_mux3_1/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/coms2_reg_config/N8_mux7_3/gateop_perm;gopLUT5
@@ -200640,7 +200609,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/N1114[0]_1/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/N12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -200750,7 +200719,7 @@ I13;1
I14;1
Inst
-u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_hdmi_in_top/hdmi_in_en/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -200776,7 +200745,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/N1134/gateop_perm;gopLUT5
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -200786,23 +200755,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_addr[0]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/coms2_reg_config/N1134_1/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/u1/N195_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -200812,23 +200775,17 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/reg_conf_done_reg/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/coms2_reg_config/N1193_3/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/N1169/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -200838,7 +200795,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/u1/cyc_count[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_ov5640/coms2_reg_config/reg_conf_done_reg/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -201036,14 +200993,20 @@ D;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_30/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/start/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/coms2_reg_config/reg_data/iGopDrm;gopDRM
@@ -201285,20 +201248,14 @@ WR_EOP;1
WR_ERR;1
Inst
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[1]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/coms2_reg_config/u1/N267_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21;gopA2Q2
@@ -201409,7 +201366,7 @@ I14;1
RS;1
Inst
-u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm;gopL5Q
+u_ov5640/coms2_reg_config/u1/tr_end/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -201425,7 +201382,7 @@ L4;1
RS;1
Inst
-u_ov5640/coms2_reg_config/u1/N187_3/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/u1/N25[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -201435,23 +201392,17 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/start/opit_0_inv_L5Q_perm;gopL5Q
+u_ov5640/coms2_reg_config/u1/N195_inv/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/coms2_reg_config/u1/N256_2_3/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/u1/N146_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -201461,7 +201412,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/u1/N267_21/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -201471,7 +201422,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/u1/N195_1/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/u1/N256_2_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -201481,7 +201432,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/u1/N262_46_3/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/u1/N256_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -201491,7 +201442,39 @@ L3;1
L4;1
Inst
-u_ov5640/power_on_delay_inst/cnt2[0]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/coms2_reg_config/u1/N256_1_3/gateop;gopMUX4TO1
+Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+u_ov5640/coms2_reg_config/u1/N262_47/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_ov5640/coms2_reg_config/u1/N256_3/gateop;gopMUX4TO1
+Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -201507,38 +201490,49 @@ L4;1
RS;1
Inst
-u_ov5640/coms2_reg_config/u1/N256_9/gateop_perm;gopLUT5
+u_axi_ddr_top/cnt0_times[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/coms2_reg_config/N1169/gateop_perm;gopLUT5
+u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/coms2_reg_config/u1/N262_46_2/gateop;gopMUX4TO1
+u_ov5640/coms2_reg_config/u1/N267_9/gateop_perm;gopLUT5
Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_ov5640/coms2_reg_config/N26_mux2/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/N1193_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -201548,42 +201542,29 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/u1/N267_18_muxf7;gopMUX16TO1
+u_ov5640/coms2_reg_config/u1/N267_13/gateop;gopMUX4TO1
Pin
F;2
-Fother;2
-L6OUTA;2
-L6OUTB;2
I0;1
I1;1
I2;1
I3;1
-I4;1
-I5;1
-I6;1
-I7;1
-I8;1
-I9;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-I15;1
-S3;1
-S00;1
-S01;1
-S02;1
-S03;1
-S10;1
-S11;1
-S12;1
-S13;1
-S20;1
-S21;1
+S0;1
+S1;1
Inst
-u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/u1/N267_16/gateop;gopMUX4TO1
+Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+u_ov5640/coms2_reg_config/N1134_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -201615,7 +201596,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N581_21/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/u1/N256_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -201625,34 +201606,34 @@ L3;1
L4;1
Inst
-u_ov5640/coms2_reg_config/u1/N267_36/gateop;gopMUX4TO1
+u_ov5640/coms2_reg_config/u1/N267_37_muxf6;gopMUX8TO1
Pin
F;2
+Y0;2
+Y1;2
I0;1
I1;1
I2;1
I3;1
-S0;1
-S1;1
+I4;1
+I5;1
+I6;1
+I7;1
+S2;1
+S00;1
+S01;1
+S10;1
+S11;1
Inst
-u_ov5640/coms2_reg_config/u1/cyc_count[5]/opit_0_inv_AQ_perm;gopAQ
+u_axi_ddr_top/N733_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_ov5640/coms2_reg_config/u1/cyc_count[2]/opit_0_inv_A2Q21;gopA2Q2
@@ -201709,40 +201690,26 @@ I14;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q
+u_ov5640/coms2_reg_config/u1/cyc_count[5]/opit_0_inv_AQ;gopAQ
Pin
CEOUT;2
-F;2
+Cout;2
Q;2
RSOUT;2
+Y;2
CE;1
CLK;1
+Cin;1
I0;1
+I0X;1
I1;1
I2;1
I3;1
+I4;1
RS;1
-S0;1
-S1;1
Inst
-u_ov5640/coms2_reg_config/u1/tr_end/opit_0_inv_L5Q_perm;gopL5Q
+u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -201758,7 +201725,17 @@ L4;1
RS;1
Inst
-u_ov5640/coms2_reg_config/u1/N185/gateop_perm;gopLUT5
+u_ov5640/coms2_reg_config/N1134/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -201804,7 +201781,7 @@ L4;1
RS;1
Inst
-u_ov5640/power_on_delay_inst/camera_pwnd_reg/opit_0_L5Q_perm;gopL5Q
+u_ov5640/power_on_delay_inst/cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -201820,17 +201797,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_or[0][0]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/power_on_delay_inst/cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/rd1_done_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -201846,14 +201829,20 @@ L4;1
RS;1
Inst
-u_ov5640/power_on_delay_inst/N15_mux15_12/gateop_perm;gopLUT5
+u_ov5640/power_on_delay_inst/camera_pwnd_reg/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/power_on_delay_inst/cnt1[2]/opit_0_inv_A2Q21;gopA2Q2
@@ -202099,7 +202088,7 @@ I14;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_2/gateop_perm;gopLUT5
+u_ov5640/power_on_delay_inst/N15_mux15_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202333,7 +202322,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/N315_9/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N315_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202343,7 +202332,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/N311_9/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202353,14 +202342,20 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_11/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/u_mix_image/image2_en/opit_0_L5Q_perm;gopL5Q
@@ -202379,7 +202374,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/N82/gateop;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202389,33 +202384,33 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/N329_17/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/rd_h[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/rd_w[0]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/N123_17/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/rd_h[0]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/rd_sta_reg[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -202531,20 +202526,14 @@ I13;1
I14;1
Inst
-u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/N1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/N311_11/gateop_perm;gopLUT5
@@ -202557,23 +202546,17 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm;gopL5Q
+N119_mux11_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/N315_11/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N78_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202583,7 +202566,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N315_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202593,17 +202576,23 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/N78_4/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/cnt1_w[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N329_16/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202613,27 +202602,39 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/N329_18/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/data_out1[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/N365_8/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/rd_w[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/N339_11/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N339_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202643,23 +202644,17 @@ L3;1
L4;1
Inst
-vs_pos_delay_cnt[1]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/N339_11/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/N123_7/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N329_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202669,7 +202664,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[7]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N365_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202679,7 +202674,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/N427/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N367_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202689,17 +202684,23 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[0]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/data_out_valid0/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/N123_6/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N329_17/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202709,7 +202710,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/N329_4/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N339_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202719,7 +202720,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/N315_8/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202729,7 +202730,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/N64_4/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N311_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -202888,36 +202889,24 @@ I14;1
RS;1
Inst
-u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/N31/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q;gopL5Q
@@ -203085,36 +203074,14 @@ I14;1
RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_ov5640/u_mix_image/data_out1[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/data_out1[4]/opit_0_L5Q_perm;gopL5Q
@@ -203133,23 +203100,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/data_out1[3]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-u_ov5640/u_mix_image/data_out1[9]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/data_out1[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203165,7 +203116,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/data_out1[13]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/data_out1[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203181,7 +203132,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/data_out1[6]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/data_out1[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203213,7 +203164,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/data_out1[14]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203245,7 +203196,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/data_out1[12]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/data_out1[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203261,7 +203212,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/data_out1[11]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203277,7 +203228,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/data_out1[15]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/data_out1[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203293,7 +203244,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/data_out1[8]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/data_out1[15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203309,7 +203260,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/data_out1[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203325,27 +203276,39 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/N34_mux3_3/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/data_out1[13]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/N365_1/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/data_out1[14]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N365_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -203355,18 +203318,33 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/data_out_valid1/opit_0;gopQ
+u_ov5640/u_mix_image/data_out1[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
RSOUT;2
+Z;2
CE;1
CLK;1
-D;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
-u_ov5640/u_mix_image/data_vs/opit_0;gopQ
+u_ov5640/u_mix_image/N123_14/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_ov5640/u_mix_image/data_out_valid1/opit_0;gopQ
Pin
CEOUT;2
Q;2
@@ -203377,26 +203355,18 @@ D;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_AQ_perm;gopAQ
+u_ov5640/u_mix_image/data_vs/opit_0;gopQ
Pin
CEOUT;2
-Cout;2
Q;2
RSOUT;2
-Y;2
CE;1
CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+D;1
RS;1
Inst
-u_ov5640/u_mix_image/N31/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -203406,7 +203376,17 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/N315_9/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_ov5640/u_mix_image/data_out1[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203612,14 +203592,20 @@ D;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_3/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/rd_w[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/u_mix_image/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
@@ -203654,7 +203640,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/rd_sta_reg[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203670,17 +203656,23 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[8]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-N104_mux11_11/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -203723,14 +203715,20 @@ D;1
RS;1
Inst
-u_ov5640/u_mix_image/N123_9/gateop_perm;gopLUT5
+vs_down_delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/u_mix_image/rd_w[5]/opit_0_L5Q_perm;gopL5Q
@@ -203797,14 +203795,20 @@ L4;1
RS;1
Inst
-u_ddr_addr_ctr/u_rd3_addr_ctr/N44_mux4/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/rd_w[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/u_mix_image/rd_w[6]/opit_0_L5Q_perm;gopL5Q
@@ -203823,7 +203827,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -203887,7 +203891,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/N367_3/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N123_15/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -203923,7 +203927,7 @@ I14;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -204109,20 +204113,14 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
@@ -204141,50 +204139,62 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[4]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[6]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_5/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
@@ -204235,20 +204245,14 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0;gopQ
@@ -204526,14 +204530,36 @@ I4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
@@ -204546,7 +204572,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -204562,7 +204588,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -204578,7 +204604,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -204594,7 +204620,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -204604,7 +204630,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -204620,33 +204646,14 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
@@ -204665,7 +204672,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_1/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -204796,7 +204803,7 @@ D;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/N68/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -204806,7 +204813,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -204816,23 +204823,17 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[3]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_15/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -204842,7 +204843,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -204852,7 +204853,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/N339_8/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_15/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -204862,33 +204863,33 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/N68/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/rd_w[1]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -204898,23 +204899,17 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/N417/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -204924,7 +204919,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_1/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -204934,7 +204929,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_9/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_17/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -204944,17 +204939,23 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_17/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/rd_vs_rise/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -204970,7 +204971,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[1]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -205000,7 +205001,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[9]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -205010,7 +205011,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[5]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -205020,7 +205021,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -205036,7 +205037,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[7]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -205046,33 +205047,33 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_7/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[2]/gateop_perm;gopLUT5
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -205082,23 +205083,17 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/rd_w[7]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/data_out_valid0/opit_0_inv_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -205114,23 +205109,17 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd1_addr_ctr/N56/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/rd_sta_fsm[4:0]_5/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -205140,20 +205129,14 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_0/gateop_A2;gopA2
@@ -205196,20 +205179,14 @@ I13;1
I14;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N160.eq_0/gateop_A2;gopA2
@@ -205759,20 +205736,14 @@ I14;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -205910,14 +205881,23 @@ I14;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[6]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/opit_0_inv_AQ;gopAQ
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q
@@ -205952,20 +205932,14 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
@@ -206000,7 +205974,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[5]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206026,27 +206000,39 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[8]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[9]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -206062,20 +206048,14 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/data_out1[5]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0;gopQ
@@ -206334,7 +206314,7 @@ I14;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_5/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206344,14 +206324,20 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
@@ -206370,7 +206356,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[3]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206396,33 +206382,33 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[4]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206432,30 +206418,30 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
@@ -206474,14 +206460,17 @@ L4;1
RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0;gopQ
@@ -206605,7 +206594,7 @@ D;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[3]_1/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206634,6 +206623,68 @@ L2;1
L3;1
L4;1
+Inst
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[4]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[5]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_ov5640/u_mix_image/N82/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
Inst
u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N39_7/gateop_perm;gopLUT5
Pin
@@ -206645,17 +206696,23 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_1/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206681,27 +206738,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_7/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-image_filiter_inst/multiline_buffer_inst/N93_mux7_12/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206711,7 +206748,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -206727,7 +206764,7 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -206742,26 +206779,6 @@ L3;1
L4;1
RS;1
-Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_3/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/gateop_perm;gopA
Pin
@@ -206776,17 +206793,7 @@ I3;1
I4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[1]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_ov5640/u_mix_image/data_out1[2]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -206802,23 +206809,17 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_9/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206828,7 +206829,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206838,26 +206839,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/opit_0_inv_AQ_perm;gopAQ
-Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
-
-Inst
-u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -206873,23 +206855,17 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/data_out1[0]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_7/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206899,7 +206875,7 @@ L3;1
L4;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_3/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206909,7 +206885,7 @@ L3;1
L4;1
Inst
-u_hdmi_in_top/N3/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -206919,7 +206895,7 @@ L3;1
L4;1
Inst
-u_hdmi_in_top/hs_cnt[0]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -206935,39 +206911,37 @@ L4;1
RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_11/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
+u_ov5640/u_mix_image/N64_4/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -207023,14 +206997,20 @@ I13;1
I14;1
Inst
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N160.eq_0/gateop_A2;gopA2
@@ -207554,23 +207534,17 @@ WR_EOP;1
WR_ERR;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/N44_mux7_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/N574_9[4]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -207580,7 +207554,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N924_10/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -207590,17 +207564,23 @@ L3;1
L4;1
Inst
-u_rotate_image/N52_mux10_3/gateop_perm;gopLUT5
+rstn_5s/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_rotate_image/N57_mux4_3/gateop_perm;gopLUT5
+u_rotate_image/N344_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -207610,7 +207590,7 @@ L3;1
L4;1
Inst
-u_rotate_image/N296_8/gateop_perm;gopLUT5
+u_rotate_image/N344_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -207620,7 +207600,7 @@ L3;1
L4;1
Inst
-u_rotate_image/N296_7/gateop_perm;gopLUT5
+u_rotate_image/N57_mux6_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -207640,20 +207620,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_rotate_image/image_w_blank_valid/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/cnt_w[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -207668,6 +207635,16 @@ L3;1
L4;1
RS;1
+Inst
+u_hdm_in_rst/N0/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_rotate_image/N131_mux9_6/gateop_perm;gopLUT5
Pin
@@ -207679,7 +207656,7 @@ L3;1
L4;1
Inst
-image_filiter_inst2/hybrid_filter_inst/N118_mux3_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N186/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -207689,39 +207666,27 @@ L3;1
L4;1
Inst
-param_manager_inst/param_offsetY/value[0]/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/N39_0_ac4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_rst/rst/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/N144_mux13_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_sync_vg/vs_out0/opit_0_L5Q_perm;gopL5Q
+image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -207737,23 +207702,17 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/N344_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_rotate_image/N296_9/gateop_perm;gopLUT5
+u_rotate_image/N350/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -207763,17 +207722,23 @@ L3;1
L4;1
Inst
-u_rotate_image/N302/gateop_perm;gopLUT5
+clk_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_char_height/N63_mux10_6/gateop_perm;gopLUT5
+u_rotate_image/N52_mux10_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -208129,17 +208094,14 @@ I4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N107.lt_2/gateop_perm;gopA
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_18/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_rotate_image/cnt_h[2]/opit_0_A2Q21;gopA2Q2
@@ -208277,7 +208239,7 @@ I14;1
RS;1
Inst
-param_manager_inst/param_offsetX/N76_mux4_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_18/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -208598,7 +208560,7 @@ D;1
RS;1
Inst
-u_rotate_image/data_out_valid2/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/fifo_data_valid/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -208614,7 +208576,7 @@ L4;1
RS;1
Inst
-u_rotate_image/fifo_data_valid/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -208833,20 +208795,14 @@ L4;1
RS;1
Inst
-u_axi_ddr_top/rd0_cnt_num[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/N182_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_rotate_image/image_h_add0[7]/opit_0_A2Q1;gopA2Q1
@@ -209492,7 +209448,7 @@ D;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N23_mux3_4/gateop_perm;gopLUT5
+u_rotate_image/N144_mux13_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -210145,7 +210101,7 @@ D;1
RS;1
Inst
-u_rotate_image/N131_mux9_5/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/N76_mux4_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -210562,20 +210518,14 @@ D;1
RS;1
Inst
-u_axi_ddr_top/rd0_time_permit/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N19_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_rotate_image/rd_sta_reg[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -210612,7 +210562,7 @@ S0;1
S1;1
Inst
-u_axi_ddr_top/N743_8/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -210622,7 +210572,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -210632,63 +210582,72 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA
+u_rotate_image/rotate_sta_fsm[2:0]_9_2/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_rotate_image/rotate_sta_fsm[2:0]_1/gateop_perm;gopLUT5
+u_rotate_image/rotate_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5
+u_rotate_image/rotate_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/N85.lt_2/gateop_perm;gopA
+u_rotate_image/rotate_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA
+u_rotate_image/N52_mux6_7/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_rotate_image/u_rotate_mult0/N2/gopapm;gopAPM
@@ -212803,7 +212762,7 @@ WEA;1
WEB;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212813,7 +212772,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212823,7 +212782,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212833,7 +212792,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212843,7 +212802,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212853,23 +212812,17 @@ L3;1
L4;1
Inst
-u_rotate_image/rd_ddr_addr_valid1/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212879,7 +212832,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N267_or[0]_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212899,7 +212852,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212909,7 +212862,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212919,7 +212872,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/N28/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212929,7 +212882,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212939,7 +212892,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212949,7 +212902,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212959,7 +212912,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212979,7 +212932,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212989,7 +212942,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_rotate_image/N44_mux7_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -212999,14 +212952,20 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
@@ -213029,30 +212988,30 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/N928_7/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/cnt1_times[0]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2;gopA2
@@ -213812,7 +213771,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -213822,7 +213781,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -213832,20 +213791,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -213855,23 +213801,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -213881,7 +213821,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -213891,17 +213831,23 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -213911,7 +213857,7 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_en/opit_0_inv_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -213927,7 +213873,7 @@ L4;1
RS;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N25_mux5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -213937,7 +213883,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[0]/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -213947,7 +213893,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -213957,7 +213903,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -213973,7 +213929,7 @@ L4;1
RS;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -213983,7 +213939,7 @@ L3;1
L4;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -213993,20 +213949,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N161.eq_4/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -214022,7 +213975,7 @@ L4;1
RS;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214032,23 +213985,17 @@ L3;1
L4;1
Inst
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -214284,17 +214231,14 @@ I14;1
RS;1
Inst
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_2/gateop_perm;gopA
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21;gopA2Q2
@@ -214690,7 +214634,7 @@ WR_EOP;1
WR_ERR;1
Inst
-u_sync_vg/N56_mux5_2/gateop_perm;gopLUT5
+u_sync_vg/N3_mux10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214700,7 +214644,7 @@ L3;1
L4;1
Inst
-u_sync_vg/N178_6/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux7_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214750,27 +214694,36 @@ I13;1
I14;1
Inst
-u_sync_vg/N54/gateop_perm;gopLUT5
+u_sync_vg/N23_1_9/gateop;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_sync_vg/N56_mux8_1/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_sync_vg/N56_mux6/gateop_perm;gopLUT5
+u_sync_vg/N50_mux2_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214780,7 +214733,7 @@ L3;1
L4;1
Inst
-u_sync_vg/v_count[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -214796,17 +214749,7 @@ L4;1
RS;1
Inst
-u_sync_vg/N28_mux8_2/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_sync_vg/N50_mux4/gateop_perm;gopLUT5
+u_sync_vg/N50_mux3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214816,7 +214759,7 @@ L3;1
L4;1
Inst
-u_sync_vg/N50_mux9_7/gateop_perm;gopLUT5
+u_sync_vg/N56_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214826,7 +214769,7 @@ L3;1
L4;1
Inst
-u_sync_vg/N50_mux2_3/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N137/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214836,7 +214779,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm;gopLUT5
+u_sync_vg/N54/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214846,7 +214789,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/init_over/opit_0_inv_L5Q_perm;gopL5Q
+u_sync_vg/pos_y[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -214862,7 +214805,7 @@ L4;1
RS;1
Inst
-u_sync_vg/h_count[11:0]_or/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214872,23 +214815,17 @@ L3;1
L4;1
Inst
-u_sync_vg/hs_out0/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/N178_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_sync_vg/N3_mux10/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N23_mux3_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214898,7 +214835,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N524_1/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N23_mux7_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214908,34 +214845,65 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[6]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_sync_vg/N145_5/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_posX[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_sync_vg/N3_mux6_4/gateop_perm;gopLUT5
+u_sync_vg/v_count[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
+
+Inst
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N522_11/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
u_sync_vg/N178_7/gateop_perm;gopLUT5
@@ -214948,17 +214916,23 @@ L3;1
L4;1
Inst
-u_sync_vg/N178_9/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/row_cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_rotate/N63_mux7_7/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/s_ready_d_d[0]_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -214968,17 +214942,23 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7210_ctl/N36/gateop_perm;gopLUT5
+u_sync_vg/vs_out0/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/ms7210_ctl/N559_6/gateop_perm;gopLUT5
+udp_osd_inst/N69_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -215038,20 +215018,14 @@ D;1
RS;1
Inst
-param_manager_inst/param_rotate/value[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_sync_vg/h_count[2]/opit_0_A2Q21;gopA2Q2
@@ -215189,14 +215163,23 @@ I14;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux7_7/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_posX[10]/opit_0_AQ_perm;gopAQ
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
Inst
u_sync_vg/h_count[11]/opit_0_AQ;gopAQ
@@ -215218,7 +215201,7 @@ I4;1
RS;1
Inst
-u_sync_vg/hdmi_image_data0[5]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215234,7 +215217,7 @@ L4;1
RS;1
Inst
-u_sync_vg/hdmi_image_data0[4]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215250,7 +215233,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215266,7 +215249,7 @@ L4;1
RS;1
Inst
-u_sync_vg/hdmi_image_data0[7]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215282,7 +215265,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215298,7 +215281,7 @@ L4;1
RS;1
Inst
-u_sync_vg/hdmi_image_data0[12]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215314,23 +215297,17 @@ L4;1
RS;1
Inst
-u_sync_vg/hdmi_image_data0[8]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_18/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_sync_vg/hdmi_image_data0[2]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215346,7 +215323,7 @@ L4;1
RS;1
Inst
-u_sync_vg/hdmi_image_data0[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215362,7 +215339,7 @@ L4;1
RS;1
Inst
-u_sync_vg/hdmi_image_data0[6]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215378,23 +215355,17 @@ L4;1
RS;1
Inst
-u_sync_vg/hdmi_image_data0[14]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_29/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_sync_vg/hdmi_image_data0[15]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215410,7 +215381,7 @@ L4;1
RS;1
Inst
-param_manager_inst/key_debounce_key_right/cnt[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215426,7 +215397,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/addr_bus_rd_ce[0]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215442,7 +215413,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215458,7 +215429,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -215650,20 +215621,14 @@ D;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/addr[6]/opit_0_inv_L5Q_perm;gopL5Q
+u_sync_vg/N178_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_sync_vg/hs_out1/opit_0;gopQ
@@ -215710,20 +215675,14 @@ D;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[12]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_sync_vg/pos_x[0]/opit_0;gopQ
@@ -215759,20 +215718,14 @@ D;1
RS;1
Inst
-param_manager_inst/rotate_load/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/N3_mux6_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_sync_vg/pos_x[5]/opit_0_A2Q21;gopA2Q2
@@ -215875,7 +215828,7 @@ I4;1
RS;1
Inst
-u_sync_vg/pos_y[0]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -216053,7 +216006,7 @@ L4;1
RS;1
Inst
-u_sync_vg/v_count[7]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/v_count[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -216069,7 +216022,7 @@ L4;1
RS;1
Inst
-u_sync_vg/v_count[5]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/v_count[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -216127,30 +216080,30 @@ L4;1
RS;1
Inst
-u_rotate_image/N144_mux13_7/gateop_perm;gopLUT5
+u_sync_vg/v_count[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_sync_vg/v_count[9]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/N50_mux9_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_sync_vg/v_count[8]/opit_0_A2Q1;gopA2Q1
@@ -216179,7 +216132,7 @@ I14;1
RS;1
Inst
-u_sync_vg/v_count[1]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/v_count[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -216195,14 +216148,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/N69_5/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_sync_vg/vs_out1/opit_0;gopQ
@@ -216437,25 +216396,19 @@ I14;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/opit_0_L6Q_perm;gopL6Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
RSOUT;2
Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
CE;1
CLK;1
-M;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
@@ -216675,14 +216628,20 @@ I14;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
@@ -216701,7 +216660,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -216717,14 +216676,20 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_30/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[13]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
@@ -216743,17 +216708,23 @@ L4;1
RS;1
Inst
-param_manager_inst/key_debounce_key_right/N20_mux4_1/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -216769,7 +216740,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -216785,7 +216756,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_22/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -216811,7 +216782,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[14]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -216827,7 +216798,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[12]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -216843,30 +216814,30 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[13]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[14]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[12]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[14]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[15]/opit_0_L5Q_perm;gopL5Q
@@ -216885,7 +216856,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217287,7 +217258,7 @@ I14;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -217303,7 +217274,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -217319,14 +217290,20 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
@@ -217345,7 +217322,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -217377,7 +217354,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[7]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217403,14 +217380,20 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
@@ -217445,14 +217428,20 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_7/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[12]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[13]/opit_0_L5Q_perm;gopL5Q
@@ -217487,36 +217476,24 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[15]/opit_0_L5Q_perm;gopL5Q
+N286_11/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0;gopQ
@@ -217695,7 +217672,23 @@ D;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217715,7 +217708,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217725,7 +217718,17 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+zoom_fifo_full/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -217741,7 +217744,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[2]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217751,7 +217754,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217761,7 +217764,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217771,7 +217774,7 @@ L3;1
L4;1
Inst
-u_zoom_image/data_out_valid1/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -217787,7 +217790,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217797,23 +217800,27 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[14]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -217829,20 +217836,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_13/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[12]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/N6_mux7_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217852,7 +217846,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[14]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217862,23 +217856,17 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[12]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_26/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217888,7 +217876,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_18/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217898,7 +217886,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_32/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217908,7 +217896,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_26/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[13]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217918,23 +217906,17 @@ L3;1
L4;1
Inst
-zoom_fifo_full/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[12]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[10]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217944,7 +217926,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[5]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_30/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217954,7 +217936,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_24/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_28/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217964,7 +217946,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[0]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -217974,23 +217956,17 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_32/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_29/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_24/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -218000,7 +217976,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_28/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -218010,51 +217986,27 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/opit_0_L6Q_perm;gopL6Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
-CE;1
-CLK;1
-M;1
-RS;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_L6Q_perm;gopL6Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
-CE;1
-CLK;1
-M;1
-RS;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_9/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -218064,33 +218016,33 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_right/change/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[4]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[1]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[3]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -218100,7 +218052,7 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -218110,17 +218062,23 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[4]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -218130,17 +218088,23 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[11]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -218156,7 +218120,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -218182,75 +218146,26 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm;gopL6Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
-CE;1
-CLK;1
-M;1
-RS;1
-
-Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/opit_0_AQ_perm;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[13]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[14]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_4/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_16/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -218260,17 +218175,23 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[13]/gateop_perm;gopLUT5
+u_sync_vg/hdmi_image_data0[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_2/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -218280,24 +218201,36 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/N20_mux2/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_14/gateop_perm;gopLUT5
+u_sync_vg/pixel_show_en1/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_20/gateop_perm;gopLUT5
@@ -218310,7 +218243,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -218326,7 +218259,7 @@ L4;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_22/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_25/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -218336,24 +218269,36 @@ L3;1
L4;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[8]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_16/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[12]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_0/gateop_A2;gopA2
@@ -218535,108 +218480,6 @@ I12;1
I13;1
I14;1
-Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/gateop_A2;gopA2
-Pin
-Cout;2
-Y0;2
-Y1;2
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-
-Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/gateop_A2;gopA2
-Pin
-Cout;2
-Y0;2
-Y1;2
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-
-Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/gateop_A2;gopA2
-Pin
-Cout;2
-Y0;2
-Y1;2
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-
-Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/gateop_A2;gopA2
-Pin
-Cout;2
-Y0;2
-Y1;2
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-
-Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/opit_0_L6Q_perm;gopL6Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
-CE;1
-CLK;1
-M;1
-RS;1
-
Inst
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0;gopQ
Pin
@@ -218814,120 +218657,127 @@ D;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_L6Q_perm;gopL6Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q1;gopA2Q1
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
+Y0;2
+Y1;2
CE;1
CLK;1
-M;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
RS;1
Inst
-param_manager_inst/key_debounce_key_restore/N88/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_27/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/opit_0_L6Q;gopL6Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21;gopA2Q2
Pin
CEOUT;2
-Q;2
+Cout;2
+Q0;2
+Q1;2
RSOUT;2
-Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
+Y0;2
+Y1;2
CE;1
CLK;1
-M;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_L6Q_perm;gopL6Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21;gopA2Q2
Pin
CEOUT;2
-Q;2
+Cout;2
+Q0;2
+Q1;2
RSOUT;2
-Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
+Y0;2
+Y1;2
CE;1
CLK;1
-M;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21;gopA2Q2
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0;gopQ
@@ -226754,20 +226604,14 @@ WR_EOP;1
WR_ERR;1
Inst
-u_sync_vg/hdmi_image_data0[9]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[13]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_zoom_image/N78_1_1/gateop_A2;gopA2
@@ -226890,23 +226734,17 @@ I13;1
I14;1
Inst
-u_zoom_image/delay_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_zoom_image/N131_mux8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_image/N143_5/gateop_perm;gopLUT5
+u_zoom_image/N857_8[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -226916,7 +226754,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N731/gateop_perm;gopLUT5
+u_zoom_image/N135_mux9_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -226926,7 +226764,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N368_mux4/gateop_perm;gopLUT5
+u_zoom_image/N131_mux12_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -226936,7 +226774,7 @@ L3;1
L4;1
Inst
-u_zoom_image/zoom_sta_fsm[6:0]_35_2/gateop_perm;gopLUT5
+u_zoom_image/N143_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -226946,7 +226784,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N131_mux4_3/gateop_perm;gopLUT5
+u_zoom_image/zoom_sta_fsm[6:0]_61/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -226956,17 +226794,23 @@ L3;1
L4;1
Inst
-u_zoom_image/N204_1_sum1_7/gateop_perm;gopLUT5
+u_zoom_image/ram_ch[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/N368_mux9_4/gateop_perm;gopLUT5
+u_zoom_image/N198/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -226976,23 +226820,17 @@ L3;1
L4;1
Inst
-u_zoom_image/no_need_rd_ddr/opit_0_inv_L5Q_perm;gopL5Q
+u_zoom_image/N227_2_ab0/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_image/record_ram_valid/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/cnt_record_ram[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -227008,20 +226846,14 @@ L4;1
RS;1
Inst
-u_zoom_image/cnt_record_ram[0]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/ram_sta_fsm[3:0]_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_zoom_image/N227_2_sum2_4/gateop;gopMUX4TO1
@@ -227035,7 +226867,7 @@ S0;1
S1;1
Inst
-u_zoom_image/N891/gateop_perm;gopLUT5
+u_zoom_image/N274_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -227045,7 +226877,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N238_0/gateop_perm;gopLUT5
+u_zoom_image/N290_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -227055,7 +226887,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[20]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/cnt_w[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -227071,14 +226903,20 @@ L4;1
RS;1
Inst
-u_zoom_image/N274_12/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[17]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_image/N244_1_1/gateop_A2;gopA2
@@ -227181,7 +227019,7 @@ I13;1
I14;1
Inst
-u_zoom_image/wr_addr3[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_zoom_image/rd_addr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -227197,17 +227035,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N961/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/ram_sta_fsm[3:0]_4/gateop_perm;gopLUT5
+u_zoom_image/ram_sta_fsm[3:0]_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -227217,7 +227061,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[1]/gateop_perm;gopLUT5
+u_zoom_image/N290_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -227227,17 +227071,23 @@ L3;1
L4;1
Inst
-u_zoom_image/N290_10/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/value[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/ram_sta_fsm[3:0]_7/gateop_perm;gopLUT5
+u_zoom_image/N290_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -227247,17 +227097,23 @@ L3;1
L4;1
Inst
-u_zoom_image/N306_11/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -227273,7 +227129,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N78/gateop_perm;gopLUT5
+u_zoom_image/N306_12/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -227283,7 +227139,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N322_12/gateop_perm;gopLUT5
+udp_wr_mem_inst/N549_25/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -227293,27 +227149,30 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N328_1.fsub_15/gateop_perm;gopA
+u_zoom_image/N322_12/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-u_zoom_image/N322_11/gateop_perm;gopLUT5
+udp_wr_mem_inst/data_count[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_image/N361_1_1/gateop_A2;gopA2
@@ -227449,7 +227308,7 @@ I3;1
I4;1
Inst
-u_zoom_image/N131_mux12_5/gateop_perm;gopLUT5
+u_zoom_image/N370/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -227459,30 +227318,27 @@ L3;1
L4;1
Inst
-u_zoom_image/N370/gateop_perm;gopLUT5
+u_zoom_image/N375.eq_6/gateop_perm;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_zoom_image/addr_sta_reg[4]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N368_mux9_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_zoom_image/N375.eq_0/gateop_A2;gopA2
@@ -227545,20 +227401,14 @@ I13;1
I14;1
Inst
-u_zoom_image/imag_addr0[6]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N204_1_sum1_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_zoom_image/N383.eq_0/gateop_A2;gopA2
@@ -227621,17 +227471,20 @@ I13;1
I14;1
Inst
-u_zoom_image/N383.eq_6/gateop;gopA
+u_zoom_image/no_need_rd_ddr/opit_0_inv_L5Q_perm;gopL5Q
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
u_zoom_image/N387_2_1/gateop_A2;gopA2
@@ -227727,17 +227580,23 @@ I3;1
I4;1
Inst
-u_zoom_image/N322_9/gateop_perm;gopLUT5
+u_zoom_image/image_w_valid[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/N530_mux7_3/gateop_perm;gopLUT5
+u_zoom_image/N530_mux12_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -227747,30 +227606,30 @@ L3;1
L4;1
Inst
-u_zoom_image/N530_mux12_3/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/rd_addr[0]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N709_11/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_zoom_image/N566_1.fsub_1/gateop_A2;gopA2
@@ -228099,7 +227958,7 @@ I13;1
I14;1
Inst
-u_zoom_image/cnt_w[1]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228115,33 +227974,33 @@ L4;1
RS;1
Inst
-u_zoom_image/N709_11/gateop_perm;gopLUT5
+u_zoom_image/image_valid[0][0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/cnt_h[2]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N843/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_image/N857_8[3]/gateop_perm;gopLUT5
+u_zoom_image/N857_8[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228151,7 +228010,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N857_8[7]/gateop_perm;gopLUT5
+u_zoom_image/N857_8[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228161,7 +228020,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N857_8[6]/gateop_perm;gopLUT5
+u_zoom_image/N857_8[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228171,7 +228030,7 @@ L3;1
L4;1
Inst
-u_zoom_image/ram_ch[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_zoom_image/delay_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228187,17 +228046,23 @@ L4;1
RS;1
Inst
-u_zoom_image/zoom_sta_fsm[6:0]_9/gateop_perm;gopLUT5
+u_zoom_image/image_h_valid[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/zoom_sta_reg[3]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/zoom_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228213,7 +228078,7 @@ L4;1
RS;1
Inst
-u_zoom_image/N857_8[2]/gateop_perm;gopLUT5
+u_zoom_image/N135_mux4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228223,7 +228088,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N715_10/gateop_perm;gopLUT5
+u_zoom_image/N857_8[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228233,7 +228098,7 @@ L3;1
L4;1
Inst
-u_zoom_image/coe_valid[0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228259,17 +228124,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/N89_5[2]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_zoom_image/image_h0[6]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/cnt_h[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228285,7 +228140,7 @@ L4;1
RS;1
Inst
-u_zoom_image/N857_8[8]/gateop_perm;gopLUT5
+u_zoom_image/N857_8[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228295,7 +228150,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N857_8[9]/gateop_perm;gopLUT5
+u_zoom_image/N715_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228305,7 +228160,7 @@ L3;1
L4;1
Inst
-u_zoom_image/zoom_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/cnt_h[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228321,7 +228176,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[2]/gateop_perm;gopLUT5
+u_zoom_image/N857_8[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228331,7 +228186,7 @@ L3;1
L4;1
Inst
-u_zoom_image/cnt_h[7]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/cnt_h[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228347,17 +228202,7 @@ L4;1
RS;1
Inst
-u_zoom_image/N843/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_zoom_image/wr_addr1[0]/opit_0_inv_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228373,7 +228218,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_34/gateop_perm;gopLUT5
+u_zoom_image/zoom_sta_fsm[6:0]_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228383,7 +228228,7 @@ L3;1
L4;1
Inst
-u_zoom_image/addr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/wr_addr0[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228399,7 +228244,7 @@ L4;1
RS;1
Inst
-u_zoom_image/addr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228415,7 +228260,7 @@ L4;1
RS;1
Inst
-u_zoom_image/addr_sta_reg[3]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/addr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228431,27 +228276,39 @@ L4;1
RS;1
Inst
-u_zoom_image/N198/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/N227_1_ab0/gateop_perm;gopLUT5
+u_zoom_image/addr_sta_reg[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/cnt_h[0]/opit_0_L5Q;gopL5Q
+u_zoom_image/addr_sta_reg[3]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228467,7 +228324,17 @@ L4;1
RS;1
Inst
-u_zoom_image/cnt_h[3]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N227_1_ab0/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_zoom_image/cnt_h[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228483,7 +228350,7 @@ L4;1
RS;1
Inst
-u_zoom_image/cnt_h[5]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/cnt_h[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228515,7 +228382,7 @@ L4;1
RS;1
Inst
-u_zoom_image/cnt_h[10]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/cnt_h[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228531,23 +228398,17 @@ L4;1
RS;1
Inst
-u_zoom_image/cnt_h[6]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N131_mux4_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_image/cnt_h[8]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/cnt_h[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228563,7 +228424,7 @@ L4;1
RS;1
Inst
-u_zoom_image/cnt_h[9]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/cnt_h[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228579,7 +228440,7 @@ L4;1
RS;1
Inst
-u_zoom_image/N274_9/gateop_perm;gopLUT5
+u_zoom_image/N715_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228589,7 +228450,7 @@ L3;1
L4;1
Inst
-u_zoom_image/image_h_valid[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_zoom_image/cnt_h[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -228604,6 +228465,16 @@ L3;1
L4;1
RS;1
+Inst
+u_zoom_image/N731/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
u_zoom_image/N857_8[10]/gateop_perm;gopLUT5
Pin
@@ -228647,7 +228518,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/gateop_perm;gopLUT5
+u_zoom_image/N891/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228657,33 +228528,33 @@ L3;1
L4;1
Inst
-u_zoom_image/cnt_w[2]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N709_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_image/N709_9/gateop_perm;gopLUT5
+u_zoom_image/cnt_w[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/N87/gateop_perm;gopLUT5
+u_zoom_image/N515_mux1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -228801,7 +228672,7 @@ I14;1
RS;1
Inst
-u_zoom_image/zoom_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/image_valid[0][1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -229389,7 +229260,7 @@ D;1
RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -229448,14 +229319,20 @@ L4;1
RS;1
Inst
-u_zoom_image/N135_mux4/gateop_perm;gopLUT5
+u_zoom_image/zoom_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_image/fifo_full0/opit_0;gopQ
@@ -229501,14 +229378,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N703_1/gateop_perm;gopLUT5
+u_zoom_image/imag_addr0[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_image/imag_addr0[4]/opit_0_L5Q_perm;gopL5Q
@@ -229527,7 +229410,7 @@ L4;1
RS;1
Inst
-u_zoom_image/imag_addr0[5]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/imag_addr0[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -229543,17 +229426,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[1]/gateop_perm;gopLUT5
+u_zoom_image/imag_addr0[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[0]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/addr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -229569,7 +229458,7 @@ L4;1
RS;1
Inst
-u_zoom_image/imag_addr0[8]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/imag_addr0[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -229601,14 +229490,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N357_4/gateop_perm;gopLUT5
+u_zoom_image/addr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_image/imag_addr1[0]/opit_0;gopQ
@@ -229644,7 +229539,7 @@ D;1
RS;1
Inst
-u_zoom_image/imag_addr_valid0/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/wr_addr1[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -229741,14 +229636,20 @@ I14;1
RS;1
Inst
-u_zoom_image/N919/gateop_perm;gopLUT5
+u_zoom_image/imag_addr_valid0/opit_0_L5Q;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_image/imag_addr_valid1/opit_0;gopQ
@@ -229828,7 +229729,7 @@ D;1
RS;1
Inst
-u_zoom_image/ram_idle/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/cnt_h[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -230800,7 +230701,7 @@ L4;1
RS;1
Inst
-u_zoom_image/image_w_valid[0]/opit_0_inv_L5Q_perm;gopL5Q
+u_zoom_image/cnt_w[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -230816,30 +230717,30 @@ L4;1
RS;1
Inst
-u_zoom_image/image_valid[0][1]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N709_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-u_zoom_image/N515_mux1/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_image/image_valid[1][0]/opit_0;gopQ
@@ -231653,7 +231554,7 @@ L4;1
RS;1
Inst
-u_zoom_image/image_valid[0][0]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -232886,7 +232787,7 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N282/gateop_perm;gopLUT5
+u_zoom_image/N857_8[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -236988,20 +236889,14 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_en/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N227_1_sum1_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_zoom_image/ram_ch0[0]/opit_0;gopQ
@@ -237086,20 +236981,14 @@ L4;1
RS;1
Inst
-u_zoom_image/addr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N858_inv/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_zoom_image/rd_one_ram/opit_0_L5Q_perm;gopL5Q
@@ -237140,7 +237029,7 @@ D;1
RS;1
Inst
-u_zoom_image/ram_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/ram_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -237156,7 +237045,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[2]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -237188,29 +237077,23 @@ L4;1
RS;1
Inst
-u_zoom_image/wr_ram_done/opit_0_L6Q_perm;gopL6Q
+u_zoom_image/wr_ram_done/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
RSOUT;2
Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
CE;1
CLK;1
-M;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
-u_zoom_image/ram_sta_reg[3]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/ram_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -237226,14 +237109,36 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[1]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_image/rd_addr0[0]/opit_0;gopQ
@@ -237346,7 +237251,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N831_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_66/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -237520,7 +237425,7 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux3/gateop_perm;gopLUT5
+u_zoom_image/N274_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -238618,17 +238523,23 @@ S0;1
S1;1
Inst
-u_zoom_image/N530_mux3_4/gateop_perm;gopLUT5
+u_zoom_image/record_ram_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/N290_9/gateop_perm;gopLUT5
+u_zoom_image/N850_inv/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -239502,23 +239413,14 @@ Z[46];1
Z[47];1
Inst
-u_zoom_image/mult_image2[1][12]/opit_0_AQ_perm;gopAQ
+u_zoom_image/N232_0/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
u_zoom_image/wr_addr0[2]/opit_0_A2Q21;gopA2Q2
@@ -239656,44 +239558,47 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_27/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21;gopA2Q2
+param_manager_inst/param_offsetX/N151_10_11/gateop_perm;gopA
Pin
-CEOUT;2
Cout;2
-Q0;2
-Q1;2
-RSOUT;2
-Y0;2
-Y1;2
-CE;1
-CLK;1
+Y;2
Cin;1
+I0;1
I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
-RS;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-u_zoom_image/wr_addr1[4]/opit_0_inv_A2Q21;gopA2Q2
+u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21;gopA2Q2
+Pin
+CEOUT;2
+Cout;2
+Q0;2
+Q1;2
+RSOUT;2
+Y0;2
+Y1;2
+CE;1
+CLK;1
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+RS;1
+
+Inst
+u_zoom_image/wr_addr1[4]/opit_0_inv_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -239801,14 +239706,20 @@ I14;1
RS;1
Inst
-u_ov5640/coms1_reg_config/u1/N256_2_4/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_image/wr_addr2[2]/opit_0_inv_A2Q21;gopA2Q2
@@ -239946,20 +239857,14 @@ I14;1
RS;1
Inst
-u_zoom_image/ram_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
u_zoom_image/wr_addr3[2]/opit_0_inv_A2Q21;gopA2Q2
@@ -240097,14 +240002,20 @@ I14;1
RS;1
Inst
-u_zoom_image/N274_11/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
u_zoom_image/zoom_num0[1]/opit_0;gopQ
@@ -244129,27 +244040,39 @@ WR_EOP;1
WR_ERR;1
Inst
-u_zoom_image/N715_11/gateop_perm;gopLUT5
+u_zoom_image/ram_idle/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/zoom_sta_fsm[6:0]_61/gateop_perm;gopLUT5
+u_zoom_image/coe_valid[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/N131_mux8/gateop_perm;gopLUT5
+u_zoom_image/zoom_sta_fsm[6:0]_35_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -244192,7 +244115,7 @@ D;1
RS;1
Inst
-u_zoom_image/zoom_sta_reg[1]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/zoom_sta_reg[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -244208,7 +244131,7 @@ L4;1
RS;1
Inst
-u_zoom_image/zoom_sta_reg[4]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/zoom_sta_reg[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -244224,17 +244147,23 @@ L4;1
RS;1
Inst
-u_zoom_image/N227_2_ab0/gateop_perm;gopLUT5
+u_zoom_image/zoom_sta_reg[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/zoom_sta_reg[5]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/zoom_sta_reg[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -244250,7 +244179,7 @@ L4;1
RS;1
Inst
-u_zoom_image/zoom_sta_reg[6]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/zoom_sta_reg[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -244266,7 +244195,7 @@ L4;1
RS;1
Inst
-u_zoom_image/N857_8[0]/gateop_perm;gopLUT5
+u_zoom_image/N274_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -244276,7 +244205,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N857_8[5]/gateop_perm;gopLUT5
+u_zoom_image/N236_0/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -244286,7 +244215,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N6/gateop_perm;gopLUT5
+u_hdmi_rst/N0/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -244498,23 +244427,17 @@ I13;1
I14;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux10/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -244764,17 +244687,14 @@ I13;1
I14;1
Inst
-udp_osd_inst/char_buf_writer_inst/N16.eq_8/gateop;gopA
+udp_osd_inst/char_buf_writer_inst/N138_24/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
udp_osd_inst/char_buf_writer_inst/N87_1_0/gateop_A2;gopA2
@@ -244877,17 +244797,23 @@ I13;1
I14;1
Inst
-udp_osd_inst/char_buf_writer_inst/N222/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/N138_20/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/N179_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -244907,7 +244833,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/N138_26/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/cnt[15:0]_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -244927,23 +244853,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/udp_rx_s_data_tready/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_24[0]_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/N230/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/N170/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -244953,17 +244873,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/N206_15/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N120_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N296_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -244973,7 +244899,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/N206_2/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/N206_15/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -244983,14 +244909,20 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/N179_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/char_buf_writer_inst/N206_14_4/gateop;gopMUX4TO1
@@ -245014,39 +244946,27 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_din[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N75_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_addr[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N590_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/state_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -245062,14 +244982,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N296_1/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/cnt[15]/opit_0_AQ_perm;gopAQ
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
Inst
udp_osd_inst/char_buf_writer_inst/ram_din[0]/opit_0_L5Q_perm;gopL5Q
@@ -245276,39 +245205,24 @@ I14;1
RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/cnt[15]/opit_0_AQ_perm;gopAQ
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N263/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_din[5]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N8_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/char_buf_writer_inst/data_size[0]/opit_0;gopQ
@@ -245487,7 +245401,7 @@ D;1
RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_addr[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/ram_addr[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -245535,7 +245449,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_addr[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/ram_addr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -245567,7 +245481,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_addr[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/ram_addr[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -245583,7 +245497,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_addr[7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/ram_addr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -245599,17 +245513,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/ram_addr[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_addr[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/ram_addr[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -245625,7 +245545,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_addr[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -245641,7 +245561,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N114_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N39_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -245651,7 +245571,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_din[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/ram_din[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -245699,7 +245619,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_din[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/N16.eq_8/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+udp_osd_inst/char_buf_writer_inst/ram_din[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -245715,27 +245648,23 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/N124_5/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_25/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/ram_din[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/ram_din[7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -245751,14 +245680,20 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/N62_sum3/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/ram_din[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/char_buf_writer_inst/ram_wen/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -245810,7 +245745,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/N206_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N148_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -245820,7 +245755,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_tx/busy/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/change_to_read/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -245836,7 +245771,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_and[10][0]/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -245926,14 +245861,20 @@ I13;1
I14;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_3/gateop_perm;gopLUT5
+u_sync_vg/hdmi_image_data0[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N72_1.fsub_1/gateop_A2;gopA2
@@ -246176,7 +246117,7 @@ I13;1
I14;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246186,7 +246127,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246196,20 +246137,14 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_valid/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N593/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N228_1_1/gateop_A2;gopA2
@@ -246392,7 +246327,7 @@ I13;1
I14;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/row_cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_valid/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -246408,23 +246343,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N102_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N709_1/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N589_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246534,7 +246463,7 @@ I13;1
I14;1
Inst
-param_manager_inst/param_osd_startX/value[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -246650,7 +246579,7 @@ I13;1
I14;1
Inst
-param_manager_inst/param_osd_startY/N148_5/gateop_perm;gopLUT5
+u_sync_vg/N56_mux5_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246660,7 +246589,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_7_or[1]_3/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246670,7 +246599,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N581_23/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N861/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246680,7 +246609,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N590_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246690,7 +246619,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246700,7 +246629,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N589_7/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N589_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246710,7 +246639,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N590_9/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N590_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246720,7 +246649,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N590_8/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_52/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246730,20 +246659,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N60.lt_6/gateop_perm;gopA
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N581_24/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N784_0/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/N11_mux6_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246753,7 +246679,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_13_2/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246763,7 +246689,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N832/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246773,7 +246699,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_29/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246783,7 +246709,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N709_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N186_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246793,7 +246719,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246803,7 +246729,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N711_2/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N838_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246813,7 +246739,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_1/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N842/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246823,23 +246749,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_2/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246849,7 +246769,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_7_or[3]_2/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_7_or[1]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246859,7 +246779,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_10/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_7_or[3]_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246869,7 +246789,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N564_2/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N597/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246879,7 +246799,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N843_2/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N784_0/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246889,7 +246809,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_29/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246899,7 +246819,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N478/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N243_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246909,7 +246829,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_35/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246919,7 +246839,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N848/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246929,7 +246849,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -246945,7 +246865,27 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_2/gateop;gopMUX4TO1
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_or[0][0]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -246956,7 +246896,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_6/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_30/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -246966,7 +246906,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -246982,17 +246922,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N683_7/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_23_2/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_13_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -247002,14 +246932,20 @@ L3;1
L4;1
Inst
-u_rotate_image/N144_mux4/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N862/gateop;gopMUX4TO1
@@ -247023,18 +246959,17 @@ S0;1
S1;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873_1/gateop;gopMUX4TO1
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N564_2/gateop_perm;gopLUT5
Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N684/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -247044,7 +246979,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_6/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N581_22/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -247263,7 +247208,7 @@ D;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247279,7 +247224,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247295,7 +247240,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247311,23 +247256,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[4]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/h_count[11:0]_or/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247343,7 +247282,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_width/value[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247359,7 +247298,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247375,23 +247314,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux7_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247407,23 +247340,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux10/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_wr_mem_inst/N44/gateop_perm;gopLUT5
+u_sync_vg/N28_mux8_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -247433,7 +247360,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247449,7 +247376,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247465,7 +247392,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247480,16 +247407,6 @@ L3;1
L4;1
RS;1
-Inst
-param_manager_inst/param_osd_startY/N63_mux10_6/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[5]/opit_0_L5Q_perm;gopL5Q
Pin
@@ -247507,7 +247424,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247539,17 +247456,23 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startY/N139/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247565,23 +247488,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[10]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/N145_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_osd_char_height/N139_1/gateop_perm;gopLUT5
+u_sync_vg/N59_mux6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -247591,7 +247508,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/m_row_pixels_valid/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hs_out0/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247606,6 +247523,16 @@ L3;1
L4;1
RS;1
+Inst
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N464_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_width[0]/opit_0;gopQ
Pin
@@ -247806,17 +247733,23 @@ I14;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N593/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247832,7 +247765,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247864,7 +247797,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247880,17 +247813,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247922,20 +247845,27 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
+
+Inst
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N60.lt_6/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[9]/opit_0_L5Q_perm;gopL5Q
@@ -247954,7 +247884,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -247970,7 +247900,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N861/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -247980,7 +247910,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_49/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N84_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -248038,7 +247968,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm;gopLUT5
+u_sync_vg/N50_mux2_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -248411,27 +248341,23 @@ D;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N597/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N589_5/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_13_3/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -248441,7 +248367,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N848/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_and[10][0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -248451,7 +248377,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_33_2/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_23_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -248461,7 +248387,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -248477,17 +248403,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N379/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79_cpy/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N843_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -248497,20 +248429,14 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N102_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[2]/opit_0_L5Q_perm;gopL5Q
@@ -248545,7 +248471,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -248561,20 +248487,14 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/row_cnt[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N679_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/char_osd_inst/char_buf_reader_inst/str_len[0]/opit_0;gopQ
@@ -248763,24 +248683,36 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/N58_maj7/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_5/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm;gopLUT5
@@ -248793,20 +248725,14 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/pix_cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N122/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/char_osd_inst/char_pic_rom_inst/N58_sum6/gateop_perm;gopLUT5
@@ -248819,7 +248745,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/N6_mux4_5/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -249343,7 +249269,7 @@ I4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N588_5/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N100/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -249499,7 +249425,7 @@ I14;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/N11_mux6_1/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -249617,17 +249543,7 @@ I14;1
RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_7/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N206_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -249637,7 +249553,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_5/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/N206_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -249699,17 +249615,7 @@ D;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N135/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux7_7/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N114_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -249719,7 +249625,7 @@ L3;1
L4;1
Inst
-u_sync_vg/pos_x[3]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_height/value[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -249735,20 +249641,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_rotate/N155_8_7/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-udp_wr_mem_inst/N204/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -249758,7 +249651,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startX/value[0]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/h_count[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -249774,7 +249667,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_posX[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -249790,7 +249683,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startY/value[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -249806,7 +249699,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/s_ready_d_d[0]_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N327_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -249816,7 +249709,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N122/gateop_perm;gopLUT5
+u_sync_vg/N138_mux7_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -249826,7 +249719,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N114_11/gateop_perm;gopLUT5
+u_sync_vg/N53_mux7_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -249836,7 +249729,7 @@ L3;1
L4;1
Inst
-u_rotate_image/N144_mux13_6/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/N41/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -249846,7 +249739,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startY/value[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/pix_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -249862,42 +249755,71 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/N137/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_sync_vg/N138_mux4/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/m_row_pixels_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_posX[10]/opit_0_AQ_perm;gopAQ
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/N114_11/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+u_sync_vg/N184_14/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+param_manager_inst/param_osd_char_height/value[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
-Cout;2
Q;2
RSOUT;2
-Y;2
+Z;2
CE;1
CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
@@ -250035,7 +249957,7 @@ I14;1
RS;1
Inst
-param_manager_inst/param_osd_startX/N76_mux4_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N415/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -250166,7 +250088,7 @@ D;1
RS;1
Inst
-u_hdmi_rst/N0/gateop_perm;gopLUT5
+u_sync_vg/N50_mux4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -250249,14 +250171,20 @@ I14;1
RS;1
Inst
-u_sync_vg/N53_mux7_4/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[1]/opit_0_L5Q_perm;gopL5Q
@@ -250275,7 +250203,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -250291,7 +250219,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -250307,7 +250235,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -250339,7 +250267,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -250355,23 +250283,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/N58_maj7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/N41/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/N6_mux4_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -250381,7 +250303,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N684/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N75_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -250408,14 +250330,20 @@ S0;1
S1;1
Inst
-param_manager_inst/param_osd_startY/N149_43_1/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/row_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm;gopDRM
@@ -250668,7 +250596,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/N72_17/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/N72_19/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -250678,7 +250606,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -250688,7 +250616,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -250698,7 +250626,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -250744,7 +250672,7 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -250938,7 +250866,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -250948,7 +250876,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -250964,7 +250892,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -250980,7 +250908,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -250996,17 +250924,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -251022,7 +250956,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[5]_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251032,7 +250966,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -251048,7 +250982,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -251080,7 +251014,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251384,23 +251318,17 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_12/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -251416,7 +251344,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251426,7 +251354,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -251442,20 +251370,14 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q
@@ -251490,7 +251412,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N613_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251516,7 +251438,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -251532,23 +251454,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/N20.fsub_8/gateop_perm;gopA
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16_cpy/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251690,7 +251609,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251700,27 +251619,39 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251730,7 +251661,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251740,7 +251671,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251750,7 +251681,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N367/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251760,7 +251691,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251770,7 +251701,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251780,23 +251711,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251806,7 +251731,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251816,7 +251741,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N983_9/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251826,7 +251751,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251836,7 +251761,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251856,7 +251781,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251866,20 +251791,14 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5
@@ -251892,20 +251811,14 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5
@@ -251918,23 +251831,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_10/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -251954,57 +251861,87 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N263/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252014,17 +251951,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N148_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_12/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252034,7 +251977,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_10/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252054,7 +251997,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -252070,14 +252013,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N192_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_0/gateop_A2;gopA2
@@ -252683,17 +252632,23 @@ WR_EOP;1
WR_ERR;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_41/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[12]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_1_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N312_1_or[0]_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252714,7 +252669,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N706/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N312_1_or[0]_2_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252724,7 +252679,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_23/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_27/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252734,7 +252689,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_28/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252744,7 +252699,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_26/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252754,7 +252709,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_24/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N847/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252764,23 +252719,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_25/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_64_cpy/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N60_mux3_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252790,7 +252739,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_1_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252800,7 +252749,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_64/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252810,7 +252759,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_7/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252820,20 +252769,17 @@ L3;1
L4;1
Inst
-u_zoom_image/N375.eq_6/gateop_perm;gopA
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N466_9/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252843,7 +252789,27 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_24/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_36[0]_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252873,17 +252839,7 @@ S10;1
S11;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N310_18/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N310_16/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -252894,7 +252850,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N766_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_51/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252904,7 +252860,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_40/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N1057_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252914,18 +252870,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N312_1_or[0]_7/gateop;gopMUX4TO1
-Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_47/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_78/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252946,7 +252891,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N834/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N566_14_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252956,7 +252901,18 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366_1/gateop;gopMUX4TO1
+Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_25/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252966,7 +252922,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N766_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_56/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252976,7 +252932,7 @@ L3;1
L4;1
Inst
-u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_62/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -252996,7 +252952,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_50/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_52/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253016,20 +252972,14 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[45]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_42/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_46/gateop_perm;gopLUT5
@@ -253042,20 +252992,14 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_50/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_54/gateop_perm;gopLUT5
@@ -253088,17 +253032,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_64/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[12]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_70/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_58/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253108,7 +253058,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[19]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[43]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253124,17 +253074,7 @@ L4;1
RS;1
Inst
-u_ov5640/coms1_reg_config/u1/N195_inv/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_zoom_image/wr_addr2[0]/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253150,7 +253090,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_58/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253160,17 +253100,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_69/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[34]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_74/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_55/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253180,7 +253126,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[24]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[25]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253196,7 +253142,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/multiline_buffer_inst/N53_mux5_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253206,7 +253152,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N422_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[31]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_23/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253227,7 +253189,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N566_14_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253237,7 +253199,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_48/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253247,7 +253209,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_44/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_1_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253257,7 +253219,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_23/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253267,17 +253229,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_52/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[19]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253293,46 +253261,33 @@ L4;1
RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/N87_1_10/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_64/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[28]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[12]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N58_ac2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_31/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_28/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253342,7 +253297,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N847/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N619_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253352,7 +253307,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1082/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N566_14_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253362,17 +253317,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_28/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_type/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[5]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N635_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253382,7 +253343,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N58_ac2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_31/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253392,7 +253353,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N566_14_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253402,7 +253363,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_30/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253428,7 +253389,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/N63_mux7_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253438,7 +253399,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_52/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N357_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253448,7 +253409,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N374/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N78/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253458,7 +253419,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N1057_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N831_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253468,17 +253429,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N516/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[29]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253488,7 +253455,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_type/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253504,7 +253471,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253520,17 +253487,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_40/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N186/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_16/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253540,7 +253497,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N72_mux3_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N577_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253550,24 +253507,42 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N584_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm;gopL6Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+A0;1
+A1;1
+A2;1
+A3;1
+A4;1
+B0;1
+B1;1
+B2;1
+B3;1
+B4;1
+CE;1
+CLK;1
+M;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N82_mux3_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_rx_flag/opit_0_L5Q_perm;gopL5Q
@@ -253586,7 +253561,7 @@ L4;1
RS;1
Inst
-u_zoom_image/rd_addr0[10:0]_inv/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N406/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253596,7 +253571,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253612,7 +253587,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253660,23 +253635,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[11]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N706/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253692,17 +253661,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N312_1_or[0]_2_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[2]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253718,45 +253693,27 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm;gopL6Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N364/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
-CE;1
-CLK;1
-M;1
-RS;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[36]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253772,7 +253729,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253788,7 +253745,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[2]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253804,23 +253761,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[11]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_43/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[4]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253836,7 +253787,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[5]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253852,7 +253803,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[31]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[6]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253868,7 +253819,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[29]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253895,7 +253846,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[17]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[19]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -253922,7 +253873,7 @@ D;1
RS;1
Inst
-u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_47/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -253987,7 +253938,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[19]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[17]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254014,7 +253965,7 @@ D;1
RS;1
Inst
-u_ov5640/coms1_reg_config/N26_mux6_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_32/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -254101,20 +254052,14 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N82_mux3_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[28]/opit_0;gopQ
@@ -254128,14 +254073,20 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_36/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[31]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[30]/opit_0;gopQ
@@ -254149,14 +254100,20 @@ D;1
RS;1
Inst
-u_zoom_image/N236_0/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[0]/opit_0;gopQ
@@ -254247,7 +254204,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254263,17 +254220,23 @@ L4;1
RS;1
Inst
-u_ov5640/coms1_reg_config/u1/N239/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[12]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254289,7 +254252,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[13]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[19]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254305,17 +254268,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_47/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[13]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[16]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[32]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254331,7 +254300,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[14]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254347,7 +254316,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[15]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[16]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254363,14 +254332,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_62/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[20]/opit_0_L5Q_perm;gopL5Q
@@ -254389,7 +254364,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[22]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[26]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254405,7 +254380,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[23]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[22]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254437,7 +254412,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[25]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[23]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254453,39 +254428,27 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[33]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_47/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[31]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N322_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[28]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[24]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254501,17 +254464,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_49/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[29]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[30]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[27]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254527,7 +254496,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[27]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[30]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254543,7 +254512,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[29]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[33]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254559,7 +254528,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[32]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[37]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254575,7 +254544,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[34]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[17]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254591,7 +254560,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[37]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[38]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254607,14 +254576,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_66/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[35]/opit_0_L5Q_perm;gopL5Q
@@ -254633,17 +254608,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/N403_5/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[26]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[39]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254659,7 +254624,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[36]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254675,7 +254640,7 @@ L4;1
RS;1
Inst
-u_ov5640/coms1_reg_config/u1/N8_mux3_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_49/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -254685,7 +254650,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[39]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254701,7 +254666,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[42]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[45]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254733,23 +254698,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[44]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/rd_addr0[10:0]_inv/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[43]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[42]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254781,7 +254740,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[17]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[44]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254813,7 +254772,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_42/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_70/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -254823,7 +254782,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[47]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[47]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -254838,6 +254797,16 @@ L3;1
L4;1
RS;1
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_1_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/error_en/opit_0_MUX4TO1Q;gopMUX4TO1Q
Pin
@@ -255577,7 +255546,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[16]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255593,7 +255562,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[15]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[16]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255609,7 +255578,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[18]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255625,7 +255594,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[19]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[20]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255641,7 +255610,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[20]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[19]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255657,17 +255626,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[8]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[21]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[22]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[18]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255683,7 +255658,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[23]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255699,7 +255674,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[24]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255715,7 +255690,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[31]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[24]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255731,7 +255706,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[26]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[22]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255747,7 +255722,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[21]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255763,23 +255738,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[28]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[27]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[29]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255795,7 +255764,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[26]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255811,7 +255780,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[27]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255827,17 +255796,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[29]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[28]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255853,7 +255828,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_12/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_24/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -255863,27 +255838,39 @@ L3;1
L4;1
Inst
-u_zoom_image/N232_0/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_28/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[31]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -255899,30 +255886,30 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_56/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_image/wr_addr0[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[0]/opit_0;gopQ
@@ -256541,7 +256528,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[16]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[18]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256557,7 +256544,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[17]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[20]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256573,7 +256560,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[18]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256589,7 +256576,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[12]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[19]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256605,7 +256592,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[34]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[24]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256621,7 +256608,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[14]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[16]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256637,7 +256624,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[40]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[22]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256669,7 +256656,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[24]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[21]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256685,7 +256672,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[41]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[35]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256749,7 +256736,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[29]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[42]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256781,7 +256768,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[31]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[38]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256813,7 +256800,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[25]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[33]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256829,7 +256816,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[33]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[34]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256845,23 +256832,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[35]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_50/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[36]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[44]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256877,7 +256858,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[37]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[31]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256893,7 +256874,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[38]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[46]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256925,17 +256906,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_32/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[40]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[37]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256951,7 +256938,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[42]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256967,7 +256954,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[43]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[36]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256983,7 +256970,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[44]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[43]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -256999,7 +256986,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[45]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[41]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -257031,17 +257018,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_32/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[45]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[46]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[17]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -257057,7 +257050,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N489_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257067,39 +257060,27 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[2]_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[20]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_48/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N102_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_32/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257109,7 +257090,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[6]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_13/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257119,23 +257100,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[22]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/N72_25/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257178,17 +257153,23 @@ I3;1
I4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[6]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[12]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N165_5/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/N138_26/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257279,20 +257260,14 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/N72_26_cpy/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[2]_7_muxf6;gopMUX8TO1
@@ -257315,7 +257290,7 @@ S10;1
S11;1
Inst
-ms72xx_ctl/ms7200_ctl/N40_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_24/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257476,7 +257451,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[2]_4/gateop_perm;gopLUT5
+u_zoom_image/N530_mux3_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257530,7 +257505,17 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_8/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N39_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_12/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -257541,7 +257526,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_12/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_14/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -257552,7 +257537,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_14/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_16/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -257563,7 +257548,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_44/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N817_2_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257573,17 +257558,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_36[0]_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[29]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_20/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257593,7 +257584,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_40/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257603,23 +257594,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[11]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_39/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_44/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257629,7 +257614,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_36/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257639,7 +257624,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_16/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_40/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257649,7 +257634,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_36[1]_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N327/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257659,7 +257644,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_48/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257669,7 +257654,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[5]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257679,7 +257664,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_29/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257689,23 +257674,27 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[12]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_12/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_24/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_20/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257715,7 +257704,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_13/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_55/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257725,22 +257714,19 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][31]/opit_0_AQ_perm;gopAQ
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
-Cout;2
Q;2
RSOUT;2
-Y;2
+Z;2
CE;1
CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
@@ -257754,7 +257740,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_20/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_28/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257764,48 +257750,30 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[14]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_17_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[7]_2_muxf6_perm;gopLUT6
-Pin
-Y0;2
-Y1;2
-Z;2
-A0;1
-A1;1
-A2;1
-A3;1
-A4;1
-B0;1
-B1;1
-B2;1
-B3;1
-B4;1
-M;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N421_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N411_6/gateop;gopMUX4TO1
@@ -257819,7 +257787,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N427_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257829,20 +257797,14 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N419_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N416_7/gateop;gopMUX4TO1
@@ -257866,7 +257828,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N415/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N427_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257886,7 +257848,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N415_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N817_1_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257896,7 +257858,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257906,7 +257868,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N420_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257916,17 +257878,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N817_2_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/crc_en/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/crc_en/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -257942,7 +257910,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -257958,7 +257926,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N8_7/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N781_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257968,7 +257936,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/ms7200_ctl/N1877/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257978,7 +257946,7 @@ L3;1
L4;1
Inst
-N285_9/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257988,7 +257956,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N199_1/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/N230/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -257998,7 +257966,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N220_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_48[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -258008,7 +257976,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[2]_9/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_27/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -258018,7 +257986,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N781_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N189_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -258214,14 +258182,20 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N102_7/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_50[0]/gateop;gopMUX4TO1
@@ -258400,36 +258374,14 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[9]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[7][0]/opit_0;gopQ
@@ -259334,7 +259286,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -259350,20 +259302,14 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5:0]_89/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[3]/opit_0_L5Q_perm;gopL5Q
@@ -259382,7 +259328,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -259435,7 +259381,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N206_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259445,7 +259391,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5:0]_89/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5:0]_85/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -259456,7 +259402,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N411_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N418/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259466,7 +259412,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N419_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N102_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259487,17 +259433,23 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N236_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -259529,7 +259481,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_tx_en/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -259561,7 +259513,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -259609,7 +259561,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -259625,7 +259577,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_36[1]_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259635,7 +259587,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/N80_0/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259764,30 +259716,30 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[2]/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N236_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/skip_en/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -259856,6 +259808,16 @@ CLK;1
D;1
RS;1
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N263/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N148_2/gateop_perm;gopLUT5
Pin
@@ -259867,7 +259829,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N84_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259877,7 +259839,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N263/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N199_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259887,23 +259849,27 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N183_4/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -259919,7 +259885,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N248_5/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259929,7 +259895,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N183_4/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259939,7 +259905,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N243_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N192_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259949,7 +259915,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_6/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/N206_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259959,7 +259925,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N192_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N248_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259969,7 +259935,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N206_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N206_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -259979,7 +259945,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -259995,17 +259961,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N75_1/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[1]/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N478/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -260015,7 +259987,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N211_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N111_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -260025,7 +259997,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N588_5/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260041,7 +260023,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_7/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N339_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -260051,7 +260033,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N189_1/gateop_perm;gopLUT5
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N589_5_cpy/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -260061,7 +260043,7 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260077,17 +260059,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260103,17 +260091,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N39_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260129,7 +260123,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260145,7 +260139,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260161,7 +260155,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260177,7 +260171,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260193,7 +260187,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260225,7 +260219,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[15]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260241,7 +260235,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260257,7 +260251,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260273,7 +260267,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260289,7 +260283,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260305,7 +260299,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260321,7 +260315,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260337,7 +260331,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260353,7 +260347,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N711_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260369,7 +260373,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[6]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260385,17 +260399,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N186_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260411,7 +260431,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260427,7 +260447,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260443,7 +260463,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N683_7/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260475,7 +260505,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[23]/opit_0_L5Q;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260491,7 +260521,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260507,7 +260537,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260523,17 +260553,33 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_48[7]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_en/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N421_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260549,37 +260595,55 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N3_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_eth_ctrl/protocol_sw_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/ram_addr[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260595,7 +260659,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260611,7 +260675,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_eth_ctrl/protocol_sw_reg[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -260627,7 +260691,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5:0]_93/gateop_perm;gopLUT5
+N163_mux3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -260637,113 +260701,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[2]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[7]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[4]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[6]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N817_1_4/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N75_1/gateop_perm;gopLUT5
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -260764,20 +260722,14 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[19]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N832/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[0]/opit_0;gopQ
@@ -261367,14 +261319,46 @@ MI;1
T;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_7/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N189_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N220_3/gateop_perm;gopLUT5
@@ -261387,7 +261371,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[3]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N183_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -261397,7 +261381,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N84_1/gateop;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N206_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -261407,23 +261391,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N192_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N186_1/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N461_8_or[4][3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -261433,17 +261411,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N199_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N39_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N192_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -261453,7 +261437,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N248_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -261463,7 +261447,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261479,7 +261463,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[4]/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1872_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -261489,20 +261473,24 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/N222/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+ms72xx_ctl/ms7200_ctl/N2083/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N236_5/gateop_perm;gopLUT5
@@ -261515,7 +261503,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -261525,39 +261513,27 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N1954_1_or[1]_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261573,7 +261549,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N102_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N171_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -261583,7 +261559,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N248_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N189_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -261609,17 +261595,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N418/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261635,7 +261627,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261651,7 +261643,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261667,7 +261659,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261683,7 +261675,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261699,7 +261691,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261715,7 +261707,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261731,33 +261723,33 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N199_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N183_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261773,7 +261765,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261789,7 +261781,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261805,7 +261797,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[30]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261821,7 +261813,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261837,7 +261829,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/N87_1_10/gateop_perm;gopA
+Pin
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261869,7 +261874,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261885,7 +261890,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[15]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261901,7 +261906,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N243_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -261911,7 +261916,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N111_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N102_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -261921,39 +261926,27 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N243_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -261985,55 +261978,37 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[30]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/N1359_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N186_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N102_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -262049,7 +262024,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/char_buf_writer_inst/ram_addr[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -262065,7 +262040,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N420_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N806_14_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262075,7 +262050,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N189_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N100/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262085,23 +262060,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N834/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N3_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N578_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262111,7 +262080,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N206_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262121,7 +262090,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1261/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_30/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262131,7 +262100,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1213_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262141,7 +262110,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_19/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1261/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262151,7 +262120,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_33/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_22/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262161,7 +262130,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_44/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N838/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262181,37 +262150,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_30/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_47/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_18/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_14/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_33/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262221,7 +262160,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_33/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_33/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262231,7 +262170,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_58/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_22/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262241,7 +262180,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_29/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262251,7 +262190,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_33/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_15/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262261,7 +262200,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N306_9/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_41/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262271,7 +262210,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_22/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262281,7 +262220,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N100/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_26/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262291,7 +262230,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1130_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262301,7 +262240,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_26/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_67/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262311,7 +262250,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_29/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262321,7 +262260,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_18/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_18_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262331,7 +262270,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_37/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_47/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262351,7 +262290,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_49/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_37/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262361,7 +262300,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N82_mux3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N518_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262371,7 +262310,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1309_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262381,7 +262320,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_26/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262391,7 +262330,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N956/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N199_maj3_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262401,17 +262340,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1079_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_44/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262421,7 +262366,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_38/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N578_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262431,7 +262376,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_36/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_47/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262441,17 +262386,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_47/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N406/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N516/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262461,7 +262412,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_56/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N232_and[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262471,7 +262422,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_51/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_32/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262481,7 +262432,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -262497,27 +262448,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N230_9_3/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N199_maj3_1/gateop;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_zoom_image/N306_12/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N579_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262547,27 +262478,20 @@ I13;1
I14;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N905/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N806_14_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N216.eq_2/gateop;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N183/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N803_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262577,7 +262501,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N573/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N199_sum5_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -262827,14 +262751,17 @@ I13;1
I14;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N361.eq_8/gateop;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N372_1/gateop_A2;gopA2
@@ -263557,7 +263484,7 @@ I13;1
I14;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_2_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N619_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263567,7 +263494,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N518_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N573_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263577,18 +263504,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_18_3/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_8/gateop_perm;gopLUT5
Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N518_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_2_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263629,7 +263555,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -263645,17 +263571,39 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_70/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[1]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_68/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -263666,7 +263614,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N257_13_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1304/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263676,7 +263624,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_29/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N577_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263686,17 +263634,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N620_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_13/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N511_3/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -263707,7 +263661,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N571_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263717,18 +263671,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N511_3/gateop;gopMUX4TO1
-Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N578_7/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_fsm[6:0]_38/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263738,39 +263681,27 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N795_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_31/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_fsm[6:0]_46/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_fsm[6:0]_33/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263780,7 +263711,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N806_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N956/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263790,7 +263721,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N578_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N571_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263800,7 +263731,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N310_7_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N82_mux3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263810,7 +263741,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N579_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1213_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263820,7 +263751,18 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N892_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N579_1/gateop;gopMUX4TO1
+Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N602_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263830,7 +263772,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1326_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N905/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263851,7 +263793,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N619_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263861,7 +263803,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_15_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263871,7 +263813,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N795_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263892,33 +263834,17 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N803_4/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N620_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1309_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N892_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263928,17 +263854,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N199_sum5_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817_1/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N806_14_3/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -263949,7 +263881,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1304/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_36/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263959,7 +263891,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1170/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263969,7 +263901,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N312_1_or[0]_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1082/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -263979,23 +263911,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_29/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_51/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264005,7 +263931,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_11_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1057_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264015,7 +263941,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1057_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264025,23 +263951,38 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_21/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[2]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014_2/gateop;gopMUX4TO1
+Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -264057,7 +263998,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_32/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264067,7 +264008,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1127_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1170/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264077,7 +264018,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1294/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264087,7 +264028,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_33/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264097,7 +264038,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1130_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1294/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264107,17 +264048,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_25/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N310_16/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264127,7 +264074,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N577_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_15_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264137,7 +264084,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_44/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264147,23 +264094,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1265/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264173,7 +264114,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N232_and[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_44/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264182,19 +264123,6 @@ L2;1
L3;1
L4;1
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N216.eq_2/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
@@ -264228,7 +264156,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N838/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_33/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264254,7 +264182,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N602_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_49/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264264,7 +264192,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_69/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -264274,30 +264202,30 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[0]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_14/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[1]/opit_0_L5Q;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q
@@ -264316,7 +264244,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -264332,7 +264260,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -264348,7 +264276,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_pkt_done/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -264364,7 +264292,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_pkt_done/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -265172,14 +265100,20 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N80_ac2/gateop_perm;gopLUT5
+u_ddr_rst/rst/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[8]/opit_0;gopQ
@@ -265292,14 +265226,20 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[4]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[2]/opit_0_L5Q;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[4]/opit_0_A2Q21;gopA2Q2
@@ -265659,23 +265599,14 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[15]/opit_0_AQ_perm;gopAQ
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[2]/opit_0_A2Q21;gopA2Q2
@@ -265867,7 +265798,7 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -265925,7 +265856,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[17]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -265989,20 +265920,14 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[16]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N353_ac2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[0]/opit_0;gopQ
@@ -266577,7 +266502,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -266593,7 +266518,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N635_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -266955,7 +266880,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -266971,7 +266896,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -266987,7 +266912,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267003,7 +266928,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267019,7 +266944,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267050,6 +266975,64 @@ L3;1
L4;1
RS;1
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[8]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[10]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[9]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N80_ac2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[11]/opit_0_L5Q_perm;gopL5Q
Pin
@@ -267067,7 +267050,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267099,43 +267082,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[10]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_60/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_sync_vg/N50_mux3/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[14]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[18]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267167,7 +267114,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267183,7 +267130,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[22]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267199,7 +267146,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[17]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[21]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267215,7 +267162,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[18]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[19]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267231,7 +267178,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[23]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267247,7 +267194,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[24]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267263,7 +267210,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[21]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[25]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267279,7 +267226,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[22]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[23]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267295,7 +267242,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_56/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[13]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267305,23 +267252,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[24]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[25]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[26]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267337,7 +267268,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[26]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[20]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -267433,7 +267364,7 @@ L4;1
RS;1
Inst
-u_ov5640/coms1_reg_config/N8_mux10/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267636,7 +267567,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267646,7 +267577,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267656,7 +267587,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[14]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267666,7 +267597,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N290_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267676,7 +267607,7 @@ L3;1
L4;1
Inst
-u_zoom_image/N234_0/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267686,7 +267617,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[15]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267696,7 +267627,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[4]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267716,7 +267647,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[5]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267726,7 +267657,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[12]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267736,7 +267667,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[8]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[15]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267746,7 +267677,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N353_ac2/gateop_perm;gopLUT5
+u_axi_rst/N0/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267756,7 +267687,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[15]/gateop_perm;gopLUT5
+u_rotate_image/N57_mux4_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267766,7 +267697,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[10]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[12]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267776,7 +267707,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[11]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[14]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267786,27 +267717,39 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[14]/gateop_perm;gopLUT5
+u_rotate_image/cnt_h[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[9]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N15/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[15]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267816,7 +267759,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_17_3/gateop_perm;gopLUT5
+u_clk50m_rst/rst/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N367/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267826,7 +267785,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_32/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267836,7 +267795,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N594_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N164_sum3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267846,7 +267805,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N612_8/gateop_perm;gopLUT5
+u_ddr_addr_ctr/N72_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267856,7 +267815,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[3]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267866,7 +267825,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[5]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267876,7 +267835,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[7]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_28_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267886,7 +267845,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[7]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_53/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267896,7 +267855,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N610/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267906,7 +267865,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267916,7 +267875,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[4]/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/N165/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267926,7 +267885,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[4]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_20/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -267936,7 +267895,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[1]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_28/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268019,14 +267978,20 @@ S10;1
S11;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_12/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/udp_rx_s_data_tready/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[3]_muxf6;gopMUX8TO1
@@ -268089,7 +268054,7 @@ S10;1
S11;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_36/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_16/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268099,7 +268064,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_28/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N192/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268109,7 +268074,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268119,23 +268084,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[15]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[6]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268145,17 +268104,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1731/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][16]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[3]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268165,7 +268130,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[9]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268175,7 +268140,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[8]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268185,7 +268150,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268195,7 +268160,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[5]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268205,7 +268170,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/N170/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[13]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268215,7 +268180,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[10]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268235,7 +268200,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268245,7 +268210,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[13]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268255,7 +268220,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[3]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[14]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268265,27 +268230,39 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[15]/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/addr[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[15]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][13]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[12]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268295,7 +268272,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N612_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268305,7 +268282,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_16/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -268455,14 +268432,17 @@ I13;1
I14;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N937_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N328_1.fsub_15/gateop;gopA
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cout;2
+Y;2
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N329.lt_0/gateop_A2;gopA2
@@ -268865,23 +268845,17 @@ I13;1
I14;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[12]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_34/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269111,23 +269085,17 @@ I13;1
I14;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[21]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_10/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N919_7_or[0]_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_22/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269137,36 +269105,34 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[11]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N613_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_75_muxf6;gopMUX8TO1
@@ -269211,7 +269177,23 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269221,7 +269203,57 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[13]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_12/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_14/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_6/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1036_9_5/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[12]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -269237,17 +269269,34 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N603/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N609_5/gateop;gopMUX4TO1
Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+ms72xx_ctl/iic_dri_tx/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N609_6/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_5/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -269258,7 +269307,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_26[0]_1/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_70/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269268,7 +269317,7 @@ L3;1
L4;1
Inst
-ms72xx_ctl/iic_dri_rx/N72/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N915/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269278,7 +269327,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_14/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N259_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269288,23 +269337,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/change_to_read/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/N39/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_9/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_18/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269314,7 +269357,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_17/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N623_3/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -269325,7 +269368,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N958_2/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/N80_0/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269335,7 +269378,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N940/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269345,7 +269388,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N622_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1066_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269355,7 +269398,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N620/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269365,7 +269408,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1036_9_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[15]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269375,7 +269418,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N191_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2622_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269385,18 +269428,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N623_3/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_9/gateop_perm;gopLUT5
Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N919_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269406,7 +269448,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N191_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269416,7 +269458,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269426,7 +269468,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N940/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269436,7 +269478,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_53/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N703_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269446,7 +269488,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[3]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269456,17 +269498,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[4]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/trig_tx_en/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[6]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269476,7 +269524,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[14]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269486,17 +269534,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[5]/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/send_data[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[7]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1731/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269506,7 +269560,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/N461_8_or[1][2]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -269522,7 +269586,37 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[11]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[13]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_5/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[3]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -269538,7 +269632,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[9]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_24/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269548,7 +269642,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[13]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[16]/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -269558,7 +269652,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[11]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[15]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269568,7 +269678,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[12]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269578,7 +269688,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[13]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269588,7 +269698,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[14]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269598,7 +269708,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/N138/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1127_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269608,7 +269718,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269618,17 +269728,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[1]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][13]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[16]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269638,7 +269754,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[10]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -269654,7 +269780,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[10]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269664,7 +269790,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/cnt[15:0]_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[11]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269674,7 +269800,43 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[2]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[12]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[14]/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[16]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -269700,23 +269862,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[2]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[9]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269726,7 +269882,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -269742,57 +269898,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[4]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[10]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[6]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[12]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[9]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[1]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269802,27 +269908,39 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[5]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[11]/gateop_perm;gopLUT5
+sync_vg_100m/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -269838,7 +269956,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269848,7 +269966,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[12]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[10]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -269868,148 +269986,27 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[13]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[3]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[4]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-u_sync_vg/N23_1_9/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[8]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[6]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[7]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[5]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[4]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[10]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/char_buf_writer_inst/state_reg[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[8]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][13]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -270025,17 +270022,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[15]/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[14]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270045,7 +270032,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270055,23 +270042,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/char_buf_writer_inst/cnt[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[11]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1066_7/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/N165_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270081,7 +270062,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N164_sum3/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N316_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270459,7 +270440,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[5]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270469,33 +270450,33 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_en/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[6]/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_28_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[4]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270505,7 +270486,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_24[0]_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[6]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270515,7 +270496,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[1]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270525,7 +270506,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[5]/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/N1895/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270535,20 +270516,14 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_tx_en/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N173_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_24[7]_2/gateop;gopMUX4TO1
@@ -270562,7 +270537,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_24/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1066_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270572,7 +270547,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[3]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N282/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270582,7 +270557,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -270609,7 +270584,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N619_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N81/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270619,53 +270594,65 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_22/gateop_perm;gopLUT5
+u_zoom_rst/rst/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_32/gateop_perm;gopLUT5
+ms72xx_ctl/ms7200_ctl/state_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_39/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -270681,7 +270668,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2622_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10_cpy/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -270691,7 +270678,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][16]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -272691,7 +272678,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -272707,46 +272694,40 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N164_sum2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N260_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N919_8/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_clr/opit_0;gopQ
@@ -272760,7 +272741,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_done_t/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -272776,7 +272757,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -272792,7 +272773,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -272808,7 +272789,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/trig_tx_en/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -272840,23 +272821,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N609_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_req/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/trans_bit[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -272872,30 +272847,30 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N919_7_or[3]_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1066_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[7]/opit_0_L5Q;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[15]/opit_0_AQ_perm;gopAQ
@@ -273106,7 +273081,7 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[13]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -273780,7 +273755,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_done_t/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_req/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -273972,20 +273947,14 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[23]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[3]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][18]/opit_0_A2Q21;gopA2Q2
@@ -274177,14 +274146,23 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][31]/opit_0_AQ;gopAQ
Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+CEOUT;2
+Cout;2
+Q;2
+RSOUT;2
+Y;2
+CE;1
+CLK;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][1]/opit_0_L5Q_perm;gopL5Q
@@ -274203,7 +274181,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274219,7 +274197,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274251,23 +274229,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[12]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274283,7 +274255,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[13]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274299,7 +274271,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][12]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][7]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274347,17 +274319,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[7]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][11]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274373,7 +274351,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][15]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274389,7 +274367,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][14]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274405,24 +274383,36 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[13]/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/send_data[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[8]/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/addr[3]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][0]/opit_0;gopQ
@@ -274793,7 +274783,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][1]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274809,17 +274799,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[3]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][3]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274835,23 +274831,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][5]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274867,7 +274857,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][6]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274883,17 +274873,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[14]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][8]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274909,7 +274905,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274925,7 +274921,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][11]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274957,7 +274953,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][13]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][15]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274973,17 +274969,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[15]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][14]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][14]/opit_0_L5Q;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -274999,7 +275001,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][15]/opit_0_L5Q;gopL5Q
+u_hdmi_rst/rst/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -275367,14 +275369,20 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1109/gateop_perm;gopLUT5
+ms72xx_ctl/ms7210_ctl/addr[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[2]/opit_0_L5Q_perm;gopL5Q
@@ -275425,20 +275433,14 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N961/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -275513,14 +275515,20 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[4]/opit_0_A2Q21;gopA2Q2
@@ -275704,7 +275712,7 @@ I4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_7/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N338_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -275714,20 +275722,14 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[13]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[1]/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -275901,23 +275903,17 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N173_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/busy/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -275933,7 +275929,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N460/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N591_14_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -275943,7 +275939,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N364/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -275953,18 +275949,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N90/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm;gopLUT5
Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_14/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_30/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -275974,7 +275969,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_41/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_33/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -275984,14 +275979,20 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_10/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_14/gateop_perm;gopLUT5
@@ -276004,17 +276005,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_18/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_33/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_18/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276024,7 +276031,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_26/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_33/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276034,7 +276041,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_29/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276044,7 +276051,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_29/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_18/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276054,7 +276061,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_22/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_41/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276064,7 +276071,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_26/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276074,7 +276081,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_37/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_47/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276084,7 +276091,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_33/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_22/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276094,7 +276101,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_26/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276104,7 +276111,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_22/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_37/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276114,7 +276121,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_14/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_10/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276124,7 +276131,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_22/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_69/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276134,7 +276141,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_28/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_15/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276144,7 +276151,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N319_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276154,7 +276161,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_15_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_44/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276164,7 +276171,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_44/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276174,7 +276181,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_30/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276184,7 +276191,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_49/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276194,14 +276201,20 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_29/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_start/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_2_3/gateop_perm;gopLUT5
@@ -276214,7 +276227,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N431/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276234,7 +276247,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_46/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276244,7 +276257,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_50/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_46/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276254,7 +276267,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_30/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_65/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276264,24 +276277,36 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_24/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N591_14_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2;gopA2
@@ -276528,17 +276553,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N432_3/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N859_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_29/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276548,14 +276563,20 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N191_and[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[4]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_18_3/gateop;gopMUX4TO1
@@ -276569,23 +276590,17 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N433/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[8]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/addr[4]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -276601,23 +276616,17 @@ L4;1
RS;1
Inst
-param_manager_inst/osd_startX_load/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_28/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_68/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_70/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -276628,7 +276637,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_69/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_71/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -276639,7 +276648,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_70/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_72/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -276650,20 +276659,14 @@ S0;1
S1;1
Inst
-u_zoom_image/imag_addr0[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_24/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_5/gateop;gopMUX4TO1
@@ -276677,7 +276680,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_7/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_8/gateop;gopMUX4TO1
Pin
F;2
I0;1
@@ -276688,17 +276691,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N619_6/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276708,7 +276701,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N434_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276729,18 +276722,23 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N429_4/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out/opit_0_L5Q_perm;gopL5Q
Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N588_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N584_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276750,7 +276748,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_11_3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N460/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276760,7 +276768,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N70_ac2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276781,7 +276789,7 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_24/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N588_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276791,23 +276799,17 @@ L3;1
L4;1
Inst
-u_zoom_image/imag_addr0[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_30/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_11_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N889/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276817,18 +276819,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N591_14_3/gateop;gopMUX4TO1
-Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
-
-Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N889/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276838,7 +276829,7 @@ L3;1
L4;1
Inst
-param_manager_inst/selected[12]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -276854,7 +276845,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N60_mux3_5/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276864,7 +276855,7 @@ L3;1
L4;1
Inst
-u_zoom_image/imag_addr1[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -276880,7 +276871,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_startX/cnt[5]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7210_ctl/cmd_index[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -276896,7 +276887,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[2]_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276906,7 +276897,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N859_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276916,7 +276907,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N421/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276926,18 +276917,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N757/gateop;gopMUX4TO1
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N748/gateop_perm;gopLUT5
Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
-param_manager_inst/key_debounce_key_left/N47_13/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276947,7 +276937,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N434_4/gateop_perm;gopLUT5
+udp_wr_mem_inst/N549_29/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276957,17 +276947,34 @@ L3;1
L4;1
Inst
-param_manager_inst/key_debounce_key_left/N47_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[9]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_49/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N757/gateop;gopMUX4TO1
+Pin
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878_4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -276977,7 +276984,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -276993,7 +277000,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -277009,17 +277016,23 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetX/N139_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -277035,7 +277048,7 @@ L4;1
RS;1
Inst
-u_zoom_image/imag_addr0[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -277051,17 +277064,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_10/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -277077,7 +277096,27 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_34/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N72_mux3/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -277093,7 +277132,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -277109,7 +277148,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -277125,7 +277164,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -277141,7 +277180,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_en/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N575_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -277157,14 +277206,20 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1123_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_en/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[0]/opit_0;gopQ
@@ -277200,7 +277255,7 @@ D;1
RS;1
Inst
-udp_wr_mem_inst/N44_11/gateop_perm;gopLUT5
+udp_wr_mem_inst/N549_33/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -277580,20 +277635,14 @@ I14;1
RS;1
Inst
-param_manager_inst/param_rotate/cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[0]/opit_0;gopQ
@@ -278388,7 +278437,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_66/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N191_and[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -278486,7 +278535,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278518,7 +278567,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278534,7 +278583,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[7]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278550,7 +278599,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278566,7 +278615,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/flags[22]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278582,7 +278631,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278598,7 +278647,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278614,7 +278663,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278630,17 +278679,23 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/N504/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[13]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278656,7 +278711,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[12]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278672,7 +278727,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[14]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278688,7 +278743,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[11]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -278720,20 +278775,14 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N766_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[0]/opit_0;gopQ
@@ -278824,39 +278873,27 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_start/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/N72_18/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866_7/gateop_perm;gopLUT5
+udp_wr_mem_inst/N549_21/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279323,17 +279360,23 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279343,7 +279386,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_31/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279353,7 +279396,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_7/gateop_perm;gopLUT5
+u_ddr_addr_ctr/N72_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279363,7 +279406,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N327/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_25/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279383,27 +279426,39 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_29/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_rotate_A/N63_mux9_8/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N173_3/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N321/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279413,7 +279468,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N321/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/N138/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279423,7 +279478,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N173_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279433,7 +279488,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[0]/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/ms7200_ctl/init_over/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -279449,17 +279504,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N915/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_num[0]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N260_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_6/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279469,20 +279530,15 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N192_1/gateop;gopMUX4TO1
Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
+F;2
+I0;1
+I1;1
+I2;1
+I3;1
+S0;1
+S1;1
Inst
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_1/gateop;gopMUX4TO1
@@ -279496,27 +279552,39 @@ S0;1
S1;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[7]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_num_en/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N260_3/gateop_perm;gopLUT5
+u_ddr_addr_ctr/vs_30hz/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N504/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_34/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279526,7 +279594,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[6]/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/N313_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279536,28 +279604,23 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N259_2/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/ram_din[2]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N281_7[0]_1/gateop;gopMUX4TO1
-Pin
-F;2
-I0;1
-I1;1
-I2;1
-I3;1
-S0;1
-S1;1
-
-Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -279573,7 +279636,7 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/N62_sum4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N338_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279583,7 +279646,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_num_en/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[25]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -279599,23 +279662,27 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_num[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N612_10/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-ms72xx_ctl/iic_dri_rx/N310_7/gateop_perm;gopLUT5
+udp_osd_inst/char_buf_writer_inst/N138_20/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N220_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -279641,33 +279708,30 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_12/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[15]/opit_0_AQ_perm;gopAQ
+ms72xx_ctl/iic_dri_rx/N72/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Cout;2
-Q;2
-RSOUT;2
-Y;2
-CE;1
-CLK;1
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-RS;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[2]/opit_0_A2Q1;gopA2Q1
@@ -279858,19 +279922,22 @@ I14;1
RS;1
Inst
-ms72xx_ctl/iic_dri_rx/scl_out/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[15]/opit_0_AQ;gopAQ
Pin
CEOUT;2
+Cout;2
Q;2
RSOUT;2
-Z;2
+Y;2
CE;1
CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
+Cin;1
+I0;1
+I0X;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
@@ -280051,24 +280118,36 @@ I14;1
RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/N189_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_en/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/char_buf_writer_inst/N138_24/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_rx/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[1]/opit_0_A2Q1;gopA2Q1
@@ -280286,7 +280365,7 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N192/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N120_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -280521,7 +280600,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -280531,7 +280610,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate_A/N148_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_38/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -280563,7 +280642,7 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -280579,7 +280658,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[4]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -280643,17 +280722,23 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[5]_1/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N594_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -280824,7 +280909,7 @@ I14;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -280840,30 +280925,30 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q
@@ -280882,7 +280967,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_8[3]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -280892,7 +280977,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -280908,7 +280993,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -280924,23 +281009,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -280956,33 +281035,33 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N958_2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_modify_V/N63_mux8_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281124,24 +281203,36 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_L5Q_perm;gopL5Q
@@ -281176,7 +281267,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N937_2/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -281192,7 +281293,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -281208,7 +281309,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[14]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281218,7 +281319,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -281234,7 +281335,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -281250,59 +281351,40 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_16/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/N6.lt_4/gateop_perm;gopA
-Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
-
-Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N603/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_MUX4TO1Q;gopMUX4TO1Q
@@ -281474,7 +281556,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281729,17 +281811,23 @@ I3;1
I4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[13]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_modify_H/N76_mux8_2/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281749,23 +281837,27 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[10]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_h_data[6]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[5]_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -281781,7 +281873,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281791,23 +281883,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281817,23 +281903,17 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281843,7 +281923,7 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N58_mux9/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281853,7 +281933,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/N489_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281863,23 +281943,17 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[0]/opit_0_L5Q_perm;gopL5Q
+u_zoom_image/N368_mux4/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N133_inv/gateop_perm;gopLUT5
+u_ddr_addr_ctr/N72_17/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281889,7 +281963,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281899,7 +281973,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281909,7 +281983,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_18/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -281919,36 +281993,24 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N164_sum2/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/opit_0_inv_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N538_16/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5
@@ -281961,7 +282023,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[2]/gateop;gopLUT5
Pin
Z;2
L0;1
@@ -281971,20 +282033,14 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/N72_26/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5
@@ -281997,7 +282053,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N15/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -282007,7 +282063,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -282017,33 +282073,33 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/opit_0_inv_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5
+ms72xx_ctl/iic_dri_tx/N460/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -282053,7 +282109,7 @@ L3;1
L4;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N46_mux9/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -282063,23 +282119,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_start_i_ff/opit_0_L5Q_perm;gopL5Q
+ms72xx_ctl/iic_dri_tx/N493_or[0]_3/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_modify_V/N76_mux8_8/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -282089,23 +282139,17 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_10/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N610/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -282115,7 +282159,7 @@ L3;1
L4;1
Inst
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -282130,16 +282174,6 @@ L3;1
L4;1
RS;1
-Inst
-param_manager_inst/param_modify_H/N63_mux8_2/gateop_perm;gopLUT5
-Pin
-Z;2
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-
Inst
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_0/gateop_A2;gopA2
Pin
@@ -282744,7 +282778,7 @@ WR_EOP;1
WR_ERR;1
Inst
-param_manager_inst/param_modify_V/N63_mux8_7/gateop_perm;gopLUT5
+udp_wr_mem_inst/N695_8/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -282765,55 +282799,7 @@ D;1
RS;1
Inst
-udp_osd_inst/rgb_out[1]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/rgb_out[9]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/rgb_out[4]/opit_0_L5Q_perm;gopL5Q
-Pin
-CEOUT;2
-Q;2
-RSOUT;2
-Z;2
-CE;1
-CLK;1
-L0;1
-L1;1
-L2;1
-L3;1
-L4;1
-RS;1
-
-Inst
-udp_osd_inst/rgb_out[17]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[16]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -282845,7 +282831,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/rgb_out[11]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -282861,7 +282847,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/rgb_out[12]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[19]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -282877,7 +282863,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/rgb_out[20]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -282893,7 +282879,7 @@ L4;1
RS;1
Inst
-u_sync_vg/hdmi_image_data0[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -282909,7 +282895,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -282925,7 +282911,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[17]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -282941,7 +282927,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/rgb_out[18]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[12]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -282957,7 +282943,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -282973,7 +282959,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/rgb_out[19]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[18]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -282989,7 +282975,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/rgb_out[3]/opit_0_L5Q_perm;gopL5Q
+u_sync_vg/hdmi_image_data0[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283005,7 +282991,7 @@ L4;1
RS;1
Inst
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283021,28 +283007,23 @@ L4;1
RS;1
Inst
-udp_osd_inst/vs_out/opit_0;gopQ
+u_sync_vg/hdmi_image_data0[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
RSOUT;2
+Z;2
CE;1
CLK;1
-D;1
-RS;1
-
-Inst
-udp_wr_mem_inst/N224/gateop_perm;gopLUT5
-Pin
-Z;2
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_zoom/value[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[20]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283058,7 +283039,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_offsetX/pluse/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/rgb_out[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283074,23 +283055,48 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/flags[3]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/vs_out/opit_0;gopQ
Pin
CEOUT;2
Q;2
RSOUT;2
-Z;2
CE;1
CLK;1
+D;1
+RS;1
+
+Inst
+udp_wr_mem_inst/N30_1.fsub_1/gateop_A2;gopA2
+Pin
+Cout;2
+Y0;2
+Y1;2
+Cin;1
+I0X;1
+I1X;1
+I00;1
+I01;1
+I02;1
+I03;1
+I04;1
+I10;1
+I11;1
+I12;1
+I13;1
+I14;1
+
+Inst
+udp_wr_mem_inst/N404/gateop_perm;gopLUT5
+Pin
+Z;2
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_wr_mem_inst/N695_8/gateop_perm;gopLUT5
+udp_wr_mem_inst/N324/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283100,39 +283106,27 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/flags[4]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N124/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_offsetX/cnt[4]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N104/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_osd_startX/N148_5/gateop_perm;gopLUT5
+udp_wr_mem_inst/N44_11/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283142,7 +283136,17 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/flags[7]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate/N152_1/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_wr_mem_inst/flags[6]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283158,7 +283162,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/flags[8]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/flags[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283174,7 +283178,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_filiter1_mode/N119/gateop_perm;gopLUT5
+udp_wr_mem_inst/N264/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283184,7 +283188,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate/N152_5_9/gateop_perm;gopLUT5
+udp_wr_mem_inst/N224/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283204,23 +283208,17 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/flags[12]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_osd_char_width/N63_mux10_7/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_wr_mem_inst/N524_4/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/N154_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283230,17 +283228,23 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N524_2/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_osd_char_height/value[0]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/flags[13]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283256,23 +283260,17 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_width/value[1]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N727/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_wr_mem_inst/N404/gateop_perm;gopLUT5
+udp_wr_mem_inst/N44/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283282,23 +283280,17 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startX/value[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/N152_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_wr_mem_inst/N444/gateop_perm;gopLUT5
+image_filiter_inst/hybrid_filter_inst/N106_91/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283308,33 +283300,33 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/index[0]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N695_6/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_wr_mem_inst/N549_29/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[19]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_zoom/N63_mux9_9/gateop_perm;gopLUT5
+udp_wr_mem_inst/N464/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283344,7 +283336,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N549_25/gateop_perm;gopLUT5
+param_manager_inst/param_rotate_A/N148_5/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283354,17 +283346,23 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N524_3/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[22]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_wr_mem_inst/flags[13]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/flags[24]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283380,7 +283378,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/N84/gateop_perm;gopLUT5
+udp_wr_mem_inst/N524_2/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283390,7 +283388,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N524_10/gateop_perm;gopLUT5
+udp_wr_mem_inst/N524_3/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283400,7 +283398,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/pkt_data_cnt[0]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/index[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283416,7 +283414,7 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/N72_24_cpy/gateop_perm;gopLUT5
+udp_wr_mem_inst/N524_1/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283426,7 +283424,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/flags[2]/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283442,23 +283440,17 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[1]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[7]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_wr_mem_inst/N549_33/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283468,17 +283460,23 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N723/gateop_perm;gopLUT5
+u_zoom_image/wr_addr3[0]/opit_0_inv_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-u_ddr_rst/rst/opit_0_inv_L5Q_perm;gopL5Q
+udp_wr_mem_inst/pkt_data_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283494,7 +283492,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/data_count[0]/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283510,7 +283508,17 @@ L4;1
RS;1
Inst
-ms72xx_ctl/ms7210_ctl/cmd_index[0]/opit_0_inv_L5Q_perm;gopL5Q
+udp_wr_mem_inst/N723/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283526,7 +283534,7 @@ L4;1
RS;1
Inst
-param_manager_inst/param_zoom/N139_1/gateop_perm;gopLUT5
+udp_wr_mem_inst/N730/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283536,7 +283544,7 @@ L3;1
L4;1
Inst
-udp_wr_mem_inst/N730/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N90/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283546,7 +283554,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_zoom/value[0]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/flags[14]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283562,49 +283570,62 @@ L4;1
RS;1
Inst
-param_manager_inst/zoom_load/opit_0_L5Q_perm;gopL5Q
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_26/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-udp_wr_mem_inst/data_count[1]/opit_0_A2Q1;gopA2Q1
+udp_wr_mem_inst/data_count[7]/opit_0_AQ_perm;gopAQ
Pin
CEOUT;2
Cout;2
Q;2
RSOUT;2
-Y0;2
-Y1;2
+Y;2
CE;1
CLK;1
Cin;1
+I0;1
I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
+I1;1
+I2;1
+I3;1
+I4;1
RS;1
Inst
-udp_wr_mem_inst/data_count[3]/opit_0_A2Q21;gopA2Q2
+udp_wr_mem_inst/data_count[2]/opit_0_L5Q_perm;gopL5Q
+Pin
+CEOUT;2
+Q;2
+RSOUT;2
+Z;2
+CE;1
+CLK;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+RS;1
+
+Inst
+param_manager_inst/param_filiter1_mode/N59/gateop_perm;gopLUT5
+Pin
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
+
+Inst
+udp_wr_mem_inst/data_count[4]/opit_0_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -283631,7 +283652,7 @@ I14;1
RS;1
Inst
-udp_wr_mem_inst/data_count[5]/opit_0_A2Q21;gopA2Q2
+udp_wr_mem_inst/data_count[6]/opit_0_A2Q21;gopA2Q2
Pin
CEOUT;2
Cout;2
@@ -283658,47 +283679,30 @@ I14;1
RS;1
Inst
-udp_wr_mem_inst/data_count[7]/opit_0_A2Q21;gopA2Q2
+udp_wr_mem_inst/state_reg[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
-Cout;2
-Q0;2
-Q1;2
+Q;2
RSOUT;2
-Y0;2
-Y1;2
+Z;2
CE;1
CLK;1
-Cin;1
-I0X;1
-I1X;1
-I00;1
-I01;1
-I02;1
-I03;1
-I04;1
-I10;1
-I11;1
-I12;1
-I13;1
-I14;1
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
RS;1
Inst
-param_manager_inst/filiter1_mode_load/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_filiter1_mode/value[2:0]_5/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
udp_wr_mem_inst/flags[1]/opit_0_L5Q;gopL5Q
@@ -283717,27 +283721,39 @@ L4;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/N72_23/gateop_perm;gopLUT5
+param_manager_inst/param_offsetX/pluse/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_zoom/N63_mux9_8/gateop_perm;gopLUT5
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/pressed/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_rotate/N58/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_74/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283747,7 +283763,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startX/N139/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N63_mux10_7/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283757,7 +283773,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startX/N149_43_1/gateop_perm;gopLUT5
+param_manager_inst/param_osd_startX/N139/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283767,7 +283783,7 @@ L3;1
L4;1
Inst
-param_manager_inst/param_osd_startY/N149_38/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/N63_mux4/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283777,14 +283793,20 @@ L3;1
L4;1
Inst
-param_manager_inst/param_rotate/N152_5_6/gateop_perm;gopLUT5
+udp_wr_mem_inst/flags[8]/opit_0_L5Q;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_wr_mem_inst/flags[9]/opit_0_L5Q;gopL5Q
@@ -283803,33 +283825,33 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_height/N156_1/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_width/value[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_wr_mem_inst/flags[11]/opit_0_L5Q;gopL5Q
+param_manager_inst/key_debounce_key_left/N47_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_osd_char_width/N63_mux3/gateop_perm;gopLUT5
+param_manager_inst/param_osd_char_height/N138/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283839,7 +283861,7 @@ L3;1
L4;1
Inst
-image_filiter_inst/hybrid_filter_inst/N162_89/gateop_perm;gopLUT5
+param_manager_inst/param_rotate_A/N63_mux9_9/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -283849,7 +283871,7 @@ L3;1
L4;1
Inst
-param_manager_inst/rotate_A_load/opit_0_L5Q_perm;gopL5Q
+param_manager_inst/param_rotate_A/value[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283865,7 +283887,7 @@ L4;1
RS;1
Inst
-param_manager_inst/offsetX_load/opit_0_L5Q_perm;gopL5Q
+u_rotate_image/image_w_blank_valid/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283881,7 +283903,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/flags[16]/opit_0_L5Q;gopL5Q
+param_manager_inst/param_offsetY/value[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283897,30 +283919,30 @@ L4;1
RS;1
Inst
-param_manager_inst/param_osd_char_height/N63_mux10_4/gateop_perm;gopLUT5
+param_manager_inst/filiter1_mode_load/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-udp_wr_mem_inst/flags[18]/opit_0_L5Q;gopL5Q
+param_manager_inst/param_modify_H/N148_1/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
param_manager_inst/modify_H_load/opit_0_L5Q_perm;gopL5Q
@@ -283939,7 +283961,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/flags[20]/opit_0_L5Q;gopL5Q
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283971,17 +283993,23 @@ L4;1
RS;1
Inst
-param_manager_inst/param_modify_S/N139_2/gateop_perm;gopLUT5
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[1]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-param_manager_inst/param_modify_V/value[0]/opit_0_L5Q_perm;gopL5Q
+udp_wr_mem_inst/flags[23]/opit_0_L5Q;gopL5Q
Pin
CEOUT;2
Q;2
@@ -283997,30 +284025,30 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/flags[24]/opit_0_L5Q;gopL5Q
+param_manager_inst/param_rotate/N102_9/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-param_manager_inst/param_modify_H/N72/gateop_perm;gopLUT5
+param_manager_inst/param_rotate/pluse/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
udp_wr_mem_inst/index[1]/opit_0_A2Q1;gopA2Q1
@@ -285549,17 +285577,14 @@ D;1
RS;1
Inst
-param_manager_inst/param_zoom/N149_10_9/gateop_perm;gopA
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_5/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
udp_wr_mem_inst/pkt_data_cnt[1]/opit_0_A2Q1;gopA2Q1
@@ -285810,7 +285835,7 @@ L4;1
RS;1
Inst
-udp_wr_mem_inst/N695_6/gateop_perm;gopLUT5
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_22/gateop_perm;gopLUT5
Pin
Z;2
L0;1
@@ -285933,7 +285958,7 @@ L4;1
RS;1
Inst
-vs_down_delay_cnt[11]/opit_0_L5Q_perm;gopL5Q
+vs_pos_delay_cnt[3]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -285949,7 +285974,7 @@ L4;1
RS;1
Inst
-vs_pos_delay_cnt[6]/opit_0_L5Q_perm;gopL5Q
+vs_down_delay_cnt[10]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -285965,7 +285990,7 @@ L4;1
RS;1
Inst
-vs_pos_delay_cnt[5]/opit_0_L5Q_perm;gopL5Q
+vs_pos_delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -285981,7 +286006,7 @@ L4;1
RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N87.lt_2/gateop_perm;gopA
+u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_perm;gopA
Pin
Cout;2
Y;2
@@ -285994,7 +286019,7 @@ I3;1
I4;1
Inst
-vs_pos_delay_cnt[0]/opit_0_L5Q_perm;gopL5Q
+vs_down_delay_cnt[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -286010,7 +286035,7 @@ L4;1
RS;1
Inst
-wr0_vs/opit_0_L5Q_perm;gopL5Q
+vs_pos_delay_cnt[9]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -286065,7 +286090,7 @@ IN;1
MI;1
Inst
-vs_pos_delay_cnt[9]/opit_0_L5Q_perm;gopL5Q
+vs_pos_delay_cnt[8]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -286097,7 +286122,7 @@ L4;1
RS;1
Inst
-vs_pos_delay_cnt[3]/opit_0_L5Q_perm;gopL5Q
+vs_pos_delay_cnt[5]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -286129,14 +286154,20 @@ L4;1
RS;1
Inst
-N104_mux11_9/gateop_perm;gopLUT5
+vs_down_delay_cnt[8]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
vs_pos_delay_cnt[7]/opit_0_L5Q_perm;gopL5Q
@@ -286155,7 +286186,7 @@ L4;1
RS;1
Inst
-vs_down_delay_cnt[8]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -286171,7 +286202,7 @@ L4;1
RS;1
Inst
-vs_pos_delay_cnt[10]/opit_0_L5Q_perm;gopL5Q
+u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -286187,17 +286218,23 @@ L4;1
RS;1
Inst
-N104_mux11_12/gateop_perm;gopLUT5
+vs_pos_delay_cnt[10]/opit_0_L5Q_perm;gopL5Q
Pin
+CEOUT;2
+Q;2
+RSOUT;2
Z;2
+CE;1
+CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
+RS;1
Inst
-vs_pos_delay_cnt[11]/opit_0_L5Q_perm;gopL5Q
+u_hdm_in_rst/rst/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -286213,7 +286250,7 @@ L4;1
RS;1
Inst
-vs_pos_delay_cnt[8]/opit_0_L5Q_perm;gopL5Q
+vs_pos_delay_cnt[11]/opit_0_L5Q_perm;gopL5Q
Pin
CEOUT;2
Q;2
@@ -286229,33 +286266,24 @@ L4;1
RS;1
Inst
-u_hdmi_in_top/hdmi_in_en/opit_0_L5Q_perm;gopL5Q
+N119_mux11_12/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
-image_filiter_inst/hybrid_filter_inst/median_finder9_g/N155.lt_2/gateop_perm;gopA
+u_ov5640/u_mix_image/N311_8/gateop_perm;gopLUT5
Pin
-Cout;2
-Y;2
-Cin;1
-I0;1
-I0X;1
-I1;1
-I2;1
-I3;1
-I4;1
+Z;2
+L0;1
+L1;1
+L2;1
+L3;1
+L4;1
Inst
zoom_ff0[0]/opit_0;gopQ
@@ -286588,20 +286616,14 @@ D;1
RS;1
Inst
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5
Pin
-CEOUT;2
-Q;2
-RSOUT;2
Z;2
-CE;1
-CLK;1
L0;1
L1;1
L2;1
L3;1
L4;1
-RS;1
Inst
zoom_vs_out0/opit_0;gopQ
@@ -289210,6 +289232,16 @@ VCC_516;gopVCC
Pin
Z;2
+Inst
+VCC_517;gopVCC
+Pin
+Z;2
+
+Inst
+VCC_518;gopVCC
+Pin
+Z;2
+
Inst
GND_0;gopGND
Pin
@@ -295360,6 +295392,36 @@ GND_1229;gopGND
Pin
Z;2
+Inst
+GND_1230;gopGND
+Pin
+Z;2
+
+Inst
+GND_1231;gopGND
+Pin
+Z;2
+
+Inst
+GND_1232;gopGND
+Pin
+Z;2
+
+Inst
+GND_1233;gopGND
+Pin
+Z;2
+
+Inst
+GND_1234;gopGND
+Pin
+Z;2
+
+Inst
+GND_1235;gopGND
+Pin
+Z;2
+
Inst
CLKROUTE_0;gopCLKROUTE
Pin
@@ -295402,6 +295464,34 @@ Z;2
L7in;1
M;1
+Inst
+CLKROUTE_6;gopCLKROUTE
+Pin
+Z;2
+L7in;1
+M;1
+
+Inst
+CLKROUTE_7;gopCLKROUTE
+Pin
+Z;2
+L7in;1
+M;1
+
+Inst
+CLKROUTE_8;gopCLKROUTE
+Pin
+Z;2
+L7in;1
+M;1
+
+Inst
+CLKROUTE_9;gopCLKROUTE
+Pin
+Z;2
+L7in;1
+M;1
+
Inst
USCMROUTE_0;gopCLKBUFG
Pin
@@ -295425,7 +295515,7 @@ N24;
N104;
N119;
N139_0;
-N298;
+N299;
U_HDMI_PLL/u_pll_e3/ntCLKFB;
_N0;
_N1;
@@ -295506,14 +295596,14 @@ _N75;
_N76;
_N77;
_N78;
-_N79;
-_N84;
+_N83;
+_N87;
_N88;
_N89;
_N90;
_N91;
_N92;
-_N93;
+_N94;
_N95;
_N96;
_N97;
@@ -295522,24 +295612,18 @@ _N99;
_N100;
_N101;
_N102;
-_N103;
+_N104;
_N105;
-_N2195;
-_N2203;
-_N2209;
-_N2277;
-_N17116;
-_N17118;
-_N17120;
-_N17122;
-_N17124;
-_N17126;
+_N2197;
+_N2205;
+_N2211;
+_N2279;
+_N17128;
_N17130;
_N17132;
_N17134;
_N17136;
_N17138;
-_N17140;
_N17142;
_N17144;
_N17146;
@@ -295548,288 +295632,292 @@ _N17150;
_N17152;
_N17154;
_N17156;
-_N18115;
-_N81412_3;
-_N81412_5;
-_N81413_3;
-_N81413_5;
-_N81414_3;
-_N81414_5;
-_N81415_3;
-_N81415_5;
-_N97085;
-_N97297;
-_N97340;
-_N103547;
-_N103551;
-_N103709;
-_N103711;
-_N103720;
-_N103722;
-_N103731;
-_N103733;
-_N103742;
-_N103743;
-_N103744;
-_N103920;
-_N103957;
-_N103958;
-_N103959;
-_N105268;
-_N105817;
-_N106355;
-_N106490;
-_N106518;
+_N17158;
+_N17160;
+_N17162;
+_N17164;
+_N17166;
+_N17168;
+_N82185_3;
+_N82185_5;
+_N82186_3;
+_N82186_5;
+_N82187_3;
+_N82187_5;
+_N82188_3;
+_N82188_5;
+_N98107;
+_N98118;
+_N104359;
+_N104363;
+_N104528;
+_N104530;
+_N104539;
+_N104541;
+_N104550;
+_N104552;
+_N104561;
+_N104562;
+_N104563;
+_N104744;
+_N104781;
+_N104782;
+_N104783;
+_N106081;
+_N106639;
+_N107308;
+_N107336;
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N19;
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N19_inv_1;
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/_N13455;
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/_N13457;
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/_N13459;
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/_N13461;
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/_N18651;
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/_N96639;
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N133;
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N140;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/_N13472;
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/_N13474;
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/_N13476;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/_N18755;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/_N18761;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/_N107206;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/_N13478;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/_N18737;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/_N18743;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/_N108028;
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/N6;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18853;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18854;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18855;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18856;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18857;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18858;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18859;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18860;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18817;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18818;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18819;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18820;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18821;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18822;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18823;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/_N18824;
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/N6;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18873;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18874;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18875;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18876;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18877;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18878;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18879;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18880;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18837;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18838;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18839;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18840;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18841;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18842;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18843;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/_N18844;
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/N6;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18895;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18896;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18897;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18898;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18899;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18900;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18901;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18902;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18859;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18860;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18861;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18862;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18863;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18864;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18865;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/_N18866;
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/N6;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18919;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18920;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18921;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18922;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18923;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18924;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18925;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18926;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18883;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18884;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18885;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18886;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18887;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18888;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18889;
+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/_N18890;
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N6;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/_N18945;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/_N18946;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/_N18947;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/_N18948;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/_N18949;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/_N18950;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/_N18951;
-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/_N18952;
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-adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/_N19899;
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+adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/_N19834;
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adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/N6;
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adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N46;
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-adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N13433;
+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N13430;
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+adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N13441;
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axi_rst;
b_in_ibuf[3]/ntD;
b_in_ibuf[4]/ntD;
@@ -295892,6 +295980,7 @@ cmos2_scl_iobuf/ntO;
cmos2_scl_iobuf/ntT;
cmos2_vsync;
cmos2_vsync_ibuf/ntD;
+ddr_clk;
ddr_rst;
de_in;
de_in_ibuf/ntD;
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image_filiter_inst/hybrid_filter_inst/N118;
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image_filiter_inst/hybrid_filter_inst/N146;
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image_filiter_inst/hybrid_filter_inst/median_finder9_b/N35;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/N37;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/N39;
@@ -296035,52 +296124,52 @@ image_filiter_inst/hybrid_filter_inst/median_finder9_b/N111;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/N155;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/N161;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/N167;
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+image_filiter_inst/hybrid_filter_inst/median_finder9_b/_N103223_1;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N4;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N17;
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image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N4;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N5;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N8;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15;
image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N17;
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image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N4;
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image_filiter_inst/matrix_valid;
image_filiter_inst/multiline_buffer_inst/N21;
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image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/wfull;
image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21;
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image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/wfull;
image_filiter_inst/multiline_buffer_inst/rst_s1;
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image_filiter_inst2/hybrid_filter_inst/N142;
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+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/_N103576_1;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N17;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N17944;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N25797;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N25819;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N95911;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N25752;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N26026;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N26030;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N96725;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N5;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N17;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N22385;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N22389;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N26062;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N95967;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N17953;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N17961;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N25211;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N96760;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N4;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15;
image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N17;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N20433;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N20437;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N25357;
-image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N95892;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N20027;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N20031;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N25461;
+image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N96724;
image_filiter_inst2/matrix_valid;
image_filiter_inst2/multiline_buffer_inst/N21;
image_filiter_inst2/multiline_buffer_inst/N48;
@@ -296383,50 +296472,50 @@ image_filiter_inst2/multiline_buffer_inst/N216_inv;
image_filiter_inst2/multiline_buffer_inst/N229;
image_filiter_inst2/multiline_buffer_inst/N271;
image_filiter_inst2/multiline_buffer_inst/N272;
-image_filiter_inst2/multiline_buffer_inst/_N13617;
-image_filiter_inst2/multiline_buffer_inst/_N13619;
-image_filiter_inst2/multiline_buffer_inst/_N13621;
-image_filiter_inst2/multiline_buffer_inst/_N13623;
-image_filiter_inst2/multiline_buffer_inst/_N13635;
-image_filiter_inst2/multiline_buffer_inst/_N13637;
-image_filiter_inst2/multiline_buffer_inst/_N13639;
-image_filiter_inst2/multiline_buffer_inst/_N13641;
-image_filiter_inst2/multiline_buffer_inst/_N15738;
-image_filiter_inst2/multiline_buffer_inst/_N15740;
-image_filiter_inst2/multiline_buffer_inst/_N15742;
-image_filiter_inst2/multiline_buffer_inst/_N15960;
-image_filiter_inst2/multiline_buffer_inst/_N15962;
-image_filiter_inst2/multiline_buffer_inst/_N84159;
-image_filiter_inst2/multiline_buffer_inst/_N97104;
-image_filiter_inst2/multiline_buffer_inst/_N98270;
-image_filiter_inst2/multiline_buffer_inst/_N103753;
-image_filiter_inst2/multiline_buffer_inst/_N103754;
-image_filiter_inst2/multiline_buffer_inst/_N103759;
-image_filiter_inst2/multiline_buffer_inst/_N103916;
+image_filiter_inst2/multiline_buffer_inst/_N13614;
+image_filiter_inst2/multiline_buffer_inst/_N13616;
+image_filiter_inst2/multiline_buffer_inst/_N13618;
+image_filiter_inst2/multiline_buffer_inst/_N13620;
+image_filiter_inst2/multiline_buffer_inst/_N13625;
+image_filiter_inst2/multiline_buffer_inst/_N13627;
+image_filiter_inst2/multiline_buffer_inst/_N13629;
+image_filiter_inst2/multiline_buffer_inst/_N13631;
+image_filiter_inst2/multiline_buffer_inst/_N15983;
+image_filiter_inst2/multiline_buffer_inst/_N15985;
+image_filiter_inst2/multiline_buffer_inst/_N15987;
+image_filiter_inst2/multiline_buffer_inst/_N15992;
+image_filiter_inst2/multiline_buffer_inst/_N15994;
+image_filiter_inst2/multiline_buffer_inst/_N84996;
+image_filiter_inst2/multiline_buffer_inst/_N97883;
+image_filiter_inst2/multiline_buffer_inst/_N101318;
+image_filiter_inst2/multiline_buffer_inst/_N104576;
+image_filiter_inst2/multiline_buffer_inst/_N104577;
+image_filiter_inst2/multiline_buffer_inst/_N104582;
+image_filiter_inst2/multiline_buffer_inst/_N104740;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13396;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13398;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13400;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13402;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13404;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13409;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13406;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13411;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13413;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13415;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13417;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13419;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/rempty;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/wfull;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16358;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16360;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16362;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16364;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16366;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16371;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16373;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16375;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16377;
-image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16379;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16529;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16531;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16533;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16535;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16537;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16542;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16544;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16546;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16548;
+image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16550;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/rempty;
image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/wfull;
image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10:0]_or;
@@ -296484,8 +296573,9 @@ ms72xx_ctl.iic_sda_tri/ntT;
ms72xx_ctl.iic_tx_sda_tri/ntI;
ms72xx_ctl.iic_tx_sda_tri/ntO;
ms72xx_ctl.iic_tx_sda_tri/ntT;
-ms72xx_ctl/_N95852;
-ms72xx_ctl/_N96143;
+ms72xx_ctl/_N96626;
+ms72xx_ctl/_N96633;
+ms72xx_ctl/_N96740;
ms72xx_ctl/busy_rx;
ms72xx_ctl/busy_tx;
ms72xx_ctl/byte_over_rx;
@@ -296502,26 +296592,26 @@ ms72xx_ctl/iic_dri_rx/_N9;
ms72xx_ctl/iic_dri_rx/_N17985;
ms72xx_ctl/iic_dri_rx/_N17986;
ms72xx_ctl/iic_dri_rx/_N17987;
-ms72xx_ctl/iic_dri_rx/_N19828;
-ms72xx_ctl/iic_dri_rx/_N19831;
-ms72xx_ctl/iic_dri_rx/_N29346;
-ms72xx_ctl/iic_dri_rx/_N29348;
+ms72xx_ctl/iic_dri_rx/_N19775;
+ms72xx_ctl/iic_dri_rx/_N19778;
+ms72xx_ctl/iic_dri_rx/_N29321;
+ms72xx_ctl/iic_dri_rx/_N29323;
ms72xx_ctl/iic_dri_rx/_N30788;
ms72xx_ctl/iic_dri_rx/_N30794;
ms72xx_ctl/iic_dri_rx/_N30799;
ms72xx_ctl/iic_dri_rx/_N30805;
ms72xx_ctl/iic_dri_rx/_N30810;
-ms72xx_ctl/iic_dri_rx/_N81582;
-ms72xx_ctl/iic_dri_rx/_N81586;
-ms72xx_ctl/iic_dri_rx/_N81608;
-ms72xx_ctl/iic_dri_rx/_N95846;
-ms72xx_ctl/iic_dri_rx/_N96754;
-ms72xx_ctl/iic_dri_rx/_N102144_2;
-ms72xx_ctl/iic_dri_rx/_N103288;
-ms72xx_ctl/iic_dri_rx/_N103986;
-ms72xx_ctl/iic_dri_rx/_N104016;
-ms72xx_ctl/iic_dri_rx/_N104046;
-ms72xx_ctl/iic_dri_rx/_N104065;
+ms72xx_ctl/iic_dri_rx/_N82353;
+ms72xx_ctl/iic_dri_rx/_N82357;
+ms72xx_ctl/iic_dri_rx/_N82374;
+ms72xx_ctl/iic_dri_rx/_N96619;
+ms72xx_ctl/iic_dri_rx/_N97518;
+ms72xx_ctl/iic_dri_rx/_N102965_2;
+ms72xx_ctl/iic_dri_rx/_N104100;
+ms72xx_ctl/iic_dri_rx/_N104811;
+ms72xx_ctl/iic_dri_rx/_N104841;
+ms72xx_ctl/iic_dri_rx/_N104871;
+ms72xx_ctl/iic_dri_rx/_N104890;
ms72xx_ctl/iic_dri_rx/dsu;
ms72xx_ctl/iic_dri_rx/full_cycle;
ms72xx_ctl/iic_dri_rx/half_cycle;
@@ -296548,19 +296638,18 @@ ms72xx_ctl/iic_dri_tx/_N17994;
ms72xx_ctl/iic_dri_tx/_N17995;
ms72xx_ctl/iic_dri_tx/_N17996;
ms72xx_ctl/iic_dri_tx/_N30831;
-ms72xx_ctl/iic_dri_tx/_N81617;
-ms72xx_ctl/iic_dri_tx/_N81621;
-ms72xx_ctl/iic_dri_tx/_N81641;
-ms72xx_ctl/iic_dri_tx/_N95847;
-ms72xx_ctl/iic_dri_tx/_N96238;
-ms72xx_ctl/iic_dri_tx/_N103294;
-ms72xx_ctl/iic_dri_tx/_N104381;
-ms72xx_ctl/iic_dri_tx/_N104416;
-ms72xx_ctl/iic_dri_tx/_N104421;
-ms72xx_ctl/iic_dri_tx/_N104427;
-ms72xx_ctl/iic_dri_tx/_N104432;
-ms72xx_ctl/iic_dri_tx/_N104434;
-ms72xx_ctl/iic_dri_tx/_N104463;
+ms72xx_ctl/iic_dri_tx/_N82383;
+ms72xx_ctl/iic_dri_tx/_N82387;
+ms72xx_ctl/iic_dri_tx/_N82418;
+ms72xx_ctl/iic_dri_tx/_N96620;
+ms72xx_ctl/iic_dri_tx/_N104106;
+ms72xx_ctl/iic_dri_tx/_N105220;
+ms72xx_ctl/iic_dri_tx/_N105255;
+ms72xx_ctl/iic_dri_tx/_N105260;
+ms72xx_ctl/iic_dri_tx/_N105266;
+ms72xx_ctl/iic_dri_tx/_N105271;
+ms72xx_ctl/iic_dri_tx/_N105273;
+ms72xx_ctl/iic_dri_tx/_N105300;
ms72xx_ctl/iic_dri_tx/pluse_1d;
ms72xx_ctl/iic_dri_tx/pluse_2d;
ms72xx_ctl/iic_dri_tx/pluse_3d;
@@ -296575,6 +296664,7 @@ ms72xx_ctl/iic_trig_tx;
ms72xx_ctl/ms7200_ctl/N8;
ms72xx_ctl/ms7200_ctl/N261;
ms72xx_ctl/ms7200_ctl/N1321;
+ms72xx_ctl/ms7200_ctl/N1359;
ms72xx_ctl/ms7200_ctl/N1366;
ms72xx_ctl/ms7200_ctl/N1386;
ms72xx_ctl/ms7200_ctl/N1388;
@@ -296582,6 +296672,7 @@ ms72xx_ctl/ms7200_ctl/N1415;
ms72xx_ctl/ms7200_ctl/N1797;
ms72xx_ctl/ms7200_ctl/N1845;
ms72xx_ctl/ms7200_ctl/N1872;
+ms72xx_ctl/ms7200_ctl/N1873;
ms72xx_ctl/ms7200_ctl/N1879;
ms72xx_ctl/ms7200_ctl/N1895;
ms72xx_ctl/ms7200_ctl/N1918;
@@ -296592,33 +296683,31 @@ ms72xx_ctl/ms7200_ctl/N2070;
ms72xx_ctl/ms7200_ctl/N2076;
ms72xx_ctl/ms7200_ctl/N2083;
ms72xx_ctl/ms7200_ctl/N2085;
-ms72xx_ctl/ms7200_ctl/_N13805;
-ms72xx_ctl/ms7200_ctl/_N13807;
-ms72xx_ctl/ms7200_ctl/_N13809;
+ms72xx_ctl/ms7200_ctl/_N13823;
+ms72xx_ctl/ms7200_ctl/_N13825;
+ms72xx_ctl/ms7200_ctl/_N13827;
ms72xx_ctl/ms7200_ctl/_N17171;
ms72xx_ctl/ms7200_ctl/_N17173;
ms72xx_ctl/ms7200_ctl/_N17175;
ms72xx_ctl/ms7200_ctl/_N17177;
-ms72xx_ctl/ms7200_ctl/_N18000;
-ms72xx_ctl/ms7200_ctl/_N18002;
-ms72xx_ctl/ms7200_ctl/_N84747;
-ms72xx_ctl/ms7200_ctl/_N95810;
-ms72xx_ctl/ms7200_ctl/_N95853;
-ms72xx_ctl/ms7200_ctl/_N95857;
-ms72xx_ctl/ms7200_ctl/_N95866;
-ms72xx_ctl/ms7200_ctl/_N96041;
-ms72xx_ctl/ms7200_ctl/_N96431;
-ms72xx_ctl/ms7200_ctl/_N96695;
-ms72xx_ctl/ms7200_ctl/_N100381;
-ms72xx_ctl/ms7200_ctl/_N103976;
-ms72xx_ctl/ms7200_ctl/_N103981;
-ms72xx_ctl/ms7200_ctl/_N104002;
-ms72xx_ctl/ms7200_ctl/_N104013;
-ms72xx_ctl/ms7200_ctl/_N104061;
-ms72xx_ctl/ms7200_ctl/_N104063;
-ms72xx_ctl/ms7200_ctl/_N104071;
-ms72xx_ctl/ms7200_ctl/_N104076;
-ms72xx_ctl/ms7200_ctl/_N104081;
+ms72xx_ctl/ms7200_ctl/_N96603;
+ms72xx_ctl/ms7200_ctl/_N96627;
+ms72xx_ctl/ms7200_ctl/_N96632;
+ms72xx_ctl/ms7200_ctl/_N96696;
+ms72xx_ctl/ms7200_ctl/_N96761;
+ms72xx_ctl/ms7200_ctl/_N97453;
+ms72xx_ctl/ms7200_ctl/_N104787;
+ms72xx_ctl/ms7200_ctl/_N104790;
+ms72xx_ctl/ms7200_ctl/_N104793;
+ms72xx_ctl/ms7200_ctl/_N104806;
+ms72xx_ctl/ms7200_ctl/_N104827;
+ms72xx_ctl/ms7200_ctl/_N104838;
+ms72xx_ctl/ms7200_ctl/_N104861;
+ms72xx_ctl/ms7200_ctl/_N104886;
+ms72xx_ctl/ms7200_ctl/_N104888;
+ms72xx_ctl/ms7200_ctl/_N104896;
+ms72xx_ctl/ms7200_ctl/_N104901;
+ms72xx_ctl/ms7200_ctl/_N104906;
ms72xx_ctl/ms7200_ctl/busy_1d;
ms72xx_ctl/ms7200_ctl/busy_falling;
ms72xx_ctl/ms7200_ctl/freq_ensure;
@@ -296634,8 +296723,9 @@ ms72xx_ctl/ms7210_ctl/N580;
ms72xx_ctl/ms7210_ctl/N586;
ms72xx_ctl/ms7210_ctl/N589;
ms72xx_ctl/ms7210_ctl/N591;
-ms72xx_ctl/ms7210_ctl/_N13830;
-ms72xx_ctl/ms7210_ctl/_N13832;
+ms72xx_ctl/ms7210_ctl/_N2723;
+ms72xx_ctl/ms7210_ctl/_N14011;
+ms72xx_ctl/ms7210_ctl/_N14013;
ms72xx_ctl/ms7210_ctl/_N17181;
ms72xx_ctl/ms7210_ctl/_N17183;
ms72xx_ctl/ms7210_ctl/_N17185;
@@ -296646,15 +296736,15 @@ ms72xx_ctl/ms7210_ctl/_N17193;
ms72xx_ctl/ms7210_ctl/_N17195;
ms72xx_ctl/ms7210_ctl/_N17197;
ms72xx_ctl/ms7210_ctl/_N17199;
-ms72xx_ctl/ms7210_ctl/_N95867;
-ms72xx_ctl/ms7210_ctl/_N104392;
-ms72xx_ctl/ms7210_ctl/_N104397;
-ms72xx_ctl/ms7210_ctl/_N104401;
-ms72xx_ctl/ms7210_ctl/_N104405;
-ms72xx_ctl/ms7210_ctl/_N104406;
-ms72xx_ctl/ms7210_ctl/_N104446;
-ms72xx_ctl/ms7210_ctl/_N104448;
-ms72xx_ctl/ms7210_ctl/_N104459;
+ms72xx_ctl/ms7210_ctl/_N96642;
+ms72xx_ctl/ms7210_ctl/_N105231;
+ms72xx_ctl/ms7210_ctl/_N105236;
+ms72xx_ctl/ms7210_ctl/_N105240;
+ms72xx_ctl/ms7210_ctl/_N105244;
+ms72xx_ctl/ms7210_ctl/_N105245;
+ms72xx_ctl/ms7210_ctl/_N105283;
+ms72xx_ctl/ms7210_ctl/_N105285;
+ms72xx_ctl/ms7210_ctl/_N105296;
ms72xx_ctl/ms7210_ctl/busy_1d;
ms72xx_ctl/ms7210_ctl/busy_falling;
ms72xx_ctl/rstn;
@@ -296791,6 +296881,7 @@ ntclkbufg_4;
ntclkbufg_5;
ntclkbufg_6;
ntclkbufg_7;
+ntclkbufg_8;
ntclkgate_0;
param_manager_inst/N30;
param_manager_inst/N33;
@@ -296798,25 +296889,28 @@ param_manager_inst/N314;
param_manager_inst/N335;
param_manager_inst/N344;
param_manager_inst/N345;
-param_manager_inst/_N2742;
-param_manager_inst/_N2756;
-param_manager_inst/_N3647;
-param_manager_inst/_N3793;
-param_manager_inst/_N13814;
-param_manager_inst/_N13816;
-param_manager_inst/_N13818;
-param_manager_inst/_N13820;
-param_manager_inst/_N13822;
-param_manager_inst/_N13824;
-param_manager_inst/_N13826;
-param_manager_inst/_N96763;
-param_manager_inst/_N104340;
-param_manager_inst/_N104342;
-param_manager_inst/_N104344;
-param_manager_inst/_N104351;
-param_manager_inst/_N104501;
-param_manager_inst/_N107262;
-param_manager_inst/_N107263;
+param_manager_inst/_N2738;
+param_manager_inst/_N2752;
+param_manager_inst/_N3230;
+param_manager_inst/_N3669;
+param_manager_inst/_N3811;
+param_manager_inst/_N13832;
+param_manager_inst/_N13834;
+param_manager_inst/_N13836;
+param_manager_inst/_N13838;
+param_manager_inst/_N13840;
+param_manager_inst/_N13842;
+param_manager_inst/_N13844;
+param_manager_inst/_N97529;
+param_manager_inst/_N105179;
+param_manager_inst/_N105181;
+param_manager_inst/_N105183;
+param_manager_inst/_N105190;
+param_manager_inst/_N105338;
+param_manager_inst/_N108087;
+param_manager_inst/_N108088;
+param_manager_inst/_N108109;
+param_manager_inst/_N108110;
param_manager_inst/changed_left;
param_manager_inst/changed_right;
param_manager_inst/clk_ms;
@@ -296830,9 +296924,9 @@ param_manager_inst/key_debounce_key_left/N20;
param_manager_inst/key_debounce_key_left/N47;
param_manager_inst/key_debounce_key_left/N87;
param_manager_inst/key_debounce_key_left/N88;
-param_manager_inst/key_debounce_key_left/_N2843;
+param_manager_inst/key_debounce_key_left/_N2839;
param_manager_inst/key_debounce_key_left/_N26996;
-param_manager_inst/key_debounce_key_left/_N104367;
+param_manager_inst/key_debounce_key_left/_N105206;
param_manager_inst/key_debounce_key_left/clk_ms_ff0;
param_manager_inst/key_debounce_key_left/clk_ms_ff1;
param_manager_inst/key_debounce_key_left/key_ff0;
@@ -296842,18 +296936,18 @@ param_manager_inst/key_debounce_key_restore/N20;
param_manager_inst/key_debounce_key_restore/N47;
param_manager_inst/key_debounce_key_restore/N87;
param_manager_inst/key_debounce_key_restore/N88;
-param_manager_inst/key_debounce_key_restore/_N2892;
+param_manager_inst/key_debounce_key_restore/_N2888;
param_manager_inst/key_debounce_key_restore/_N27008;
-param_manager_inst/key_debounce_key_restore/_N104374;
+param_manager_inst/key_debounce_key_restore/_N105213;
param_manager_inst/key_debounce_key_restore/key_ff0;
param_manager_inst/key_debounce_key_restore/key_ff1;
param_manager_inst/key_debounce_key_right/N20;
param_manager_inst/key_debounce_key_right/N47;
param_manager_inst/key_debounce_key_right/N87;
param_manager_inst/key_debounce_key_right/N88;
-param_manager_inst/key_debounce_key_right/_N2941;
+param_manager_inst/key_debounce_key_right/_N2937;
param_manager_inst/key_debounce_key_right/_N27020;
-param_manager_inst/key_debounce_key_right/_N104359;
+param_manager_inst/key_debounce_key_right/_N105198;
param_manager_inst/key_debounce_key_right/key_ff0;
param_manager_inst/key_debounce_key_right/key_ff1;
param_manager_inst/modify_H_flags_ff0;
@@ -296901,6 +296995,7 @@ param_manager_inst/osd_startY_flags_ff1;
param_manager_inst/osd_startY_flags_ff2;
param_manager_inst/osd_startY_flags_ff3;
param_manager_inst/osd_startY_load;
+param_manager_inst/param_filiter1_mode/N59;
param_manager_inst/param_filiter1_mode/N102;
param_manager_inst/param_filiter1_mode/N111;
param_manager_inst/param_filiter1_mode/N116;
@@ -296911,27 +297006,28 @@ param_manager_inst/param_filiter1_mode/N149;
param_manager_inst/param_filiter1_mode/N152;
param_manager_inst/param_filiter1_mode/N153;
param_manager_inst/param_filiter1_mode/N161;
-param_manager_inst/param_filiter1_mode/_N81667;
-param_manager_inst/param_filiter1_mode/_N105304;
-param_manager_inst/param_filiter1_mode/_N105307;
+param_manager_inst/param_filiter1_mode/_N37753;
+param_manager_inst/param_filiter1_mode/_N82454;
+param_manager_inst/param_filiter1_mode/_N106117;
+param_manager_inst/param_filiter1_mode/_N106120;
param_manager_inst/param_filiter1_mode/changed_down;
param_manager_inst/param_filiter1_mode/changed_up;
param_manager_inst/param_filiter1_mode/key_debounce_inst1/N20;
param_manager_inst/param_filiter1_mode/key_debounce_inst1/N47;
param_manager_inst/param_filiter1_mode/key_debounce_inst1/N87;
param_manager_inst/param_filiter1_mode/key_debounce_inst1/N88;
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/_N3006;
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/_N3002;
param_manager_inst/param_filiter1_mode/key_debounce_inst1/_N27038;
-param_manager_inst/param_filiter1_mode/key_debounce_inst1/_N104474;
+param_manager_inst/param_filiter1_mode/key_debounce_inst1/_N105311;
param_manager_inst/param_filiter1_mode/key_debounce_inst1/key_ff0;
param_manager_inst/param_filiter1_mode/key_debounce_inst1/key_ff1;
param_manager_inst/param_filiter1_mode/key_debounce_inst2/N20;
param_manager_inst/param_filiter1_mode/key_debounce_inst2/N47;
param_manager_inst/param_filiter1_mode/key_debounce_inst2/N87;
param_manager_inst/param_filiter1_mode/key_debounce_inst2/N88;
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/_N3055;
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/_N3051;
param_manager_inst/param_filiter1_mode/key_debounce_inst2/_N27050;
-param_manager_inst/param_filiter1_mode/key_debounce_inst2/_N104491;
+param_manager_inst/param_filiter1_mode/key_debounce_inst2/_N105328;
param_manager_inst/param_filiter1_mode/key_debounce_inst2/key_ff0;
param_manager_inst/param_filiter1_mode/key_debounce_inst2/key_ff1;
param_manager_inst/param_filiter1_mode/pluse;
@@ -296941,9 +297037,8 @@ param_manager_inst/param_filiter2_mode/N140;
param_manager_inst/param_filiter2_mode/N149;
param_manager_inst/param_filiter2_mode/N152;
param_manager_inst/param_filiter2_mode/N153;
-param_manager_inst/param_filiter2_mode/_N81678;
+param_manager_inst/param_filiter2_mode/_N82459;
param_manager_inst/param_modify_H/N72;
-param_manager_inst/param_modify_H/N76;
param_manager_inst/param_modify_H/N120;
param_manager_inst/param_modify_H/N122;
param_manager_inst/param_modify_H/N140;
@@ -296952,46 +297047,45 @@ param_manager_inst/param_modify_H/N150;
param_manager_inst/param_modify_H/N153;
param_manager_inst/param_modify_H/N154;
param_manager_inst/param_modify_H/_N3248;
-param_manager_inst/param_modify_H/_N13934;
-param_manager_inst/param_modify_H/_N13936;
-param_manager_inst/param_modify_H/_N13938;
+param_manager_inst/param_modify_H/_N13885;
+param_manager_inst/param_modify_H/_N13887;
+param_manager_inst/param_modify_H/_N13889;
param_manager_inst/param_modify_H/_N27073_inv;
-param_manager_inst/param_modify_H/_N29675;
-param_manager_inst/param_modify_H/_N29678;
-param_manager_inst/param_modify_H/_N29681;
-param_manager_inst/param_modify_H/_N29684;
-param_manager_inst/param_modify_H/_N104546;
-param_manager_inst/param_modify_H/_N104547;
-param_manager_inst/param_modify_H/_N104548;
-param_manager_inst/param_modify_H/_N107227;
-param_manager_inst/param_modify_H/_N107229;
-param_manager_inst/param_modify_H/_N107234;
-param_manager_inst/param_modify_H/_N107236;
+param_manager_inst/param_modify_H/_N29625;
+param_manager_inst/param_modify_H/_N29628;
+param_manager_inst/param_modify_H/_N29631;
+param_manager_inst/param_modify_H/_N29634;
+param_manager_inst/param_modify_H/_N105381;
+param_manager_inst/param_modify_H/_N105382;
+param_manager_inst/param_modify_H/_N105383;
+param_manager_inst/param_modify_H/_N108049;
+param_manager_inst/param_modify_H/_N108056;
+param_manager_inst/param_modify_H/_N108060;
param_manager_inst/param_modify_H/pluse;
param_manager_inst/param_modify_S/N76;
param_manager_inst/param_modify_S/N140;
+param_manager_inst/param_modify_S/N142;
param_manager_inst/param_modify_S/N149;
param_manager_inst/param_modify_S/N150;
param_manager_inst/param_modify_S/N153;
param_manager_inst/param_modify_S/N154;
-param_manager_inst/param_modify_S/_N13943;
-param_manager_inst/param_modify_S/_N13945;
-param_manager_inst/param_modify_S/_N13947;
+param_manager_inst/param_modify_S/_N13894;
+param_manager_inst/param_modify_S/_N13896;
+param_manager_inst/param_modify_S/_N13898;
param_manager_inst/param_modify_S/_N27116_inv;
-param_manager_inst/param_modify_S/_N107281;
-param_manager_inst/param_modify_S/_N107282;
-param_manager_inst/param_modify_S/_N107290;
+param_manager_inst/param_modify_S/_N108118;
param_manager_inst/param_modify_V/N76;
param_manager_inst/param_modify_V/N140;
+param_manager_inst/param_modify_V/N142;
param_manager_inst/param_modify_V/N149;
param_manager_inst/param_modify_V/N150;
param_manager_inst/param_modify_V/N153;
param_manager_inst/param_modify_V/N154;
-param_manager_inst/param_modify_V/_N14021;
-param_manager_inst/param_modify_V/_N14023;
-param_manager_inst/param_modify_V/_N14025;
+param_manager_inst/param_modify_V/_N13963;
+param_manager_inst/param_modify_V/_N13965;
+param_manager_inst/param_modify_V/_N13967;
param_manager_inst/param_modify_V/_N27159_inv;
-param_manager_inst/param_modify_V/_N107271;
+param_manager_inst/param_modify_V/_N108096;
param_manager_inst/param_offsetX/N72;
param_manager_inst/param_offsetX/N76;
param_manager_inst/param_offsetX/N102;
@@ -297001,16 +297095,16 @@ param_manager_inst/param_offsetX/N149;
param_manager_inst/param_offsetX/N150;
param_manager_inst/param_offsetX/N153;
param_manager_inst/param_offsetX/N154;
-param_manager_inst/param_offsetX/_N15152;
-param_manager_inst/param_offsetX/_N15154;
-param_manager_inst/param_offsetX/_N15156;
-param_manager_inst/param_offsetX/_N15158;
-param_manager_inst/param_offsetX/_N15160;
+param_manager_inst/param_offsetX/_N15357;
+param_manager_inst/param_offsetX/_N15359;
+param_manager_inst/param_offsetX/_N15361;
+param_manager_inst/param_offsetX/_N15363;
+param_manager_inst/param_offsetX/_N15365;
param_manager_inst/param_offsetX/_N27202_inv;
-param_manager_inst/param_offsetX/_N29719;
-param_manager_inst/param_offsetX/_N104483;
-param_manager_inst/param_offsetX/_N104485;
-param_manager_inst/param_offsetX/_N104496;
+param_manager_inst/param_offsetX/_N29694;
+param_manager_inst/param_offsetX/_N105320;
+param_manager_inst/param_offsetX/_N105322;
+param_manager_inst/param_offsetX/_N105333;
param_manager_inst/param_offsetX/pluse;
param_manager_inst/param_offsetY/N76;
param_manager_inst/param_offsetY/N140;
@@ -297018,15 +297112,15 @@ param_manager_inst/param_offsetY/N149;
param_manager_inst/param_offsetY/N150;
param_manager_inst/param_offsetY/N153;
param_manager_inst/param_offsetY/N154;
-param_manager_inst/param_offsetY/_N3781;
-param_manager_inst/param_offsetY/_N3785;
-param_manager_inst/param_offsetY/_N15248;
-param_manager_inst/param_offsetY/_N15250;
-param_manager_inst/param_offsetY/_N15252;
-param_manager_inst/param_offsetY/_N15254;
-param_manager_inst/param_offsetY/_N15256;
+param_manager_inst/param_offsetY/_N3799;
+param_manager_inst/param_offsetY/_N3803;
+param_manager_inst/param_offsetY/_N15515;
+param_manager_inst/param_offsetY/_N15517;
+param_manager_inst/param_offsetY/_N15519;
+param_manager_inst/param_offsetY/_N15521;
+param_manager_inst/param_offsetY/_N15523;
param_manager_inst/param_offsetY/_N27254_inv;
-param_manager_inst/param_offsetY/_N104598;
+param_manager_inst/param_offsetY/_N105433;
param_manager_inst/param_osd_char_height/N72;
param_manager_inst/param_osd_char_height/N76;
param_manager_inst/param_osd_char_height/N102;
@@ -297037,34 +297131,35 @@ param_manager_inst/param_osd_char_height/N142;
param_manager_inst/param_osd_char_height/N148;
param_manager_inst/param_osd_char_height/N153;
param_manager_inst/param_osd_char_height/N154;
-param_manager_inst/param_osd_char_height/_N3927;
-param_manager_inst/param_osd_char_height/_N3949;
-param_manager_inst/param_osd_char_height/_N15507;
-param_manager_inst/param_osd_char_height/_N15509;
-param_manager_inst/param_osd_char_height/_N15511;
-param_manager_inst/param_osd_char_height/_N15513;
-param_manager_inst/param_osd_char_height/_N95979_inv;
-param_manager_inst/param_osd_char_height/_N107054;
-param_manager_inst/param_osd_char_height/_N107056;
-param_manager_inst/param_osd_char_height/_N107151;
-param_manager_inst/param_osd_char_height/_N107154;
+param_manager_inst/param_osd_char_height/_N3939;
+param_manager_inst/param_osd_char_height/_N3961;
+param_manager_inst/param_osd_char_height/_N15665;
+param_manager_inst/param_osd_char_height/_N15667;
+param_manager_inst/param_osd_char_height/_N15669;
+param_manager_inst/param_osd_char_height/_N15671;
+param_manager_inst/param_osd_char_height/_N97022_inv;
+param_manager_inst/param_osd_char_height/_N107876;
+param_manager_inst/param_osd_char_height/_N107878;
+param_manager_inst/param_osd_char_height/_N107973;
+param_manager_inst/param_osd_char_height/_N107976;
param_manager_inst/param_osd_char_height/pluse;
param_manager_inst/param_osd_char_width/N63;
param_manager_inst/param_osd_char_width/N76;
+param_manager_inst/param_osd_char_width/N139;
param_manager_inst/param_osd_char_width/N140;
param_manager_inst/param_osd_char_width/N142;
param_manager_inst/param_osd_char_width/N148;
param_manager_inst/param_osd_char_width/N153;
param_manager_inst/param_osd_char_width/N154;
-param_manager_inst/param_osd_char_width/_N4061;
-param_manager_inst/param_osd_char_width/_N4085;
-param_manager_inst/param_osd_char_width/_N15632;
-param_manager_inst/param_osd_char_width/_N15634;
-param_manager_inst/param_osd_char_width/_N15636;
-param_manager_inst/param_osd_char_width/_N15638;
-param_manager_inst/param_osd_char_width/_N95823_inv;
-param_manager_inst/param_osd_char_width/_N107060;
-param_manager_inst/param_osd_char_width/_N107067;
+param_manager_inst/param_osd_char_width/_N4097;
+param_manager_inst/param_osd_char_width/_N15676;
+param_manager_inst/param_osd_char_width/_N15678;
+param_manager_inst/param_osd_char_width/_N15680;
+param_manager_inst/param_osd_char_width/_N15682;
+param_manager_inst/param_osd_char_width/_N97127_inv;
+param_manager_inst/param_osd_char_width/_N107881;
+param_manager_inst/param_osd_char_width/_N107883;
+param_manager_inst/param_osd_char_width/_N107889;
param_manager_inst/param_osd_startX/N76;
param_manager_inst/param_osd_startX/N122;
param_manager_inst/param_osd_startX/N139;
@@ -297073,59 +297168,60 @@ param_manager_inst/param_osd_startX/N142;
param_manager_inst/param_osd_startX/N148;
param_manager_inst/param_osd_startX/N153;
param_manager_inst/param_osd_startX/N154;
-param_manager_inst/param_osd_startX/_N4233;
-param_manager_inst/param_osd_startX/_N15727;
-param_manager_inst/param_osd_startX/_N15729;
-param_manager_inst/param_osd_startX/_N15731;
-param_manager_inst/param_osd_startX/_N15733;
+param_manager_inst/param_osd_startX/_N4235;
+param_manager_inst/param_osd_startX/_N15696;
+param_manager_inst/param_osd_startX/_N15698;
+param_manager_inst/param_osd_startX/_N15700;
+param_manager_inst/param_osd_startX/_N15702;
param_manager_inst/param_osd_startX/_N27413;
param_manager_inst/param_osd_startX/_N27422;
param_manager_inst/param_osd_startX/_N27427_inv;
-param_manager_inst/param_osd_startX/_N29798;
-param_manager_inst/param_osd_startX/_N107081;
-param_manager_inst/param_osd_startX/_N107083;
-param_manager_inst/param_osd_startX/_N107084;
-param_manager_inst/param_osd_startX/_N107093;
-param_manager_inst/param_osd_startX/_N107094;
-param_manager_inst/param_osd_startX/_N107107;
+param_manager_inst/param_osd_startX/_N29773;
+param_manager_inst/param_osd_startX/_N107904;
+param_manager_inst/param_osd_startX/_N107906;
+param_manager_inst/param_osd_startX/_N107907;
+param_manager_inst/param_osd_startX/_N107916;
+param_manager_inst/param_osd_startX/_N107917;
+param_manager_inst/param_osd_startX/_N107930;
param_manager_inst/param_osd_startX/pluse;
param_manager_inst/param_osd_startY/N139;
param_manager_inst/param_osd_startY/N140;
param_manager_inst/param_osd_startY/N148;
param_manager_inst/param_osd_startY/N154;
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param_manager_inst/param_rotate/pluse;
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param_manager_inst/pressed_left;
param_manager_inst/pressed_restore;
param_manager_inst/pressed_right;
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u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N235;
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u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N27705;
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u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cke_pass;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmod_pass;
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u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_txpr_pass;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit_pass;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_done;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/_N96030;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/_N96815;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_rst_rreq;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N124;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N140;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N176;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N21;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N16316;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N16318;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N16320;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N96032;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N103632;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N106835;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N106841;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N17010;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N17012;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N17014;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N96819;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N104444;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N107664;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N107670;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_tmod_pass;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_twldqsen_pass;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_resp_r;
@@ -297344,45 +297440,45 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N265;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N294;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N303;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14284;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14286;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14288;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14290;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14292;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14294;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14296;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14298;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14300;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14302;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14304;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14306;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14308;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14310;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14312;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N18095_inv;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N22258;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N29921;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N95983;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N95994;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96039;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96040;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96049;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96053;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96797;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97033;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97144;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97145;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N105426;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N105430;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106546;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106549;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106550;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106551;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106574;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106577;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106578;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106581;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106583;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106584;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106586;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106588;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106592;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106598;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106607;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N108364;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N22198;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N29896;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96759;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96828;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96830;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96833;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96838;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96842;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97576;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97803;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97917;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97918;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106361;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106365;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107364;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107367;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107368;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107369;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107392;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107395;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107396;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107399;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107401;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107402;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107404;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107406;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107410;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107416;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107425;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N109250;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt_trfc_pass;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_success;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt_done;
@@ -297410,47 +297506,53 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N382;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14574;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14579;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14581;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14532;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14537;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14539;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N28526;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N55657;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N56412;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N57216;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N58869;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N59500;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N82045;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N96265;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N97065;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N97066;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N105455;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N137_rnmt;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N53495;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N55147;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N56942;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N58045;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N58048;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N82844;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N82848;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N82855;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N82859;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N97038;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N97836;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N97837;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N106264;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N240;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N0;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14543;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14545;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14547;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N97086;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N106342;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N106347;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N106349;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N106378;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14524;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14526;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14528;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N84886;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N97845;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N97846;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N107160;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N107164;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N107167;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N107173;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N107196;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14586;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14588;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14590;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14592;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14594;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14596;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14598;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14600;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N106328;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N106332;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N106336;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N106339;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14544;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14546;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14548;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14550;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14552;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14554;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14556;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14558;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107146;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107150;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157_cpy;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_neg;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_rst_n_rg;
@@ -297459,129 +297561,122 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N1814;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15390;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15392;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15394;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N83022;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N83332;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N95825;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96106;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96107;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96109;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96110;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96120;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96124;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96158;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96160;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96167;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96271;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96272;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96274;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96318;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96883;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15904;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15906;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15908;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N25006;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N59860;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N84178;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96676;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96884;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96886;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96885;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96887;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96913;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N105278;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N105949;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N106218;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N106288;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N106303;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N106624;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96888;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96898;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96900;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96902;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96937;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96939;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96942;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97033;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97080;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97478;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97660;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97662;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97663;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97672;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N104452;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N106091;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N106767;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N107042;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_inv;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5587;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22871;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22873;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22876;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22878;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22887;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22889;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22906;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24127;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5581;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22846;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22848;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22851;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22853;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22862;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22864;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N22881;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23929;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23953;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23976;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23977;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23978;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23979;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23980;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23981;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23982;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23983;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23984;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23985;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23986;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23987;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23988;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23989;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23990;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23991;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24024;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24025;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24026;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24027;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24028;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24029;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24030;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24031;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24032;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24033;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24034;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24035;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24036;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24037;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24038;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24039;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24088;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24089;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24092;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24093;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24096;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24097;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24100;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24101;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24136;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24137;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24138;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24139;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24140;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24141;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24142;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24143;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24144;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24145;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24146;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24147;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24148;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24149;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24150;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24174;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24197;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24198;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24199;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24200;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24201;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24202;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24203;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24204;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24205;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24206;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24207;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24208;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24209;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24210;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24211;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24212;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24245;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24246;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24247;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24248;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24249;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24250;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24251;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24252;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24253;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24254;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24255;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24256;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24257;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24258;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24259;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24260;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24309;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24310;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24313;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24314;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24317;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24318;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24321;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24322;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24357;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24358;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24359;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24360;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24361;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24362;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24363;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24364;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24365;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24366;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24367;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24368;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24369;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24370;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24371;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24372;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N95788;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96702;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24151;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96568;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N97460;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N138;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N431;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N15882;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N15884;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22668;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22669;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22670;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22671;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25192;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25195;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25196;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25197;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N82115;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96583;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N16437;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N16439;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25001;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25004;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25005;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N82919;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_n;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N56;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N63;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N72;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N165;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N173;
@@ -297599,35 +297694,32 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N466;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N475;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N6;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N12;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N15;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N22;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N5513;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14037;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14039;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14041;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14621;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14623;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14625;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17021;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17023;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17025;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N22696;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N62891;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105908;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105909;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105917;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105928;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105929;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105932;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105937;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105945;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105962;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105979;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N5539;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14577;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14579;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14581;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17029;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17031;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17033;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17072;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17074;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17076;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N22668;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106728;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106729;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106737;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106746;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106747;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106750;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106755;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106763;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106782;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106799;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ddrphy_gatei;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ddrphy_read_valid;
@@ -297659,39 +297751,39 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_gate_vld;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N16;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N97659;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N97664;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105840;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105844;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105848;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105852;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105856;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105860;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105864;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105868;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105872;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105875;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105985;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105989;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105993;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105997;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106001;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106012;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106016;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106020;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106024;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106028;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106032;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106036;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106037;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106043;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106047;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106068;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106072;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106076;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106080;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106083;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106087;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N98457;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N98462;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106662;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106666;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106670;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106674;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106678;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106682;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106686;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106690;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106694;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106697;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106805;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106809;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106813;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106817;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106821;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106832;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106836;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106840;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106844;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106848;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106852;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106856;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106857;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106863;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106867;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106888;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106892;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106896;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106900;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106903;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106907;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_del;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N384;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N446;
@@ -297705,54 +297797,58 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N679;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N683;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N5568;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14177;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14179;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14181;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14640;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N5562;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N13987;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N13989;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N13991;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14599;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14601;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14603;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14623;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14625;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14627;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14629;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14633;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14635;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14637;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14642;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14644;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14664;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14666;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14668;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14670;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14674;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14676;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14678;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14683;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14685;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14687;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14689;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N16999;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N17001;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N17003;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22748;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22793;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22819;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22825_inv;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22828;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22829;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22830;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22831;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22832;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22833;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N30142;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N82537;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N86995;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N96148;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N98671;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N105812;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N105823;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N105824;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N105825;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N105826;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N105830;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N105832;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N105880;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N105881;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N105884;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106534;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106564;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14646;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N14648;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N16969;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N16971;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N16973;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22723;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22768;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22794;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22800_inv;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22803;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22804;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22805;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22806;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22807;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N22808;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N30245;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N84099;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N87783;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N96930;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N101396;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106097;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106098;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106099;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106100;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106634;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106645;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106646;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106647;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106648;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106652;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106654;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106702;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106703;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N106706;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N107352;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N107382;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_inc_dec_n;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_rising;
@@ -297775,38 +297871,37 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_inv;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5676;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23156;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23158;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23161;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23163;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23172;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23174;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23191;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N95789;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96179;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5644;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23064;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23066;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23069;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23071;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23080;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23082;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23099;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96569;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N97491;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N17015;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N17017;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22940;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22941;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22942;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22943;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22944;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23872;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23875;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23876;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23877;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N82515;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N95827;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96189;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N13792;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N13794;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22906;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22907;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22908;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22909;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22910;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23666;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23669;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23670;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23671;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N83337;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96678;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96953;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_n;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N14;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N56;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N63;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136;
@@ -297825,33 +297920,35 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N475;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N6;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N10;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N12;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N22;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N5611;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N5601;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14669;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14671;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14673;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14706;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14708;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14710;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14712;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14714;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15010;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15012;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15014;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N16024;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N16026;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N16028;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N23001;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N63902;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106180;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106181;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106189;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106200;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106201;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106207;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106215;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106229;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106246;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15526;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15528;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15530;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N22935;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N64885;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107000;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107001;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107009;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107020;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107021;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107024;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107029;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107037;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107055;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107072;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/ddrphy_gatei;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/ddrphy_read_valid;
@@ -297884,40 +297981,40 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N11;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N16;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N97687;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N97690;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105732;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105736;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105740;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105744;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105748;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105752;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105756;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105757;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105760;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105765;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105767;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105787;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105791;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105795;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105799;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105802;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105806;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106100;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106104;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106108;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106112;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106116;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106124;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106128;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106132;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106136;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106140;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106144;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106148;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106152;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106156;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106159;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N98465;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N98468;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106554;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106558;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106562;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106566;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106570;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106574;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106578;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106579;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106582;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106587;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106589;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106609;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106613;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106617;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106621;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106624;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106628;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106920;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106924;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106928;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106932;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106936;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106944;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106948;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106952;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106956;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106960;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106964;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106968;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106972;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106976;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106979;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_del;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N446;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N570;
@@ -297927,35 +298024,35 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N610;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N679;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N5656;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14718;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14720;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14722;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14724;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14728;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14730;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14732;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14746;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14748;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14750;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14752;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N15542;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N15544;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N15546;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N17007;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N17009;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N17011;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N30199;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N82925;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N87573;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N105263;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N105291;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N105293;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106164;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106165;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106168;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106529;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106561;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N5624;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14677;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14679;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14681;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14683;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14687;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14689;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14691;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14696;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14698;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14700;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14702;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14978;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14980;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14982;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N17097;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N17099;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N17101;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N30302;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N84168;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N88361;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106076;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106104;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106106;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106984;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106985;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106988;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N107347;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N107379;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/gate_check;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/ioclk_dm;
@@ -297973,33 +298070,34 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wrlvl_dqs_en;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_inv;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5777;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23364;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23366;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23369;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23371;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23380;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23382;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23399;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N95790;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96699;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5767;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23521;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23523;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23526;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23528;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23537;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23539;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23556;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96570;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N97454;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N17029;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N17031;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22242;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22245;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22246;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22247;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23275;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23276;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23277;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23278;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23279;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N82905;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96023;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N17045;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N17047;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22182;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22185;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22186;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22187;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23183;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23184;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23185;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23186;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23187;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N83739;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96948;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N97026;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_n;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d;
@@ -298024,27 +298122,29 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N12;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N15;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N22;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14061;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14063;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14065;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14770;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14772;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14774;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16991;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16993;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16995;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N23286;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N64933;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N105253;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N105261;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106260;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106261;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106267;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106274;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106275;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106283;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106301;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106700;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N5686;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14728;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14730;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14732;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16954;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16956;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16958;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N17063;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N17065;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N17067;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N23194;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N65978;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106060;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106061;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106069;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107086;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107087;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107090;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107095;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107103;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107107;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107120;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107512;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag;
@@ -298078,40 +298178,42 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_check_pass;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N11;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N16;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N97684;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N97688;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105612;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105616;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105620;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105624;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105628;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105639;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105643;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105647;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105651;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105655;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105659;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105663;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105664;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105670;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105674;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105696;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105700;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105704;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105708;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105711;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105715;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106636;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106640;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106644;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106648;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106652;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106656;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106660;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106664;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106668;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106671;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N98454;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N98466;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106440;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106444;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106448;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106452;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106456;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106460;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106464;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106465;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106468;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106475;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106479;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106483;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106487;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106491;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106496;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106498;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106518;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106522;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106526;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106530;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106533;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106537;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107448;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107452;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107456;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107460;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107464;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107468;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107472;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107476;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107480;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107483;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_del;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N446;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N570;
@@ -298121,38 +298223,35 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N610;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N679;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N5735;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14778;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14780;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14782;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14784;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14788;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14790;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14792;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14805;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14807;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14809;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14811;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15017;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15019;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15021;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15934;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15936;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15938;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N30276;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N83291;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N88151;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106513;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106524;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106558;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106611;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106614;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106616;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106626;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106628;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106676;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106677;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106680;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N5725;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14736;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14738;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14740;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14742;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14746;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14748;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14750;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14761;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14763;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14765;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14767;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15081;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15083;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15085;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N17105;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N17107;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N17109;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N30395;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N84859;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N88943;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107331;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107342;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107376;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107438;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107440;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107488;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107489;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107492;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/gate_check;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/ioclk_dm;
@@ -298170,45 +298269,47 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wrlvl_dqs_en;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_inv;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5851;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23998;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24000;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24003;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24005;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24014;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24016;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24033;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N95791;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96708;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5877;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23777;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23779;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23782;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23784;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23793;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23795;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23812;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96571;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N97476;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N16084;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N16086;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22684;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22687;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22688;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22689;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23673;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23674;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23675;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23676;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23677;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N83280;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96259;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96322;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N15002;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N15004;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22628;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22631;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22632;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22633;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23590;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23591;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23592;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23593;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23594;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N84115;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N97084;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N97098;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_n;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N14;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N56;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N72;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N63;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N136;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N173;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N228;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N296;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N334;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N359;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N377;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N386;
@@ -298217,33 +298318,31 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N466;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N475;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N6;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N12;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N15;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N22;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N5801;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N13890;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N13892;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N13894;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14829;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14831;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14833;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N15920;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N15922;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N15924;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N23837;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N65991;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N105242;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N105247;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106316;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106361;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106362;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106370;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106371;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106796;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106804;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106805;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106810;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106813;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106818;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N5839;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14714;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14716;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14718;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14793;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14795;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14797;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N17037;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N17039;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N17041;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N23628;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N67087;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106050;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107179;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107180;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107188;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107189;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107615;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107623;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107624;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107633;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107647;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag;
@@ -298278,39 +298377,39 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_gate_vld;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N315;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N84566;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N97685;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N97689;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105487;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105491;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105495;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105499;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105503;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105507;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105511;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105512;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105518;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105580;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105584;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105588;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105592;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105595;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105599;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106398;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106402;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106406;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106410;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106414;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106422;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106426;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106430;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106434;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106438;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106442;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106446;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106450;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106454;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106457;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N85377;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N98467;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N98469;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106296;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106300;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106304;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106308;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106312;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106316;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106320;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106321;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106327;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106404;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106408;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106412;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106416;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106419;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106423;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107216;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107220;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107224;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107228;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107232;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107240;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107244;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107248;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107252;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107256;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107260;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107264;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107268;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107272;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107275;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_del;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N446;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N570;
@@ -298320,43 +298419,43 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N610;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N679;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N5820;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14837;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N5858;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14810;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14812;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14814;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14816;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14820;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14822;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14824;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14839;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14841;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14843;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14847;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14849;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14851;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14865;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14867;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14869;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14871;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15480;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15482;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15484;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15762;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15764;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15766;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N30323;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N83434;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N83645;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N88729;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N105284;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N105285;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N105286;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N105287;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106461;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106462;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106465;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106480;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106482;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106485;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106495;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106496;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106499;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106510;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106555;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14845;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16279;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16281;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16283;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16961;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16963;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16965;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N30422;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N84280;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N84865;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N89521;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107279;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107280;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107283;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107298;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107300;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107303;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107313;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107314;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107317;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107328;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107373;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107431;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107432;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107433;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107434;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/gate_check;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ioclk_dm;
@@ -298460,8 +298559,8 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/buffer_almost_full;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_en;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_tworw;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/ddrc_init_done;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/_N96029;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/_N96341;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/_N97165;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/_N97168;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_done;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_new_row;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_new_valid;
@@ -298477,36 +298576,36 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N252;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N281;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N304;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N317;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N6205;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N13492;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N13494;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N13496;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N13498;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N13500;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24498;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24507;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24508;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24509;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24510;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24511;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24512;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24513;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24514;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24515;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24516;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24517;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24518;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24519;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24520;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24521;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24867;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24870;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N105211;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N6298;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N15891;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N15893;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N15895;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N15897;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N15899;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24218;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24227;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24228;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24229;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24230;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24231;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24232;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24233;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24234;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24235;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24236;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24237;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24238;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24239;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24240;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24241;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24587;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24590;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N96998;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N96999;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N97000;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N97001;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N106247;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/N28;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/_N96290;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/_N96291;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/_N96292;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/_N96293;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/rowaddr_check_diff;
@@ -298514,21 +298613,20 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N39;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N89;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N258;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N371;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N404;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N410;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N416;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N418;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N458;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N461;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N491;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15216;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15218;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15220;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N24960;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N24969;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N84037;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N95818;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N96157;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15257;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15259;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15261;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N24686;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N24695;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N84823;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N96670;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N107589;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/back_valid;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/ctrl_back_rdy;
@@ -298548,123 +298646,122 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/P
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N61;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N69;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N3_inv_1;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N6888;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N104959;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N104965;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N6961;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N105977;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N105983;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/cmd_wr;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N55;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N61;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N69;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N3_inv_1;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N7000;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N104895;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N104901;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N7073;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N105913;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N105919;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/cmd_wr;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N55;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N61;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N69;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N3_inv_1;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N7112;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N104927;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N104933;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N7185;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N105945;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N105951;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/cmd_wr;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N55;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N61;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N69;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N3_inv_1;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N7224;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N104863;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N104869;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N7297;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N105881;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N105887;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/cmd_wr;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N55;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N61;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N69;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N3_inv_1;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N7336;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N104943;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N104949;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N7409;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N105961;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N105967;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/cmd_wr;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N55;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N61;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N69;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N3_inv_1;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N7448;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N104879;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N104885;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N7521;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N105897;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N105903;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/cmd_wr;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N55;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N61;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N69;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N3_inv_1;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N7560;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N104911;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N104917;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N7633;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N105929;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N105935;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/cmd_wr;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N55;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N61;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N69;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N3_inv_1;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N7672;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N104847;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N104853;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N7745;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N105865;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N105871;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/cmd_wr;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N7;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/_N104755;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/_N105799;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/_N104747;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/_N105791;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/_N104751;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/_N105795;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/_N104743;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/_N105787;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/_N104753;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/_N105797;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/_N104745;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/_N105789;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/_N104749;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/_N105793;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/_N104741;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/_N105785;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N7;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/_N104787;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/_N105831;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N7;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/_N104771;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/_N105815;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N7;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/_N104779;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/_N105823;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N7;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/_N104763;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/_N105807;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N7;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/_N104783;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/_N105827;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N7;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/_N104767;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/_N105811;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N7;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/_N104775;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/_N105819;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N7;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N25;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/_N104757;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24995;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N25010;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N25035;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N25040;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N25041;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N84089;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96409;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96411;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96414;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96417;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96417_cpy;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96772;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N102308_2;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N102308_3;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N104834;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N104986;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/_N105801;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24721;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24736;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24761;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24766;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24767;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N84881;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97171;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97173;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97176;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97179;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97179_cpy;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97564;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N103547_2;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N103547_3;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N105852;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N106004;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_valid_d1;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_accepted_l;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass;
@@ -298705,21 +298802,21 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/t
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N12;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/r_cnt_pass;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/_N104805;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/_N105849;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N45;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N47;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N3;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N6430;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N15659;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17324;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17326;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N25124;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N25139;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N96430;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N103199_2;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N104968;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N104973;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N6513;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N15350;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17302;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17304;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N24930;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N24945;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N97061;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N97072;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N103967_2;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N105986;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N105991;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/cmd_pre;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N50;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N55;
@@ -298730,41 +298827,40 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/t
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N27;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N29;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N35_inv_1;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N6672;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N15265;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N22538;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N96352;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N96653;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N97011;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N6745;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N15294;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N22394;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N96730;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N97405;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N97780;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N14;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N27;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N98;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N106;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/full;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N26;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15089;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15091;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15095;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15097;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15118;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15120;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15124;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15126;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_en_real;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/full;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N26;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N14986;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N14988;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N14992;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N14994;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N14933;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N14935;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N14939;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N14941;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_en_real;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N197;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/_N15643;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/_N15645;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/_N15565;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/_N15567;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/buffer_almost_full_a;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/buffer_almost_full_b;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/cmd_act;
@@ -298783,8 +298879,8 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll_d;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N148;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N155;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/_N96921;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/_N97074;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/_N97701;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/_N97841;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/pipe_cmd_accepted_l;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/pipe_cmd_accepted_m;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/pipe_cmd_act;
@@ -298803,34 +298899,34 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1796;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2051;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2053;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N3;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N96386;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N96387;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N96389;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N96391;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N96393;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N96934;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N96936;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97093;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97094;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97097;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97177;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97181;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N105384;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N105386;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N105392;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N105406;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N107940;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N107946;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97142;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97143;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97146;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97148;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97150;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97705;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97707;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97860;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97861;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97864;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97939;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N97943;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N106222;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N106224;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N106230;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N106240;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N108770;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/_N108776;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/r_brd_m;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/r_bwr_m;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/data_out_valid;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/empty;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/full;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15169;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15171;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15176;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15178;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15215;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15217;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15222;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15224;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_en;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/wr_en;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54;
@@ -298845,24 +298941,23 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N270;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N274;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N278;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N282;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/_N6167;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/_N6171;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/_N15126;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/_N15128;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/_N15130;
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+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/_N15188;
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+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/_N15244;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/_N103130_2;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/axi_arvalid;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N10;
@@ -298870,6 +298965,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N14;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_1;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_ready;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_valid;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr;
@@ -298882,10 +298978,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/full;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16;
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-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15028;
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15032;
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+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15009;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15011;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15015;
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15017;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/rempty;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_en_real;
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wvld_m;
@@ -298910,61 +299006,61 @@ u_axi_ddr_top/N928;
u_axi_ddr_top/_N36;
u_axi_ddr_top/_N46;
u_axi_ddr_top/_N50;
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u_axi_ddr_top/araddr_empty;
u_axi_ddr_top/axi_addr_valid;
u_axi_ddr_top/axi_data_valid;
@@ -299014,83 +299110,83 @@ u_axi_ddr_top/s_axi_awready;
u_axi_ddr_top/s_axi_awvalid;
u_axi_ddr_top/s_axi_wready;
u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N167;
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-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/_N15084;
-u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/_N15688;
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u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wfull;
u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N21;
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+u_axi_ddr_top/u_axi_wr_connect/_N104928;
u_axi_ddr_top/u_axi_wr_connect/ddr0_valid_fall0;
u_axi_ddr_top/u_axi_wr_connect/ddr0_valid_fall2;
u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall0;
@@ -299182,40 +299278,40 @@ u_axi_ddr_top/u_axi_wr_connect/fifo0_data_full;
u_axi_ddr_top/u_axi_wr_connect/fifo1_data_full;
u_axi_ddr_top/u_axi_wr_connect/fifo3_data_full;
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15977;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15979;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15981;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15983;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15985;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15990;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15992;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15994;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15996;
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u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rempty;
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wfull;
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16014;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16016;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16018;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16020;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N108381;
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u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rempty;
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wfull;
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158;
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+u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16059;
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16061;
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16063;
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16065;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16067;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16069;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16074;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16076;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16078;
-u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16080;
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rempty;
u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wfull;
u_axi_ddr_top/u_axi_wr_connect/rd0_en;
@@ -299237,38 +299333,38 @@ u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid0;
u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid1;
u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid2;
u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N167;
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/_N15701;
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/_N15703;
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/_N15705;
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/_N15707;
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/_N15709;
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/_N15714;
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/_N15716;
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/_N15718;
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/_N15720;
-u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/_N15722;
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u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rempty;
u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wfull;
u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N147;
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14551;
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14553;
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14555;
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14557;
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14693;
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14695;
-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14697;
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u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wfull;
u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N22;
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u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15038;
u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15040;
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15042;
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15044;
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15046;
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15051;
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15053;
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15055;
-u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15057;
u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wfull;
u_axi_ddr_top/wdata_empty;
u_axi_ddr_top/wr3_en;
@@ -299278,39 +299374,37 @@ u_axi_rst/rst0;
u_axi_rst/rst1;
u_clk50m_rst/rst0;
u_clk50m_rst/rst1;
-u_ddr_addr_ctr/N69;
-u_ddr_addr_ctr/N73;
-u_ddr_addr_ctr/_N13646;
-u_ddr_addr_ctr/_N13648;
-u_ddr_addr_ctr/_N13650;
-u_ddr_addr_ctr/_N13652;
-u_ddr_addr_ctr/_N13654;
-u_ddr_addr_ctr/_N13656;
-u_ddr_addr_ctr/_N13658;
-u_ddr_addr_ctr/_N13660;
-u_ddr_addr_ctr/_N13662;
-u_ddr_addr_ctr/_N13664;
-u_ddr_addr_ctr/_N103666;
-u_ddr_addr_ctr/_N103670;
-u_ddr_addr_ctr/_N103674;
-u_ddr_addr_ctr/_N103678;
-u_ddr_addr_ctr/_N103682;
+u_ddr_addr_ctr/N72;
+u_ddr_addr_ctr/N76;
+u_ddr_addr_ctr/_N15998;
+u_ddr_addr_ctr/_N16000;
+u_ddr_addr_ctr/_N16002;
+u_ddr_addr_ctr/_N16004;
+u_ddr_addr_ctr/_N16006;
+u_ddr_addr_ctr/_N16008;
+u_ddr_addr_ctr/_N16010;
+u_ddr_addr_ctr/_N16012;
+u_ddr_addr_ctr/_N16014;
+u_ddr_addr_ctr/_N104489;
+u_ddr_addr_ctr/_N104493;
+u_ddr_addr_ctr/_N104497;
+u_ddr_addr_ctr/_N104498;
u_ddr_addr_ctr/rd1_vs0;
u_ddr_addr_ctr/u_rd0_addr_ctr/N131;
u_ddr_addr_ctr/u_rd0_addr_ctr/N152;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13668;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13670;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13672;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13676;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13678;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13680;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13682;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13684;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13686;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13688;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13690;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N13692;
-u_ddr_addr_ctr/u_rd0_addr_ctr/_N104723;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13636;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13638;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13640;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13644;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13646;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13648;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13650;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13652;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13654;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13656;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13658;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N13660;
+u_ddr_addr_ctr/u_rd0_addr_ctr/_N105736;
u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt;
u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt0;
u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt1;
@@ -299320,11 +299414,11 @@ u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done_rise;
u_ddr_addr_ctr/u_rd1_addr_ctr/N16;
u_ddr_addr_ctr/u_rd1_addr_ctr/N259;
u_ddr_addr_ctr/u_rd1_addr_ctr/N271;
-u_ddr_addr_ctr/u_rd1_addr_ctr/_N16092;
-u_ddr_addr_ctr/u_rd1_addr_ctr/_N16094;
-u_ddr_addr_ctr/u_rd1_addr_ctr/_N16096;
-u_ddr_addr_ctr/u_rd1_addr_ctr/_N16098;
-u_ddr_addr_ctr/u_rd1_addr_ctr/_N16100;
+u_ddr_addr_ctr/u_rd1_addr_ctr/_N16071;
+u_ddr_addr_ctr/u_rd1_addr_ctr/_N16073;
+u_ddr_addr_ctr/u_rd1_addr_ctr/_N16075;
+u_ddr_addr_ctr/u_rd1_addr_ctr/_N16077;
+u_ddr_addr_ctr/u_rd1_addr_ctr/_N16079;
u_ddr_addr_ctr/u_rd1_addr_ctr/empty;
u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done0;
u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done1;
@@ -299336,40 +299430,40 @@ u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs0;
u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs1;
u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs_rise0;
u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N21;
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16177;
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16179;
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16181;
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16183;
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16187;
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16189;
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16191;
-u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16193;
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16139;
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16141;
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16143;
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16145;
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16149;
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16151;
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16153;
+u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16155;
u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/wfull;
u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/N0;
u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_vary0;
u_ddr_addr_ctr/u_rd3_addr_ctr/N34;
u_ddr_addr_ctr/u_rd3_addr_ctr/N44;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N9428;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N9446;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N14442;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N14444;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N14446;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N14448;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N14450;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N14452;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N14454;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16156;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16158;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16160;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16162;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16164;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16209;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16211;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16213;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16215;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16217;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16219;
-u_ddr_addr_ctr/u_rd3_addr_ctr/_N16221;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N9458;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N9476;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N15090;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N15092;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N15094;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N15096;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N15098;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N15100;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N15102;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16118;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16120;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16122;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16124;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16126;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16159;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16161;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16163;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16165;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16167;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16169;
+u_ddr_addr_ctr/u_rd3_addr_ctr/_N16171;
u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid0;
u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid1;
u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid2;
@@ -299404,7 +299498,7 @@ u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag;
u_ddr_addr_ctr/u_wr3_addr_ctr/N73;
u_ddr_addr_ctr/u_wr3_addr_ctr/N103;
u_ddr_addr_ctr/u_wr3_addr_ctr/N108;
-u_ddr_addr_ctr/u_wr3_addr_ctr/_N84166;
+u_ddr_addr_ctr/u_wr3_addr_ctr/_N85000;
u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done0;
u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done1;
u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done2;
@@ -299467,18 +299561,18 @@ u_ov5640/coms1_reg_config/N12;
u_ov5640/coms1_reg_config/N1134;
u_ov5640/coms1_reg_config/N1169;
u_ov5640/coms1_reg_config/N1193;
-u_ov5640/coms1_reg_config/_N9664;
-u_ov5640/coms1_reg_config/_N9682;
-u_ov5640/coms1_reg_config/_N9690;
-u_ov5640/coms1_reg_config/_N16246;
-u_ov5640/coms1_reg_config/_N16248;
-u_ov5640/coms1_reg_config/_N16250;
-u_ov5640/coms1_reg_config/_N16252;
-u_ov5640/coms1_reg_config/_N16384;
-u_ov5640/coms1_reg_config/_N16386;
-u_ov5640/coms1_reg_config/_N16388;
-u_ov5640/coms1_reg_config/_N96528;
-u_ov5640/coms1_reg_config/_N106873;
+u_ov5640/coms1_reg_config/_N9677;
+u_ov5640/coms1_reg_config/_N9695;
+u_ov5640/coms1_reg_config/_N9703;
+u_ov5640/coms1_reg_config/_N16268;
+u_ov5640/coms1_reg_config/_N16270;
+u_ov5640/coms1_reg_config/_N16272;
+u_ov5640/coms1_reg_config/_N16274;
+u_ov5640/coms1_reg_config/_N16288;
+u_ov5640/coms1_reg_config/_N16290;
+u_ov5640/coms1_reg_config/_N16292;
+u_ov5640/coms1_reg_config/_N97285;
+u_ov5640/coms1_reg_config/_N107702;
u_ov5640/coms1_reg_config/clk_20k_regdiv;
u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite;
u_ov5640/coms1_reg_config/clock_20k;
@@ -299486,22 +299580,22 @@ u_ov5640/coms1_reg_config/start;
u_ov5640/coms1_reg_config/tr_end;
u_ov5640/coms1_reg_config/u1/N195;
u_ov5640/coms1_reg_config/u1/N239;
-u_ov5640/coms1_reg_config/u1/_N16393;
-u_ov5640/coms1_reg_config/u1/_N16395;
-u_ov5640/coms1_reg_config/u1/_N25450;
-u_ov5640/coms1_reg_config/u1/_N25453;
-u_ov5640/coms1_reg_config/u1/_N25456;
-u_ov5640/coms1_reg_config/u1/_N25461;
-u_ov5640/coms1_reg_config/u1/_N25467;
-u_ov5640/coms1_reg_config/u1/_N25468;
-u_ov5640/coms1_reg_config/u1/_N84271;
-u_ov5640/coms1_reg_config/u1/_N95900;
-u_ov5640/coms1_reg_config/u1/_N95931;
-u_ov5640/coms1_reg_config/u1/_N96534;
-u_ov5640/coms1_reg_config/u1/_N96769;
-u_ov5640/coms1_reg_config/u1/_N98079;
-u_ov5640/coms1_reg_config/u1/_N103821;
-u_ov5640/coms1_reg_config/u1/_N106880;
+u_ov5640/coms1_reg_config/u1/_N16297;
+u_ov5640/coms1_reg_config/u1/_N16299;
+u_ov5640/coms1_reg_config/u1/_N25300;
+u_ov5640/coms1_reg_config/u1/_N25303;
+u_ov5640/coms1_reg_config/u1/_N25306;
+u_ov5640/coms1_reg_config/u1/_N25311;
+u_ov5640/coms1_reg_config/u1/_N25317;
+u_ov5640/coms1_reg_config/u1/_N25318;
+u_ov5640/coms1_reg_config/u1/_N85071;
+u_ov5640/coms1_reg_config/u1/_N96805;
+u_ov5640/coms1_reg_config/u1/_N97112;
+u_ov5640/coms1_reg_config/u1/_N97234;
+u_ov5640/coms1_reg_config/u1/_N97669;
+u_ov5640/coms1_reg_config/u1/_N99985;
+u_ov5640/coms1_reg_config/u1/_N104644;
+u_ov5640/coms1_reg_config/u1/_N107709;
u_ov5640/coms1_reg_config/u1/reg_sdat_rnmt;
u_ov5640/coms1_reg_config/u1/sclk;
u_ov5640/coms2_reg_config/N8;
@@ -299509,62 +299603,66 @@ u_ov5640/coms2_reg_config/N12;
u_ov5640/coms2_reg_config/N1134;
u_ov5640/coms2_reg_config/N1169;
u_ov5640/coms2_reg_config/N1193;
-u_ov5640/coms2_reg_config/_N9736;
-u_ov5640/coms2_reg_config/_N9754;
-u_ov5640/coms2_reg_config/_N9762;
-u_ov5640/coms2_reg_config/_N16399;
-u_ov5640/coms2_reg_config/_N16401;
-u_ov5640/coms2_reg_config/_N16403;
-u_ov5640/coms2_reg_config/_N16405;
-u_ov5640/coms2_reg_config/_N16411;
-u_ov5640/coms2_reg_config/_N16413;
-u_ov5640/coms2_reg_config/_N16415;
-u_ov5640/coms2_reg_config/_N96531;
-u_ov5640/coms2_reg_config/_N103874;
+u_ov5640/coms2_reg_config/_N9749;
+u_ov5640/coms2_reg_config/_N9767;
+u_ov5640/coms2_reg_config/_N9775;
+u_ov5640/coms2_reg_config/_N16303;
+u_ov5640/coms2_reg_config/_N16305;
+u_ov5640/coms2_reg_config/_N16307;
+u_ov5640/coms2_reg_config/_N16309;
+u_ov5640/coms2_reg_config/_N16315;
+u_ov5640/coms2_reg_config/_N16317;
+u_ov5640/coms2_reg_config/_N16319;
+u_ov5640/coms2_reg_config/_N97290;
+u_ov5640/coms2_reg_config/_N104698;
u_ov5640/coms2_reg_config/clk_20k_regdiv;
u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite;
u_ov5640/coms2_reg_config/clock_20k;
u_ov5640/coms2_reg_config/start;
u_ov5640/coms2_reg_config/tr_end;
-u_ov5640/coms2_reg_config/u1/N146;
-u_ov5640/coms2_reg_config/u1/N185;
-u_ov5640/coms2_reg_config/u1/N187;
u_ov5640/coms2_reg_config/u1/N195;
-u_ov5640/coms2_reg_config/u1/_N16420;
-u_ov5640/coms2_reg_config/u1/_N16422;
-u_ov5640/coms2_reg_config/u1/_N25893;
-u_ov5640/coms2_reg_config/u1/_N25896;
-u_ov5640/coms2_reg_config/u1/_N25899;
-u_ov5640/coms2_reg_config/u1/_N25904;
-u_ov5640/coms2_reg_config/u1/_N25910;
-u_ov5640/coms2_reg_config/u1/_N25911;
-u_ov5640/coms2_reg_config/u1/_N84324;
-u_ov5640/coms2_reg_config/u1/_N96487;
-u_ov5640/coms2_reg_config/u1/_N96610;
-u_ov5640/coms2_reg_config/u1/_N96977;
-u_ov5640/coms2_reg_config/u1/_N106895;
-u_ov5640/coms2_reg_config/u1/_N106896;
+u_ov5640/coms2_reg_config/u1/N239;
+u_ov5640/coms2_reg_config/u1/N256;
+u_ov5640/coms2_reg_config/u1/N267;
+u_ov5640/coms2_reg_config/u1/_N16324;
+u_ov5640/coms2_reg_config/u1/_N16326;
+u_ov5640/coms2_reg_config/u1/_N25830;
+u_ov5640/coms2_reg_config/u1/_N25833;
+u_ov5640/coms2_reg_config/u1/_N25837;
+u_ov5640/coms2_reg_config/u1/_N25840;
+u_ov5640/coms2_reg_config/u1/_N25845;
+u_ov5640/coms2_reg_config/u1/_N25848;
+u_ov5640/coms2_reg_config/u1/_N25853;
+u_ov5640/coms2_reg_config/u1/_N25859;
+u_ov5640/coms2_reg_config/u1/_N85124;
+u_ov5640/coms2_reg_config/u1/_N87597;
+u_ov5640/coms2_reg_config/u1/_N97064;
+u_ov5640/coms2_reg_config/u1/_N97132;
+u_ov5640/coms2_reg_config/u1/_N97333;
+u_ov5640/coms2_reg_config/u1/_N97590;
+u_ov5640/coms2_reg_config/u1/_N97699;
+u_ov5640/coms2_reg_config/u1/_N104685;
u_ov5640/coms2_reg_config/u1/reg_sdat_rnmt;
u_ov5640/coms2_reg_config/u1/sclk;
u_ov5640/power_on_delay_inst/N15;
-u_ov5640/power_on_delay_inst/_N13709;
-u_ov5640/power_on_delay_inst/_N13711;
-u_ov5640/power_on_delay_inst/_N13713;
-u_ov5640/power_on_delay_inst/_N13715;
-u_ov5640/power_on_delay_inst/_N13717;
-u_ov5640/power_on_delay_inst/_N13719;
-u_ov5640/power_on_delay_inst/_N13721;
-u_ov5640/power_on_delay_inst/_N13723;
-u_ov5640/power_on_delay_inst/_N16426;
-u_ov5640/power_on_delay_inst/_N16428;
-u_ov5640/power_on_delay_inst/_N16430;
-u_ov5640/power_on_delay_inst/_N16432;
-u_ov5640/power_on_delay_inst/_N16434;
-u_ov5640/power_on_delay_inst/_N16436;
-u_ov5640/power_on_delay_inst/_N16438;
-u_ov5640/power_on_delay_inst/_N106851;
-u_ov5640/power_on_delay_inst/_N106855;
-u_ov5640/power_on_delay_inst/_N106859;
+u_ov5640/power_on_delay_inst/_N13678;
+u_ov5640/power_on_delay_inst/_N13680;
+u_ov5640/power_on_delay_inst/_N13682;
+u_ov5640/power_on_delay_inst/_N13684;
+u_ov5640/power_on_delay_inst/_N13686;
+u_ov5640/power_on_delay_inst/_N13688;
+u_ov5640/power_on_delay_inst/_N13690;
+u_ov5640/power_on_delay_inst/_N13692;
+u_ov5640/power_on_delay_inst/_N16330;
+u_ov5640/power_on_delay_inst/_N16332;
+u_ov5640/power_on_delay_inst/_N16334;
+u_ov5640/power_on_delay_inst/_N16336;
+u_ov5640/power_on_delay_inst/_N16338;
+u_ov5640/power_on_delay_inst/_N16340;
+u_ov5640/power_on_delay_inst/_N16342;
+u_ov5640/power_on_delay_inst/_N107680;
+u_ov5640/power_on_delay_inst/_N107684;
+u_ov5640/power_on_delay_inst/_N107688;
u_ov5640/power_on_delay_inst/camera_pwnd;
u_ov5640/u_mix_image/N311;
u_ov5640/u_mix_image/N315;
@@ -299575,33 +299673,33 @@ u_ov5640/u_mix_image/N415;
u_ov5640/u_mix_image/N417;
u_ov5640/u_mix_image/N427;
u_ov5640/u_mix_image/_N4;
-u_ov5640/u_mix_image/_N13728;
-u_ov5640/u_mix_image/_N13730;
-u_ov5640/u_mix_image/_N13732;
-u_ov5640/u_mix_image/_N13734;
-u_ov5640/u_mix_image/_N16442;
-u_ov5640/u_mix_image/_N16444;
-u_ov5640/u_mix_image/_N16446;
-u_ov5640/u_mix_image/_N16448;
-u_ov5640/u_mix_image/_N16476;
-u_ov5640/u_mix_image/_N16478;
-u_ov5640/u_mix_image/_N16480;
-u_ov5640/u_mix_image/_N16482;
-u_ov5640/u_mix_image/_N16498;
-u_ov5640/u_mix_image/_N16500;
-u_ov5640/u_mix_image/_N16502;
-u_ov5640/u_mix_image/_N16504;
-u_ov5640/u_mix_image/_N96537;
-u_ov5640/u_mix_image/_N96993;
-u_ov5640/u_mix_image/_N103792;
-u_ov5640/u_mix_image/_N103793;
-u_ov5640/u_mix_image/_N103802;
-u_ov5640/u_mix_image/_N103803;
-u_ov5640/u_mix_image/_N103812;
-u_ov5640/u_mix_image/_N103813;
-u_ov5640/u_mix_image/_N103845;
-u_ov5640/u_mix_image/_N103853;
-u_ov5640/u_mix_image/_N103854;
+u_ov5640/u_mix_image/_N13697;
+u_ov5640/u_mix_image/_N13699;
+u_ov5640/u_mix_image/_N13701;
+u_ov5640/u_mix_image/_N13703;
+u_ov5640/u_mix_image/_N16346;
+u_ov5640/u_mix_image/_N16348;
+u_ov5640/u_mix_image/_N16350;
+u_ov5640/u_mix_image/_N16352;
+u_ov5640/u_mix_image/_N16380;
+u_ov5640/u_mix_image/_N16382;
+u_ov5640/u_mix_image/_N16384;
+u_ov5640/u_mix_image/_N16386;
+u_ov5640/u_mix_image/_N16402;
+u_ov5640/u_mix_image/_N16404;
+u_ov5640/u_mix_image/_N16406;
+u_ov5640/u_mix_image/_N16408;
+u_ov5640/u_mix_image/_N97291;
+u_ov5640/u_mix_image/_N97559;
+u_ov5640/u_mix_image/_N104615;
+u_ov5640/u_mix_image/_N104616;
+u_ov5640/u_mix_image/_N104625;
+u_ov5640/u_mix_image/_N104626;
+u_ov5640/u_mix_image/_N104635;
+u_ov5640/u_mix_image/_N104636;
+u_ov5640/u_mix_image/_N104668;
+u_ov5640/u_mix_image/_N104676;
+u_ov5640/u_mix_image/_N104677;
u_ov5640/u_mix_image/cmos1_vsync_rise;
u_ov5640/u_mix_image/cmos2_vsync_rise;
u_ov5640/u_mix_image/data_out_valid0;
@@ -299615,44 +299713,42 @@ u_ov5640/u_mix_image/rd_vs0;
u_ov5640/u_mix_image/rd_vs1;
u_ov5640/u_mix_image/rd_vs2;
u_ov5640/u_mix_image/rd_vs_rise;
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16509;
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16511;
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16513;
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16515;
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16517;
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16521;
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16523;
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16525;
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16527;
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16529;
-u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N108362;
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16413;
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16415;
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16417;
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16419;
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16421;
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16425;
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16427;
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16429;
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16431;
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16433;
+u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N109247;
u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wfull;
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16453;
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16455;
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16457;
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16459;
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16461;
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16533;
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16535;
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16537;
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16539;
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16541;
-u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N108363;
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16357;
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16359;
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16361;
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16363;
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16365;
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16443;
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16445;
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16447;
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16449;
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16451;
+u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N109248;
u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wfull;
u_ov5640/u_mix_image/wr1_en;
u_ov5640/u_mix_image/wr2_en;
u_rotate_image/N52;
u_rotate_image/N170;
-u_rotate_image/N302;
+u_rotate_image/N350;
u_rotate_image/_N17;
-u_rotate_image/_N9883;
-u_rotate_image/_N9905;
-u_rotate_image/_N9923;
-u_rotate_image/_N9933;
-u_rotate_image/_N9939;
-u_rotate_image/_N9967;
-u_rotate_image/_N12915;
-u_rotate_image/_N12916;
+u_rotate_image/_N9918;
+u_rotate_image/_N9940;
+u_rotate_image/_N9958;
+u_rotate_image/_N9968;
+u_rotate_image/_N9974;
+u_rotate_image/_N10002;
u_rotate_image/_N12917;
u_rotate_image/_N12918;
u_rotate_image/_N12919;
@@ -299701,43 +299797,45 @@ u_rotate_image/_N12961;
u_rotate_image/_N12962;
u_rotate_image/_N12963;
u_rotate_image/_N12964;
-u_rotate_image/_N16225;
-u_rotate_image/_N16227;
-u_rotate_image/_N16229;
-u_rotate_image/_N16231;
-u_rotate_image/_N16233;
-u_rotate_image/_N16235;
-u_rotate_image/_N16237;
-u_rotate_image/_N16239;
-u_rotate_image/_N16241;
-u_rotate_image/_N16545;
-u_rotate_image/_N16547;
-u_rotate_image/_N16549;
-u_rotate_image/_N16551;
-u_rotate_image/_N16572;
-u_rotate_image/_N16574;
-u_rotate_image/_N16576;
-u_rotate_image/_N16578;
-u_rotate_image/_N16592;
-u_rotate_image/_N16594;
-u_rotate_image/_N16596;
-u_rotate_image/_N16598;
-u_rotate_image/_N16600;
-u_rotate_image/_N16602;
-u_rotate_image/_N16604;
-u_rotate_image/_N16606;
-u_rotate_image/_N16608;
-u_rotate_image/_N104107;
-u_rotate_image/_N104578;
-u_rotate_image/_N104579;
-u_rotate_image/_N104610;
-u_rotate_image/_N104611;
-u_rotate_image/_N104621;
-u_rotate_image/_N104622;
-u_rotate_image/_N104623;
-u_rotate_image/_N104630;
-u_rotate_image/_N104632;
-u_rotate_image/_N104639;
+u_rotate_image/_N12965;
+u_rotate_image/_N12966;
+u_rotate_image/_N16175;
+u_rotate_image/_N16177;
+u_rotate_image/_N16179;
+u_rotate_image/_N16181;
+u_rotate_image/_N16183;
+u_rotate_image/_N16185;
+u_rotate_image/_N16187;
+u_rotate_image/_N16189;
+u_rotate_image/_N16191;
+u_rotate_image/_N16455;
+u_rotate_image/_N16457;
+u_rotate_image/_N16459;
+u_rotate_image/_N16461;
+u_rotate_image/_N16477;
+u_rotate_image/_N16479;
+u_rotate_image/_N16481;
+u_rotate_image/_N16483;
+u_rotate_image/_N16497;
+u_rotate_image/_N16499;
+u_rotate_image/_N16501;
+u_rotate_image/_N16503;
+u_rotate_image/_N16505;
+u_rotate_image/_N16507;
+u_rotate_image/_N16509;
+u_rotate_image/_N16511;
+u_rotate_image/_N16513;
+u_rotate_image/_N104946;
+u_rotate_image/_N105413;
+u_rotate_image/_N105414;
+u_rotate_image/_N105445;
+u_rotate_image/_N105446;
+u_rotate_image/_N105456;
+u_rotate_image/_N105457;
+u_rotate_image/_N105458;
+u_rotate_image/_N105465;
+u_rotate_image/_N105467;
+u_rotate_image/_N105474;
u_rotate_image/addr_fifo_empty;
u_rotate_image/addr_fifo_rd_en;
u_rotate_image/addr_fifo_valid;
@@ -299751,61 +299849,61 @@ u_rotate_image/image_w_blank_valid;
u_rotate_image/image_w_valid;
u_rotate_image/rd_sta_s2;
u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21;
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16624;
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16626;
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16628;
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16630;
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16632;
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637;
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16639;
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16641;
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16643;
-u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16645;
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16563;
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16565;
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16567;
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16569;
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16571;
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576;
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578;
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16580;
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16582;
+u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16584;
u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wfull;
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16650;
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16652;
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16654;
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16656;
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16658;
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16662;
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16664;
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16666;
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16668;
-u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16670;
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16589;
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16591;
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16593;
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16595;
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16597;
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16601;
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16603;
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16605;
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16607;
+u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16609;
u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/wfull;
u_sync_vg/N54;
u_sync_vg/N61;
u_sync_vg/N145;
u_sync_vg/N178;
u_sync_vg/N185;
-u_sync_vg/_N10003;
-u_sync_vg/_N10011;
u_sync_vg/_N10039;
-u_sync_vg/_N10041;
-u_sync_vg/_N10071;
-u_sync_vg/_N10093;
-u_sync_vg/_N10113;
-u_sync_vg/_N10145;
-u_sync_vg/_N16583;
-u_sync_vg/_N16585;
-u_sync_vg/_N16587;
-u_sync_vg/_N16589;
-u_sync_vg/_N16674;
-u_sync_vg/_N16676;
-u_sync_vg/_N16678;
-u_sync_vg/_N16680;
-u_sync_vg/_N16682;
-u_sync_vg/_N96762;
-u_sync_vg/_N97008;
-u_sync_vg/_N97010;
-u_sync_vg/_N97018;
-u_sync_vg/_N97211;
-u_sync_vg/_N105053;
-u_sync_vg/_N105054;
-u_sync_vg/_N105066;
-u_sync_vg/_N105067;
-u_sync_vg/_N105074;
-u_sync_vg/_N107935;
+u_sync_vg/_N10047;
+u_sync_vg/_N10075;
+u_sync_vg/_N10077;
+u_sync_vg/_N10107;
+u_sync_vg/_N10129;
+u_sync_vg/_N10149;
+u_sync_vg/_N10165;
+u_sync_vg/_N16488;
+u_sync_vg/_N16490;
+u_sync_vg/_N16492;
+u_sync_vg/_N16494;
+u_sync_vg/_N16613;
+u_sync_vg/_N16615;
+u_sync_vg/_N16617;
+u_sync_vg/_N16619;
+u_sync_vg/_N16621;
+u_sync_vg/_N97573;
+u_sync_vg/_N97773;
+u_sync_vg/_N97778;
+u_sync_vg/_N97979;
+u_sync_vg/_N105600;
+u_sync_vg/_N105601;
+u_sync_vg/_N105613;
+u_sync_vg/_N105614;
+u_sync_vg/_N105622;
+u_sync_vg/_N105624;
+u_sync_vg/_N108767;
u_sync_vg/de_re0;
u_sync_vg/de_re1;
u_sync_vg/de_re2;
@@ -299820,26 +299918,26 @@ u_sync_vg/vs_out1;
u_sync_vg/vs_out2;
u_sys_pll/u_pll_e3/ntCLKFB;
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16324;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16326;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16328;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16330;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16332;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16334;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16336;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16341;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16343;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16345;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16347;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16349;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16351;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16353;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N108007;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N108010;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N108011;
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N108384;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16234;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16236;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16238;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16240;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16242;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16244;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16246;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16251;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16253;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16255;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16257;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16259;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16261;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16263;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N108841;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N109268;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N109269;
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rempty;
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wfull;
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr[11]_cpy;
u_zoom_image/N198;
u_zoom_image/N232;
u_zoom_image/N234;
@@ -299854,20 +299952,19 @@ u_zoom_image/N850;
u_zoom_image/N858;
u_zoom_image/N891;
u_zoom_image/N919;
+u_zoom_image/_N23;
u_zoom_image/_N25;
u_zoom_image/_N28;
u_zoom_image/_N43;
-u_zoom_image/_N10185;
-u_zoom_image/_N10193;
-u_zoom_image/_N10201;
+u_zoom_image/_N10205;
u_zoom_image/_N10213;
-u_zoom_image/_N10250;
-u_zoom_image/_N10267;
-u_zoom_image/_N10283;
-u_zoom_image/_N10299;
-u_zoom_image/_N10307;
-u_zoom_image/_N12965;
-u_zoom_image/_N12966;
+u_zoom_image/_N10221;
+u_zoom_image/_N10233;
+u_zoom_image/_N10270;
+u_zoom_image/_N10287;
+u_zoom_image/_N10303;
+u_zoom_image/_N10319;
+u_zoom_image/_N10327;
u_zoom_image/_N12967;
u_zoom_image/_N12968;
u_zoom_image/_N12969;
@@ -300080,116 +300177,118 @@ u_zoom_image/_N13175;
u_zoom_image/_N13176;
u_zoom_image/_N13177;
u_zoom_image/_N13178;
-u_zoom_image/_N13739;
+u_zoom_image/_N13179;
+u_zoom_image/_N13180;
+u_zoom_image/_N13708;
+u_zoom_image/_N13710;
+u_zoom_image/_N13712;
+u_zoom_image/_N13714;
+u_zoom_image/_N13719;
+u_zoom_image/_N13721;
+u_zoom_image/_N13723;
+u_zoom_image/_N13725;
+u_zoom_image/_N13730;
+u_zoom_image/_N13732;
+u_zoom_image/_N13734;
+u_zoom_image/_N13736;
u_zoom_image/_N13741;
u_zoom_image/_N13743;
u_zoom_image/_N13745;
-u_zoom_image/_N13750;
+u_zoom_image/_N13747;
u_zoom_image/_N13752;
u_zoom_image/_N13754;
u_zoom_image/_N13756;
-u_zoom_image/_N13761;
+u_zoom_image/_N13758;
u_zoom_image/_N13763;
u_zoom_image/_N13765;
u_zoom_image/_N13767;
-u_zoom_image/_N13772;
+u_zoom_image/_N13769;
u_zoom_image/_N13774;
u_zoom_image/_N13776;
u_zoom_image/_N13778;
-u_zoom_image/_N13783;
-u_zoom_image/_N13785;
-u_zoom_image/_N13787;
-u_zoom_image/_N13789;
-u_zoom_image/_N13794;
-u_zoom_image/_N13796;
-u_zoom_image/_N13798;
-u_zoom_image/_N13800;
-u_zoom_image/_N14629;
-u_zoom_image/_N14631;
-u_zoom_image/_N14633;
-u_zoom_image/_N14635;
-u_zoom_image/_N14927;
-u_zoom_image/_N14929;
-u_zoom_image/_N14931;
-u_zoom_image/_N14933;
-u_zoom_image/_N14935;
-u_zoom_image/_N14937;
-u_zoom_image/_N14941;
-u_zoom_image/_N14943;
-u_zoom_image/_N14945;
-u_zoom_image/_N14947;
-u_zoom_image/_N14953;
-u_zoom_image/_N14955;
-u_zoom_image/_N14960;
-u_zoom_image/_N14962;
-u_zoom_image/_N14964;
-u_zoom_image/_N14966;
-u_zoom_image/_N14968;
-u_zoom_image/_N14970;
-u_zoom_image/_N14974;
-u_zoom_image/_N14976;
-u_zoom_image/_N14978;
-u_zoom_image/_N14980;
-u_zoom_image/_N14982;
-u_zoom_image/_N16684;
+u_zoom_image/_N13780;
+u_zoom_image/_N14585;
+u_zoom_image/_N14587;
+u_zoom_image/_N14589;
+u_zoom_image/_N14591;
+u_zoom_image/_N14593;
+u_zoom_image/_N14595;
+u_zoom_image/_N14877;
+u_zoom_image/_N14879;
+u_zoom_image/_N14881;
+u_zoom_image/_N14883;
+u_zoom_image/_N14889;
+u_zoom_image/_N14891;
+u_zoom_image/_N14896;
+u_zoom_image/_N14898;
+u_zoom_image/_N14900;
+u_zoom_image/_N14902;
+u_zoom_image/_N14904;
+u_zoom_image/_N14906;
+u_zoom_image/_N14910;
+u_zoom_image/_N14912;
+u_zoom_image/_N14914;
+u_zoom_image/_N14916;
+u_zoom_image/_N14918;
+u_zoom_image/_N16623;
+u_zoom_image/_N16633;
+u_zoom_image/_N16635;
+u_zoom_image/_N16637;
+u_zoom_image/_N16639;
+u_zoom_image/_N16641;
+u_zoom_image/_N16643;
+u_zoom_image/_N16645;
+u_zoom_image/_N16647;
+u_zoom_image/_N16649;
+u_zoom_image/_N16651;
+u_zoom_image/_N16655;
+u_zoom_image/_N16657;
+u_zoom_image/_N16659;
+u_zoom_image/_N16661;
+u_zoom_image/_N16663;
+u_zoom_image/_N16665;
+u_zoom_image/_N16667;
+u_zoom_image/_N16669;
+u_zoom_image/_N16671;
+u_zoom_image/_N16673;
+u_zoom_image/_N16677;
+u_zoom_image/_N16679;
+u_zoom_image/_N16681;
+u_zoom_image/_N16683;
+u_zoom_image/_N16685;
+u_zoom_image/_N16690;
+u_zoom_image/_N16692;
u_zoom_image/_N16694;
u_zoom_image/_N16696;
u_zoom_image/_N16698;
u_zoom_image/_N16700;
-u_zoom_image/_N16702;
u_zoom_image/_N16704;
u_zoom_image/_N16706;
u_zoom_image/_N16708;
u_zoom_image/_N16710;
u_zoom_image/_N16712;
-u_zoom_image/_N16716;
-u_zoom_image/_N16718;
-u_zoom_image/_N16720;
-u_zoom_image/_N16722;
-u_zoom_image/_N16724;
-u_zoom_image/_N16726;
-u_zoom_image/_N16728;
-u_zoom_image/_N16730;
-u_zoom_image/_N16732;
-u_zoom_image/_N16734;
-u_zoom_image/_N16750;
-u_zoom_image/_N16752;
-u_zoom_image/_N16754;
-u_zoom_image/_N16756;
-u_zoom_image/_N16758;
-u_zoom_image/_N16763;
-u_zoom_image/_N16765;
-u_zoom_image/_N16767;
-u_zoom_image/_N16769;
-u_zoom_image/_N16771;
-u_zoom_image/_N16773;
-u_zoom_image/_N16777;
-u_zoom_image/_N16779;
-u_zoom_image/_N16781;
-u_zoom_image/_N16783;
-u_zoom_image/_N16785;
-u_zoom_image/_N96561;
-u_zoom_image/_N104995;
-u_zoom_image/_N104996;
-u_zoom_image/_N104997;
-u_zoom_image/_N105007;
-u_zoom_image/_N105009;
-u_zoom_image/_N105018;
-u_zoom_image/_N105020;
-u_zoom_image/_N105029;
-u_zoom_image/_N105031;
-u_zoom_image/_N105036;
-u_zoom_image/_N105043;
-u_zoom_image/_N105046;
-u_zoom_image/_N105079;
-u_zoom_image/_N105085;
-u_zoom_image/_N105097;
-u_zoom_image/_N105114;
-u_zoom_image/_N105128;
-u_zoom_image/_N105129;
-u_zoom_image/_N105134;
-u_zoom_image/_N105142;
-u_zoom_image/_N107195;
+u_zoom_image/_N97307;
+u_zoom_image/_N105542;
+u_zoom_image/_N105543;
+u_zoom_image/_N105544;
+u_zoom_image/_N105554;
+u_zoom_image/_N105556;
+u_zoom_image/_N105565;
+u_zoom_image/_N105567;
+u_zoom_image/_N105576;
+u_zoom_image/_N105578;
+u_zoom_image/_N105583;
+u_zoom_image/_N105590;
+u_zoom_image/_N105593;
+u_zoom_image/_N105626;
+u_zoom_image/_N105632;
+u_zoom_image/_N105644;
+u_zoom_image/_N105661;
+u_zoom_image/_N105675;
+u_zoom_image/_N105676;
+u_zoom_image/_N105681;
+u_zoom_image/_N105689;
+u_zoom_image/_N108017;
u_zoom_image/data_in_valid0;
u_zoom_image/data_out_valid1;
u_zoom_image/fifo_full0;
@@ -300213,29 +300312,31 @@ udp_osd_inst/N26;
udp_osd_inst/N29;
udp_osd_inst/N40;
udp_osd_inst/N69;
+udp_osd_inst/_N97124;
udp_osd_inst/char_buf_writer_inst/N11;
udp_osd_inst/char_buf_writer_inst/N16;
udp_osd_inst/char_buf_writer_inst/N141;
+udp_osd_inst/char_buf_writer_inst/N165;
udp_osd_inst/char_buf_writer_inst/N170;
udp_osd_inst/char_buf_writer_inst/N179;
udp_osd_inst/char_buf_writer_inst/N222;
udp_osd_inst/char_buf_writer_inst/_N1;
-udp_osd_inst/char_buf_writer_inst/_N15271;
-udp_osd_inst/char_buf_writer_inst/_N15273;
-udp_osd_inst/char_buf_writer_inst/_N15275;
-udp_osd_inst/char_buf_writer_inst/_N15277;
-udp_osd_inst/char_buf_writer_inst/_N15279;
-udp_osd_inst/char_buf_writer_inst/_N16790;
-udp_osd_inst/char_buf_writer_inst/_N16792;
-udp_osd_inst/char_buf_writer_inst/_N16794;
-udp_osd_inst/char_buf_writer_inst/_N16796;
-udp_osd_inst/char_buf_writer_inst/_N16798;
-udp_osd_inst/char_buf_writer_inst/_N16800;
-udp_osd_inst/char_buf_writer_inst/_N16802;
+udp_osd_inst/char_buf_writer_inst/_N14921;
+udp_osd_inst/char_buf_writer_inst/_N14923;
+udp_osd_inst/char_buf_writer_inst/_N14925;
+udp_osd_inst/char_buf_writer_inst/_N14927;
+udp_osd_inst/char_buf_writer_inst/_N14929;
+udp_osd_inst/char_buf_writer_inst/_N16729;
+udp_osd_inst/char_buf_writer_inst/_N16731;
+udp_osd_inst/char_buf_writer_inst/_N16733;
+udp_osd_inst/char_buf_writer_inst/_N16735;
+udp_osd_inst/char_buf_writer_inst/_N16737;
+udp_osd_inst/char_buf_writer_inst/_N16739;
+udp_osd_inst/char_buf_writer_inst/_N16741;
udp_osd_inst/char_buf_writer_inst/_N18382;
-udp_osd_inst/char_buf_writer_inst/_N26277;
-udp_osd_inst/char_buf_writer_inst/_N26278;
-udp_osd_inst/char_buf_writer_inst/_N26287;
+udp_osd_inst/char_buf_writer_inst/_N26259;
+udp_osd_inst/char_buf_writer_inst/_N26260;
+udp_osd_inst/char_buf_writer_inst/_N26269;
udp_osd_inst/char_buf_writer_inst/_N30558;
udp_osd_inst/char_buf_writer_inst/_N30561;
udp_osd_inst/char_buf_writer_inst/_N30564;
@@ -300246,18 +300347,16 @@ udp_osd_inst/char_buf_writer_inst/_N30576;
udp_osd_inst/char_buf_writer_inst/_N30579;
udp_osd_inst/char_buf_writer_inst/_N30582;
udp_osd_inst/char_buf_writer_inst/_N30585;
-udp_osd_inst/char_buf_writer_inst/_N77915;
-udp_osd_inst/char_buf_writer_inst/_N106956;
-udp_osd_inst/char_buf_writer_inst/_N106960;
-udp_osd_inst/char_buf_writer_inst/_N106962;
-udp_osd_inst/char_osd_inst/_N107128;
+udp_osd_inst/char_buf_writer_inst/_N78526;
+udp_osd_inst/char_buf_writer_inst/_N107780;
+udp_osd_inst/char_buf_writer_inst/_N107784;
+udp_osd_inst/char_buf_writer_inst/_N107786;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N73;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79_cpy;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N100;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N245;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N379;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N478;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N684;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N711;
@@ -300265,7 +300364,7 @@ udp_osd_inst/char_osd_inst/char_buf_reader_inst/N714;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N784;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N832;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N842;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N843;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N848;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N858;
@@ -300273,70 +300372,73 @@ udp_osd_inst/char_osd_inst/char_buf_reader_inst/N861;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N862;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907[6]_cpy;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N0;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N2;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N7;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N13698;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N13700;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N13702;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N13704;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N14091;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N14093;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N14095;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N14097;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N14099;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N14562;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N14564;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N14566;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N14568;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N14570;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15062;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15064;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15045;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15047;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15049;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15051;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15053;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15057;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15059;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15061;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15063;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15065;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15475;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15477;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15479;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N15481;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N16196;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N16198;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18389;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18392;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18403;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404;
udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18405;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N30325;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N30374;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N81460;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N82884;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N82900;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96372;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96517;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96555;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96929;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97090;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97174;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N106978;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N106993;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N106995;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N106996;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N107004;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N107006;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N107017;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N108032;
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N108385;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N30062;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N30111;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N84128;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N84135;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96870;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97129;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97275;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97697;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97897;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97976;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N99326;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N101750;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N107806;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N107821;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N107823;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N107826;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N108858;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N108866;
+udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N109249;
udp_osd_inst/char_osd_inst/char_next;
udp_osd_inst/char_osd_inst/char_pic_rom_inst/N41;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N9062;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N10325;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N10331;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14458;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14460;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14462;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14464;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14466;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14611;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14613;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14615;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14617;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N16613;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N16615;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N16617;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N16619;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N95973;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N107183;
-udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N107189;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N4437;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N10345;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N10351;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14829;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14831;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14833;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N14835;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N15106;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N15108;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N15110;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N15112;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N15114;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N16518;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N16520;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N16522;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N16524;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N97272;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N108005;
+udp_osd_inst/char_osd_inst/char_pic_rom_inst/_N108011;
udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or;
udp_osd_inst/char_osd_inst/char_valid;
udp_osd_inst/char_osd_inst/pixels_shifter_inst/N6;
@@ -300347,57 +300449,54 @@ udp_osd_inst/char_osd_inst/pixels_shifter_inst/N114;
udp_osd_inst/char_osd_inst/pixels_shifter_inst/N122;
udp_osd_inst/char_osd_inst/pixels_shifter_inst/N135;
udp_osd_inst/char_osd_inst/pixels_shifter_inst/N137;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N10397;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N10405;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16806;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16808;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16811;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16813;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16815;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16817;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16819;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N99960;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107115;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107125;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107126;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107175;
-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107176;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N10417;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N10425;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16745;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16747;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16750;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16752;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16754;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16756;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16758;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N100778;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107938;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107948;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107949;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107997;
+udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107998;
udp_osd_inst/char_osd_inst/pixels_shifter_inst/s_ready_d;
udp_osd_inst/char_osd_inst/row_pixels_ready;
udp_osd_inst/char_osd_inst/row_pixels_valid;
udp_osd_inst/eth_udp_inst/N72;
udp_osd_inst/eth_udp_inst/N72_cpy;
-udp_osd_inst/eth_udp_inst/_N84201;
-udp_osd_inst/eth_udp_inst/_N95844;
-udp_osd_inst/eth_udp_inst/_N95913;
-udp_osd_inst/eth_udp_inst/_N95922;
-udp_osd_inst/eth_udp_inst/_N95923;
-udp_osd_inst/eth_udp_inst/_N95925;
-udp_osd_inst/eth_udp_inst/_N95955;
-udp_osd_inst/eth_udp_inst/_N95958;
-udp_osd_inst/eth_udp_inst/_N96003;
-udp_osd_inst/eth_udp_inst/_N96007;
-udp_osd_inst/eth_udp_inst/_N96072;
-udp_osd_inst/eth_udp_inst/_N96085;
-udp_osd_inst/eth_udp_inst/_N96096;
-udp_osd_inst/eth_udp_inst/_N96358;
-udp_osd_inst/eth_udp_inst/_N96385;
-udp_osd_inst/eth_udp_inst/_N96556;
-udp_osd_inst/eth_udp_inst/_N96693;
-udp_osd_inst/eth_udp_inst/_N96774;
-udp_osd_inst/eth_udp_inst/_N96775;
-udp_osd_inst/eth_udp_inst/_N96776;
-udp_osd_inst/eth_udp_inst/_N96780;
-udp_osd_inst/eth_udp_inst/_N97006;
-udp_osd_inst/eth_udp_inst/_N97022;
-udp_osd_inst/eth_udp_inst/_N97473;
-udp_osd_inst/eth_udp_inst/_N98508;
-udp_osd_inst/eth_udp_inst/_N104315;
-udp_osd_inst/eth_udp_inst/_N106910;
-udp_osd_inst/eth_udp_inst/_N106911;
-udp_osd_inst/eth_udp_inst/_N106920;
-udp_osd_inst/eth_udp_inst/_N107965;
-udp_osd_inst/eth_udp_inst/_N108056;
+udp_osd_inst/eth_udp_inst/_N82337;
+udp_osd_inst/eth_udp_inst/_N82491;
+udp_osd_inst/eth_udp_inst/_N96653;
+udp_osd_inst/eth_udp_inst/_N96654;
+udp_osd_inst/eth_udp_inst/_N96657;
+udp_osd_inst/eth_udp_inst/_N96703;
+udp_osd_inst/eth_udp_inst/_N96734;
+udp_osd_inst/eth_udp_inst/_N96787;
+udp_osd_inst/eth_udp_inst/_N97121;
+udp_osd_inst/eth_udp_inst/_N97122;
+udp_osd_inst/eth_udp_inst/_N97125;
+udp_osd_inst/eth_udp_inst/_N97265;
+udp_osd_inst/eth_udp_inst/_N97327;
+udp_osd_inst/eth_udp_inst/_N97338;
+udp_osd_inst/eth_udp_inst/_N97341;
+udp_osd_inst/eth_udp_inst/_N97535;
+udp_osd_inst/eth_udp_inst/_N97539;
+udp_osd_inst/eth_udp_inst/_N97540;
+udp_osd_inst/eth_udp_inst/_N97542;
+udp_osd_inst/eth_udp_inst/_N97554;
+udp_osd_inst/eth_udp_inst/_N97887;
+udp_osd_inst/eth_udp_inst/_N98258;
+udp_osd_inst/eth_udp_inst/_N100572;
+udp_osd_inst/eth_udp_inst/_N105154;
+udp_osd_inst/eth_udp_inst/_N107734;
+udp_osd_inst/eth_udp_inst/_N107735;
+udp_osd_inst/eth_udp_inst/_N107744;
+udp_osd_inst/eth_udp_inst/_N108899;
udp_osd_inst/eth_udp_inst/arp_gmii_tx_en;
udp_osd_inst/eth_udp_inst/arp_rx_done;
udp_osd_inst/eth_udp_inst/arp_rx_type;
@@ -300405,18 +300504,18 @@ udp_osd_inst/eth_udp_inst/arp_tx_en;
udp_osd_inst/eth_udp_inst/gmii_rxd_valid;
udp_osd_inst/eth_udp_inst/gmii_txd_valid;
udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14259;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14261;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14263;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14265;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14267;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15113;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15115;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15117;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15119;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15121;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N108365;
-udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N108366;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15142;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15144;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15146;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15148;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15150;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15155;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15157;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15159;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15161;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15163;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N109266;
+udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N109267;
udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rempty;
udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wfull;
udp_osd_inst/eth_udp_inst/icmp_gmii_tx_en;
@@ -300424,10 +300523,10 @@ udp_osd_inst/eth_udp_inst/icmp_rec_en;
udp_osd_inst/eth_udp_inst/icmp_tx_start_en;
udp_osd_inst/eth_udp_inst/rec_en;
udp_osd_inst/eth_udp_inst/tx_req;
-udp_osd_inst/eth_udp_inst/u_arp/_N96069;
-udp_osd_inst/eth_udp_inst/u_arp/_N96846;
-udp_osd_inst/eth_udp_inst/u_arp/_N97055;
-udp_osd_inst/eth_udp_inst/u_arp/_N97057;
+udp_osd_inst/eth_udp_inst/u_arp/_N96855;
+udp_osd_inst/eth_udp_inst/u_arp/_N97621;
+udp_osd_inst/eth_udp_inst/u_arp/_N97817;
+udp_osd_inst/eth_udp_inst/u_arp/_N97819;
udp_osd_inst/eth_udp_inst/u_arp/crc_en;
udp_osd_inst/eth_udp_inst/u_arp/tx_done;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52;
@@ -300443,7 +300542,6 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N406;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N419;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N422;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_cpy;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639;
@@ -300453,55 +300551,57 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N834;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N847;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N1057;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N4998;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N5481;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N18413;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N22378;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N23306;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N23312;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N83294;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N96226;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N96803;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N97436;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N97485;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107311;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107315;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107316;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107326;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107330;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107334;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107338;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107342;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107346;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107350;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107358;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107371;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107373;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107375;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107382;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107386;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107390;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107394;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107398;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107402;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107404;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107409;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107416;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107420;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107424;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107428;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107432;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107436;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107438;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107443;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107445;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107453;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107457;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107462;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107475;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107476;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107477;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108081;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108082;
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+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N25486;
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+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N84898;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N97222;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N97717;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N98228;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N98265;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108141;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108144;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108145;
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+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108163;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108167;
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+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108204;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108211;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108215;
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+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108231;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108233;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108238;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108245;
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+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108304;
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+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108306;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108892;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108893;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108916;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108917;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/error_en;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/skip_en;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_inv;
@@ -300519,106 +300619,106 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N781;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N817;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N932;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N13921;
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-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20887;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20888;
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-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20890;
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-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20892;
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-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20935;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20936;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20937;
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-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20939;
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-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20945;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20946;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20947;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20948;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20949;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20950;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20990;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20998;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20999;
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-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21001;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21002;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21003;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21004;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21005;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21014;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21023;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21024;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21025;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21026;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21027;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21028;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21029;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21038;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N38191;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N38289;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N38293;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N95832;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N95890;
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-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N96807;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103144_2;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103145_2;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103184_4;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103184_7;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103184_9;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103189_2;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103189_7;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103189_10;
-udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107660;
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+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108574;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108578;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108582;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108593;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108597;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108601;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108605;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108609;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108613;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108617;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108621;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108624;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108625;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108629;
+udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108686;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/skip_en;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_done_t;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d0;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d1;
udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d2;
udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N263;
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N95977;
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N96081;
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N96842;
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N96843;
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97028;
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97029;
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97058;
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N107804;
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N107806;
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N107809;
-udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N107811;
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N96853;
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N96856;
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97617;
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97618;
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97812;
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97813;
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97820;
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N108636;
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N108638;
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N108641;
+udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N108643;
udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_rx_flag;
udp_osd_inst/eth_udp_inst/u_eth_ctrl/icmp_tx_req_d0;
udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft1/ntO;
@@ -300639,24 +300739,24 @@ udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[2].gtp_outbuft1/ntT;
udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[3].gtp_outbuft1/ntO;
udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[3].gtp_outbuft1/ntT;
udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/u_rgmii_rx_ctl_ibuf/ntD;
-udp_osd_inst/eth_udp_inst/u_icmp/_N96067;
-udp_osd_inst/eth_udp_inst/u_icmp/_N97048;
-udp_osd_inst/eth_udp_inst/u_icmp/_N97050;
+udp_osd_inst/eth_udp_inst/u_icmp/_N96861;
+udp_osd_inst/eth_udp_inst/u_icmp/_N97827;
+udp_osd_inst/eth_udp_inst/u_icmp/_N97829;
udp_osd_inst/eth_udp_inst/u_icmp/crc_en;
udp_osd_inst/eth_udp_inst/u_icmp/tx_done;
udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N263;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96065;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96068;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96836;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96837;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96840;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97043;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97044;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97051;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N107881;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N107883;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N107886;
-udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N107888;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96859;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96862;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97627;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97628;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97631;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97822;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97823;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97830;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N108713;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N108715;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N108718;
+udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N108720;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N82;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N100;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129;
@@ -300664,6 +300764,7 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N183;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N361;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N397;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N421;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N456;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N511;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N516;
@@ -300695,36 +300796,36 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1127;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1170;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1213;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1261;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1265;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1294;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1304;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1309;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1326;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N5391;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N5466;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N5329;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N5465;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N10697;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14324;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14326;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14328;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14330;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14332;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14334;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14336;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14338;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14340;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14342;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14344;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14346;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14348;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14350;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14352;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13799;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13801;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13803;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13805;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13807;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13809;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13811;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14329;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14331;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14333;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14335;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14337;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14339;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14341;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14343;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14345;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14347;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14349;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14351;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14353;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14355;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14357;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14359;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14361;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14363;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14365;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14367;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14369;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14371;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14373;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14375;
@@ -300733,65 +300834,62 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14379;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14381;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14383;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14385;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17056;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17058;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17060;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17062;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17064;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17066;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17068;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14387;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14389;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14391;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14393;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14395;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14397;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14399;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N18460;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N18470;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N18475;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N18479;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22164;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22175;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22178;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22180;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N29955;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N81758;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N81987;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N95975;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N96999;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N100419;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107503;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107507;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107511;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107515;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107518;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107522;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107540;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107549;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107553;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107557;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107561;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107565;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107569;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107572;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107576;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107581;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107586;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107590;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107594;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107598;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107602;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107604;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107606;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107609;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107614;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107618;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107622;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107626;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107629;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107632;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107635;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107647;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107652;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107657;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108059;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108064;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108067;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108068;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22650;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22664;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22666;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N29901;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N84087;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N84941;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N96834;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N97775;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N103649_2;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108335;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108339;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108343;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108347;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108350;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108354;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108360;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108372;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108381;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108385;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108389;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108393;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108397;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108401;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108404;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108408;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108413;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108418;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108422;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108426;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108430;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108434;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108436;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108438;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108441;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108446;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108450;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108454;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108458;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108461;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108464;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108467;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108479;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108484;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108489;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108894;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108902;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108903;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3;
@@ -300826,50 +300924,76 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1731;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2622;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2624;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3084;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N10425;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N10498;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15297;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15299;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N10439;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N10512;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15301;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15303;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15305;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15307;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15309;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15311;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15313;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15315;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15317;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15319;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15321;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15323;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15518;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15520;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15522;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15524;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15526;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15528;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15530;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15575;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15577;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15579;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16033;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16035;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16037;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16039;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16041;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16043;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16045;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16139;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16141;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16143;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16145;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16147;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16149;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16151;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16823;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16825;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16827;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16829;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16831;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15329;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15331;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15333;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15335;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15337;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15339;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15341;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15369;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15371;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15373;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15375;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15377;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15379;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15381;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15486;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15488;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15490;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15572;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15574;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15576;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15578;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15580;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15582;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15584;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16018;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16020;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16022;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16024;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16026;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16028;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16030;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16762;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16764;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16766;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16768;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16770;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16772;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16774;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16776;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16778;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16780;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16782;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16784;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16786;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16788;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16790;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16795;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16797;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16799;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16801;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16803;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16805;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16807;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16812;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16814;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16816;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16818;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16820;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16822;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16824;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16826;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16828;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16833;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16835;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16837;
@@ -300880,71 +301004,45 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16845;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16847;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16849;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16851;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16856;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16858;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16860;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16862;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16864;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16853;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16855;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16857;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16859;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16861;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16866;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16868;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16873;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16875;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16877;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16879;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16881;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16883;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16885;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16887;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16889;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16870;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16872;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16874;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16876;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16878;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16880;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16884;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16886;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16888;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16890;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16892;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16894;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16896;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16898;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16900;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16902;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16904;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16906;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16908;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16910;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16912;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16914;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16916;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16918;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16920;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16922;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16927;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16929;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16931;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16933;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16935;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16937;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16939;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16941;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16945;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16947;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16949;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16951;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16953;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16955;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16957;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16959;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16964;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16966;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16968;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16970;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16972;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16974;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16976;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16978;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16980;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16924;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16926;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16928;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N18495;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25971;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25975;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25976;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26001;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26002;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26004;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26005;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26006;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25935;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25939;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25940;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25965;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25966;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25968;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25969;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25970;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26327;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26342;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26389;
@@ -300988,40 +301086,44 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26744;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26745;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26746;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26747;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N84470;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N95801;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96019;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96367;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96573;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96731;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N102344_2;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N102547_2;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N102854_2;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N106906;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N106909;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107683;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107685;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107696;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107698;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107862;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108072;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108075;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108076;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108095;
-udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108106;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N85270;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96582;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97305;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97455;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97509;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97586;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97693;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N103457_2;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N103555_2;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N103556_2;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107730;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107733;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108515;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108517;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108528;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108530;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108694;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108907;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108910;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108911;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108930;
+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108941;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d0;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d1;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d2;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/trig_tx_en;
udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_done_t;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N72;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N90;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N374;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N376;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N431;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N432;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N433;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N434;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N460;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N580;
@@ -301039,59 +301141,60 @@ udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N859;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N889;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N10578;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16556;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16558;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16560;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16562;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16564;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16566;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16568;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N10592;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16102;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16104;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16106;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16108;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16110;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16112;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16114;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N18510;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N26584;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N26589;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N26601;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N26602;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N30726;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N81655;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N84440;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N84443;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N84536;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N96777;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N96779;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104125;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104141;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104145;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104149;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104153;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104157;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104172;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104176;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104180;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104184;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104188;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104192;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104195;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104199;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104204;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104209;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104213;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104217;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104221;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104225;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104227;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104229;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104232;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104237;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104241;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104245;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104249;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104252;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104255;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104267;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104270;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N107971;
-udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N107972;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N85237;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N85240;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N85340;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N96655;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N97357;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N97541;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N97553;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104964;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104980;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104984;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104988;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104992;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104996;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105011;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105015;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105019;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105023;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105027;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105031;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105034;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105038;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105044;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105047;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105052;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105056;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105060;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105064;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105066;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105068;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105071;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105076;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105080;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105084;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105088;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105091;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105094;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105106;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105109;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N108801;
+udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N108802;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en;
udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N120;
@@ -301103,21 +301206,21 @@ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N282;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N296;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N321;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N327;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14103;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14105;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14107;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14109;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14111;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14113;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14115;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N15501;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N15503;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N97495;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N106928;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N106933;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N106935;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N106939;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N108115;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13922;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13924;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13926;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13928;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13930;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13932;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13934;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N17122;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N17124;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N98274;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107752;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107757;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107759;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107763;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N108952;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/change_to_read;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_empty;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en;
@@ -301127,6 +301230,7 @@ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_wr_en;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_wr_en_cpy;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_wr_done;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/recv_m_data_tlast;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req_sync0;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req_sync1;
@@ -301134,25 +301238,24 @@ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync0;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync1;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14997;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14999;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15001;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15003;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15005;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17160;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17162;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17164;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17166;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17168;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N108382;
-udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N108383;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13665;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13667;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13669;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13671;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13673;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17080;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17082;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17084;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17086;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17088;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N109270;
+udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N109271;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wfull;
udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_start_i_ff;
udp_osd_inst/eth_udp_inst/udp_rx_pkt_done;
udp_osd_inst/m_pixel_data;
udp_osd_inst/m_pixel_valid;
udp_osd_inst/ram_wen;
-udp_osd_inst/udp_rx_data_tlast;
udp_osd_inst/udp_rx_data_tready;
udp_osd_inst/udp_rx_data_tvalid;
udp_rx_pkt_en;
@@ -301185,19 +301288,19 @@ udp_wr_mem_inst/N524;
udp_wr_mem_inst/N723;
udp_wr_mem_inst/N727;
udp_wr_mem_inst/N730;
-udp_wr_mem_inst/_N15067;
-udp_wr_mem_inst/_N15069;
-udp_wr_mem_inst/_N15071;
-udp_wr_mem_inst/_N97138;
-udp_wr_mem_inst/_N97274;
-udp_wr_mem_inst/_N97275;
-udp_wr_mem_inst/_N97276;
-udp_wr_mem_inst/_N97277;
-udp_wr_mem_inst/_N104284;
-udp_wr_mem_inst/_N104290;
-udp_wr_mem_inst/_N104294;
-udp_wr_mem_inst/_N104298;
-udp_wr_mem_inst/_N104323;
+udp_wr_mem_inst/_N13814;
+udp_wr_mem_inst/_N13816;
+udp_wr_mem_inst/_N13818;
+udp_wr_mem_inst/_N97909;
+udp_wr_mem_inst/_N98046;
+udp_wr_mem_inst/_N98047;
+udp_wr_mem_inst/_N98048;
+udp_wr_mem_inst/_N98049;
+udp_wr_mem_inst/_N105123;
+udp_wr_mem_inst/_N105129;
+udp_wr_mem_inst/_N105133;
+udp_wr_mem_inst/_N105137;
+udp_wr_mem_inst/_N105162;
vs_in;
vs_in_ibuf/ntD;
vs_osd;
@@ -301232,34 +301335,32 @@ N123_0.co [4];
N123_0.co [6];
N123_0.co [8];
N123_0.co [10];
-N332[1];
-N332[2];
-N332[3];
-N332[4];
-N332[5];
-N332[6];
-N332[7];
-N332[8];
-N332[9];
-N332[10];
-N332[11];
-N334[1];
-N334[2];
-N334[3];
-N334[4];
-N334[5];
-N334[6];
-N334[7];
-N334[8];
-N334[9];
-N334[10];
-N334[11];
+N333[1];
+N333[2];
+N333[3];
+N333[4];
+N333[5];
+N333[6];
+N333[7];
+N333[8];
+N333[9];
+N333[10];
+N333[11];
+N335[1];
+N335[2];
+N335[3];
+N335[4];
+N335[5];
+N335[6];
+N335[7];
+N335[8];
+N335[9];
+N335[10];
+N335[11];
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N132.co [2];
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N132.co [4];
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N132.co [6];
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N199 [0];
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N199 [1];
-adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N201 [2];
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204 [0];
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204 [1];
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204 [2];
@@ -301367,6 +301468,7 @@ adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/nb0 [4];
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/nb0 [5];
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/nb0 [6];
adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/nb0 [7];
+adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/nb1 [7];
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N7.co [2];
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N15.co [2];
adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N23.co [2];
@@ -305326,8 +305428,6 @@ ms72xx_ctl/ms7200_ctl/state_n [1];
ms72xx_ctl/ms7200_ctl/state_n [2];
ms72xx_ctl/ms7200_ctl/state_n [4];
ms72xx_ctl/ms7200_ctl/state_n [5];
-ms72xx_ctl/ms7210_ctl/N62 [3];
-ms72xx_ctl/ms7210_ctl/N62 [4];
ms72xx_ctl/ms7210_ctl/N612 [0];
ms72xx_ctl/ms7210_ctl/N612 [1];
ms72xx_ctl/ms7210_ctl/cmd_iic [0];
@@ -306977,6 +307077,13 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [0];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [1];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [1];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [2];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [3];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [4];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [5];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [6];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [7];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N262 [13];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [0];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [1];
@@ -307409,8 +307516,12 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped [3];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 [2];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81 [1];
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.co [2];
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.co [4];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81 [2];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81 [3];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81 [4];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81 [5];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.co [1];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.co [3];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N567 [6];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt [0];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt [1];
@@ -308202,7 +308313,6 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddr
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_ctrl [1];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_ctrl [2];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_ctrl [3];
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N328 [2];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_next_state [0];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_next_state [1];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_next_state [2];
@@ -308856,7 +308966,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wclk_ca [0];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wclk_ca [1];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wclk_ca [2];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wclk_ca [3];
-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [1];
+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [0];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [2];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [3];
u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_dqs_resp_tmp [0];
@@ -314337,8 +314447,6 @@ u_ddr_addr_ctr/clk_cnt [16];
u_ddr_addr_ctr/clk_cnt [17];
u_ddr_addr_ctr/clk_cnt [18];
u_ddr_addr_ctr/clk_cnt [19];
-u_ddr_addr_ctr/clk_cnt [20];
-u_ddr_addr_ctr/clk_cnt [21];
u_ddr_addr_ctr/u_rd0_addr_ctr/N157 [2];
u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg [0];
u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg [1];
@@ -315419,29 +315527,29 @@ u_rotate_image/N17_1.co [4];
u_rotate_image/N17_1.co [6];
u_rotate_image/N17_1.co [8];
u_rotate_image/N17_1.co [10];
-u_rotate_image/N290 [0];
-u_rotate_image/N290 [1];
-u_rotate_image/N290 [2];
-u_rotate_image/N290 [3];
-u_rotate_image/N290 [4];
-u_rotate_image/N290 [5];
-u_rotate_image/N290 [6];
-u_rotate_image/N290 [7];
-u_rotate_image/N290 [8];
-u_rotate_image/N290 [9];
-u_rotate_image/N290 [10];
-u_rotate_image/N301 [0];
-u_rotate_image/N301 [1];
-u_rotate_image/N301 [2];
-u_rotate_image/N301 [3];
-u_rotate_image/N301 [4];
-u_rotate_image/N301 [5];
-u_rotate_image/N301 [6];
-u_rotate_image/N301 [7];
-u_rotate_image/N301 [8];
-u_rotate_image/N301 [9];
-u_rotate_image/N301 [10];
-u_rotate_image/N340 [2];
+u_rotate_image/N338 [0];
+u_rotate_image/N338 [1];
+u_rotate_image/N338 [2];
+u_rotate_image/N338 [3];
+u_rotate_image/N338 [4];
+u_rotate_image/N338 [5];
+u_rotate_image/N338 [6];
+u_rotate_image/N338 [7];
+u_rotate_image/N338 [8];
+u_rotate_image/N338 [9];
+u_rotate_image/N338 [10];
+u_rotate_image/N349 [0];
+u_rotate_image/N349 [1];
+u_rotate_image/N349 [2];
+u_rotate_image/N349 [3];
+u_rotate_image/N349 [4];
+u_rotate_image/N349 [5];
+u_rotate_image/N349 [6];
+u_rotate_image/N349 [7];
+u_rotate_image/N349 [8];
+u_rotate_image/N349 [9];
+u_rotate_image/N349 [10];
+u_rotate_image/N396 [2];
u_rotate_image/centerX [0];
u_rotate_image/centerX [1];
u_rotate_image/centerX [2];
@@ -316031,14 +316139,6 @@ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [12];
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [5];
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [6];
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [7];
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [8];
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [9];
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [10];
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [11];
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [12];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rbin [15];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rptr [0];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rptr [1];
@@ -316061,7 +316161,6 @@ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [1];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [2];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [3];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [4];
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [5];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [6];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [7];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [8];
@@ -316073,7 +316172,7 @@ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [14];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [15];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [1];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [3];
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [5];
+u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [4];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [6];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [7];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [8];
@@ -316135,7 +316234,6 @@ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [2];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [3];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [4];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [5];
-u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [6];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [7];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [8];
u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [9];
@@ -317310,7 +317408,6 @@ udp_osd_inst/char_osd_inst/char_buf_reader_inst/N900 [9];
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N900 [10];
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N902 [1];
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N902 [2];
-udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [2];
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [4];
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [5];
udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [6];
@@ -319707,9 +319804,11 @@ udp_wr_mem_inst/N4_1.co [7];
udp_wr_mem_inst/N4_1.co [9];
udp_wr_mem_inst/N4_1.co [11];
udp_wr_mem_inst/N4_1.co [13];
-udp_wr_mem_inst/N30_1.co [1];
-udp_wr_mem_inst/N30_1.co [3];
-udp_wr_mem_inst/N30_1.co [5];
+udp_wr_mem_inst/N30_1.co [2];
+udp_wr_mem_inst/N30_1.co [4];
+udp_wr_mem_inst/N30_1.co [6];
+udp_wr_mem_inst/N784 [1];
+udp_wr_mem_inst/N784 [2];
udp_wr_mem_inst/N790 [2];
udp_wr_mem_inst/N790 [3];
udp_wr_mem_inst/N790 [4];
@@ -323808,6 +323907,49 @@ ntR3906;
ntR3907;
ntR3908;
ntR3909;
+ntR3910;
+ntR3911;
+ntR3912;
+ntR3913;
+ntR3914;
+ntR3915;
+ntR3916;
+ntR3917;
+ntR3918;
+ntR3919;
+ntR3920;
+ntR3921;
+ntR3922;
+ntR3923;
+ntR3924;
+ntR3925;
+ntR3926;
+ntR3927;
+ntR3928;
+ntR3929;
+ntR3930;
+ntR3931;
+ntR3932;
+ntR3933;
+ntR3934;
+ntR3935;
+ntR3936;
+ntR3937;
+ntR3938;
+ntR3939;
+ntR3940;
+ntR3941;
+ntR3942;
+ntR3943;
+ntR3944;
+ntR3945;
+ntR3946;
+ntR3947;
+ntR3948;
+ntR3949;
+ntR3950;
+ntR3951;
+ntR3952;
Clock
clk;1000
diff --git a/project/place_route/multimedia_video_processor_timing_summary_after_hold_fix.txt b/project/place_route/multimedia_video_processor_timing_summary_after_hold_fix.txt
index 1c14e55..88fafeb 100644
--- a/project/place_route/multimedia_video_processor_timing_summary_after_hold_fix.txt
+++ b/project/place_route/multimedia_video_processor_timing_summary_after_hold_fix.txt
@@ -1,21 +1,22 @@
-Design Summary : Some Constraints Violated.
+Design Summary : All Constraints Met.
Setup Summary(Slow Corner):
****************************************************************************************************
TNS Failing TNS Total
Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- cmos1_pclk cmos1_pclk 5.710 0.000 0 251
- cmos2_pclk cmos2_pclk 4.328 0.000 0 251
- hdmi_in_clk hdmi_in_clk 1.168 0.000 0 311
- eth_rxc eth_rxc 1.145 0.000 0 5907
- clk_50m clk_50m 10.898 0.000 0 9498
- clk_200m clk_200m -0.762 -17.604 44 3769
- clk_25m clk_25m 35.453 0.000 0 30
- clk_10m clk_10m 94.284 0.000 0 1099
- clk_720p60Hz clk_720p60Hz 5.528 0.000 0 4786
- clk_20k clk_20k 49995.068 0.000 0 181
- ddrphy_clkin ddrphy_clkin 0.480 0.000 0 18193
+ cmos1_pclk cmos1_pclk 5.348 0.000 0 251
+ cmos2_pclk cmos2_pclk 4.387 0.000 0 251
+ hdmi_in_clk hdmi_in_clk 1.866 0.000 0 311
+ eth_rxc eth_rxc 1.165 0.000 0 5918
+ clk_50m clk_50m 10.408 0.000 0 9493
+ clk_200m clk_200m 1.141 0.000 0 258
+ clk_25m clk_25m 35.531 0.000 0 30
+ clk_10m clk_10m 94.646 0.000 0 1092
+ clk_1080p60Hz clk_1080p60Hz 1.098 0.000 0 3524
+ clk_720p60Hz clk_720p60Hz 6.064 0.000 0 4786
+ clk_20k clk_20k 49994.640 0.000 0 177
+ ddrphy_clkin ddrphy_clkin 2.548 0.000 0 18286
ioclk0 ioclk0 1.692 0.000 0 24
ioclk1 ioclk1 1.692 0.000 0 72
====================================================================================================
@@ -25,17 +26,18 @@ Hold Summary(Slow Corner):
THS Failing THS Total
Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- cmos1_pclk cmos1_pclk 0.185 0.000 0 251
- cmos2_pclk cmos2_pclk 0.412 0.000 0 251
- hdmi_in_clk hdmi_in_clk 0.187 0.000 0 311
- eth_rxc eth_rxc 0.377 0.000 0 5907
- clk_50m clk_50m 0.176 0.000 0 9498
- clk_200m clk_200m 0.239 0.000 0 3769
- clk_25m clk_25m 0.573 0.000 0 30
- clk_10m clk_10m 0.311 0.000 0 1099
- clk_720p60Hz clk_720p60Hz 0.312 0.000 0 4786
- clk_20k clk_20k 0.356 0.000 0 181
- ddrphy_clkin ddrphy_clkin 0.143 0.000 0 18193
+ cmos1_pclk cmos1_pclk 0.171 0.000 0 251
+ cmos2_pclk cmos2_pclk 0.406 0.000 0 251
+ hdmi_in_clk hdmi_in_clk 0.185 0.000 0 311
+ eth_rxc eth_rxc 0.145 0.000 0 5918
+ clk_50m clk_50m 0.188 0.000 0 9493
+ clk_200m clk_200m 0.311 0.000 0 258
+ clk_25m clk_25m 0.549 0.000 0 30
+ clk_10m clk_10m 0.286 0.000 0 1092
+ clk_1080p60Hz clk_1080p60Hz 0.209 0.000 0 3524
+ clk_720p60Hz clk_720p60Hz 0.313 0.000 0 4786
+ clk_20k clk_20k 0.356 0.000 0 177
+ ddrphy_clkin ddrphy_clkin 0.151 0.000 0 18286
ioclk0 ioclk0 0.450 0.000 0 24
ioclk1 ioclk1 0.450 0.000 0 72
====================================================================================================
@@ -45,11 +47,12 @@ Recovery Summary(Slow Corner):
TNS Failing TNS Total
Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- clk_50m clk_50m 16.117 0.000 0 192
- clk_200m clk_200m 1.199 0.000 0 175
- clk_10m clk_10m 97.806 0.000 0 1
- clk_720p60Hz clk_720p60Hz 8.661 0.000 0 717
- ddrphy_clkin ddrphy_clkin 5.561 0.000 0 2569
+ clk_50m clk_50m 15.838 0.000 0 192
+ clk_200m clk_200m 1.238 0.000 0 69
+ clk_10m clk_10m 97.807 0.000 0 1
+ clk_1080p60Hz clk_1080p60Hz 3.317 0.000 0 106
+ clk_720p60Hz clk_720p60Hz 9.028 0.000 0 717
+ ddrphy_clkin ddrphy_clkin 5.761 0.000 0 2569
====================================================================================================
Removal Summary(Slow Corner):
@@ -57,11 +60,12 @@ Removal Summary(Slow Corner):
THS Failing THS Total
Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- clk_50m clk_50m 0.533 0.000 0 192
- clk_200m clk_200m 0.548 0.000 0 175
- clk_10m clk_10m 1.299 0.000 0 1
- clk_720p60Hz clk_720p60Hz 1.206 0.000 0 717
- ddrphy_clkin ddrphy_clkin 0.751 0.000 0 2569
+ clk_50m clk_50m 0.592 0.000 0 192
+ clk_200m clk_200m 0.546 0.000 0 69
+ clk_10m clk_10m 1.253 0.000 0 1
+ clk_1080p60Hz clk_1080p60Hz 1.201 0.000 0 106
+ clk_720p60Hz clk_720p60Hz 0.940 0.000 0 717
+ ddrphy_clkin ddrphy_clkin 0.616 0.000 0 2569
====================================================================================================
Minimum Pulse Width Summary(Slow Corner):
@@ -76,17 +80,18 @@ Setup Summary(Fast Corner):
TNS Failing TNS Total
Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- cmos1_pclk cmos1_pclk 6.782 0.000 0 251
- cmos2_pclk cmos2_pclk 6.122 0.000 0 251
- hdmi_in_clk hdmi_in_clk 2.649 0.000 0 311
- eth_rxc eth_rxc 3.058 0.000 0 5907
- clk_50m clk_50m 13.447 0.000 0 9498
- clk_200m clk_200m 0.729 0.000 0 3769
- clk_25m clk_25m 36.750 0.000 0 30
- clk_10m clk_10m 95.958 0.000 0 1099
- clk_720p60Hz clk_720p60Hz 7.912 0.000 0 4786
- clk_20k clk_20k 49996.415 0.000 0 181
- ddrphy_clkin ddrphy_clkin 3.338 0.000 0 18193
+ cmos1_pclk cmos1_pclk 6.465 0.000 0 251
+ cmos2_pclk cmos2_pclk 5.887 0.000 0 251
+ hdmi_in_clk hdmi_in_clk 3.174 0.000 0 311
+ eth_rxc eth_rxc 3.107 0.000 0 5918
+ clk_50m clk_50m 13.002 0.000 0 9493
+ clk_200m clk_200m 2.144 0.000 0 258
+ clk_25m clk_25m 36.816 0.000 0 30
+ clk_10m clk_10m 96.197 0.000 0 1092
+ clk_1080p60Hz clk_1080p60Hz 2.501 0.000 0 3524
+ clk_720p60Hz clk_720p60Hz 8.248 0.000 0 4786
+ clk_20k clk_20k 49996.134 0.000 0 177
+ ddrphy_clkin ddrphy_clkin 4.710 0.000 0 18286
ioclk0 ioclk0 1.834 0.000 0 24
ioclk1 ioclk1 1.834 0.000 0 72
====================================================================================================
@@ -96,17 +101,18 @@ Hold Summary(Fast Corner):
THS Failing THS Total
Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- cmos1_pclk cmos1_pclk 0.101 0.000 0 251
+ cmos1_pclk cmos1_pclk 0.100 0.000 0 251
cmos2_pclk cmos2_pclk 0.250 0.000 0 251
- hdmi_in_clk hdmi_in_clk 0.101 0.000 0 311
- eth_rxc eth_rxc 0.250 0.000 0 5907
- clk_50m clk_50m 0.135 0.000 0 9498
- clk_200m clk_200m 0.191 0.000 0 3769
- clk_25m clk_25m 0.403 0.000 0 30
- clk_10m clk_10m 0.230 0.000 0 1099
+ hdmi_in_clk hdmi_in_clk 0.102 0.000 0 311
+ eth_rxc eth_rxc 0.064 0.000 0 5918
+ clk_50m clk_50m 0.132 0.000 0 9493
+ clk_200m clk_200m 0.239 0.000 0 258
+ clk_25m clk_25m 0.387 0.000 0 30
+ clk_10m clk_10m 0.231 0.000 0 1092
+ clk_1080p60Hz clk_1080p60Hz 0.155 0.000 0 3524
clk_720p60Hz clk_720p60Hz 0.251 0.000 0 4786
- clk_20k clk_20k 0.253 0.000 0 181
- ddrphy_clkin ddrphy_clkin 0.105 0.000 0 18193
+ clk_20k clk_20k 0.253 0.000 0 177
+ ddrphy_clkin ddrphy_clkin 0.100 0.000 0 18286
ioclk0 ioclk0 0.383 0.000 0 24
ioclk1 ioclk1 0.383 0.000 0 72
====================================================================================================
@@ -116,11 +122,12 @@ Recovery Summary(Fast Corner):
TNS Failing TNS Total
Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- clk_50m clk_50m 17.156 0.000 0 192
- clk_200m clk_200m 2.227 0.000 0 175
- clk_10m clk_10m 98.368 0.000 0 1
- clk_720p60Hz clk_720p60Hz 9.978 0.000 0 717
- ddrphy_clkin ddrphy_clkin 6.834 0.000 0 2569
+ clk_50m clk_50m 17.011 0.000 0 192
+ clk_200m clk_200m 2.226 0.000 0 69
+ clk_10m clk_10m 98.389 0.000 0 1
+ clk_1080p60Hz clk_1080p60Hz 4.325 0.000 0 106
+ clk_720p60Hz clk_720p60Hz 10.187 0.000 0 717
+ ddrphy_clkin ddrphy_clkin 6.941 0.000 0 2569
====================================================================================================
Removal Summary(Fast Corner):
@@ -128,11 +135,12 @@ Removal Summary(Fast Corner):
THS Failing THS Total
Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- clk_50m clk_50m 0.400 0.000 0 192
- clk_200m clk_200m 0.447 0.000 0 175
- clk_10m clk_10m 0.907 0.000 0 1
- clk_720p60Hz clk_720p60Hz 0.824 0.000 0 717
- ddrphy_clkin ddrphy_clkin 0.533 0.000 0 2569
+ clk_50m clk_50m 0.439 0.000 0 192
+ clk_200m clk_200m 0.445 0.000 0 69
+ clk_10m clk_10m 0.866 0.000 0 1
+ clk_1080p60Hz clk_1080p60Hz 0.825 0.000 0 106
+ clk_720p60Hz clk_720p60Hz 0.687 0.000 0 717
+ ddrphy_clkin ddrphy_clkin 0.460 0.000 0 2569
====================================================================================================
Minimum Pulse Width Summary(Fast Corner):
diff --git a/project/place_route/prr.db b/project/place_route/prr.db
index a4d5220..27f80da 100644
--- a/project/place_route/prr.db
+++ b/project/place_route/prr.db
@@ -6499,48 +6499,48 @@
Use of CLMA
- 2694
+ 2666
6450
42
FF
- 8356
+ 8349
38700
22
LUT
- 8529
+ 8468
25800
- 34
+ 33
LUT-FF pairs
- 3368
+ 3365
25800
14
Use of CLMS
- 1700
+ 1728
4250
- 40
+ 41
FF
- 5264
+ 5269
25500
21
LUT
- 5415
+ 5482
17000
- 32
+ 33
LUT-FF pairs
- 2199
+ 2194
17000
13
@@ -6583,9 +6583,9 @@
Use of HARD0N1
- 1334
+ 1340
6672
- 20
+ 21
Use of HSST
@@ -6751,9 +6751,9 @@
Use of USCM
- 16
+ 17
30
- 54
+ 57
USCM dataused
0
@@ -6804,8 +6804,8 @@
multimedia_video_processor
- 13929
- 13620
+ 13927
+ 13618
88
23.5
98.5
@@ -6827,7 +6827,7 @@
0
0
0
- 16
+ 17
U_HDMI_PLL
0
@@ -6857,7 +6857,7 @@
adjust_color_wrapper_inst
- 1127
+ 1128
1096
0
1.5
@@ -6883,7 +6883,7 @@
0
adjust_color_inst
- 1127
+ 1128
1018
0
1.5
@@ -6909,7 +6909,7 @@
0
convert_hsv2rgb_inst
- 69
+ 70
81
0
1.5
@@ -8558,7 +8558,7 @@
image_filiter_inst2
- 946
+ 945
856
0
0
@@ -8584,7 +8584,7 @@
0
hybrid_filter_inst
- 727
+ 726
621
0
0
@@ -9287,7 +9287,7 @@
ms72xx_ctl
- 333
+ 332
236
0
0
@@ -9313,7 +9313,7 @@
0
iic_dri_rx
- 80
+ 81
61
0
0
@@ -9340,7 +9340,7 @@
iic_dri_tx
- 65
+ 64
56
0
0
@@ -9394,7 +9394,7 @@
ms7210_ctl
- 88
+ 87
62
0
0
@@ -9422,7 +9422,7 @@
param_manager_inst
- 666
+ 672
354
0
0
@@ -9529,7 +9529,7 @@
param_filiter1_mode
- 67
+ 69
34
0
0
@@ -9637,7 +9637,7 @@
param_modify_H
- 51
+ 52
22
0
0
@@ -9664,7 +9664,7 @@
param_modify_S
- 28
+ 30
9
0
0
@@ -9691,7 +9691,7 @@
param_modify_V
- 28
+ 29
9
0
0
@@ -9718,7 +9718,7 @@
param_offsetX
- 56
+ 54
25
0
0
@@ -9772,7 +9772,7 @@
param_osd_char_height
- 57
+ 55
24
0
0
@@ -9799,7 +9799,7 @@
param_osd_char_width
- 32
+ 33
11
0
0
@@ -9880,7 +9880,7 @@
param_rotate
- 47
+ 49
21
0
0
@@ -9907,7 +9907,7 @@
param_rotate_A
- 33
+ 34
10
0
0
@@ -9962,7 +9962,7 @@
u_axi_ddr_top
- 5792
+ 5801
6000
88
0
@@ -9988,7 +9988,7 @@
2
I_ipsxb_ddr_top
- 4006
+ 4015
4123
88
0
@@ -10041,7 +10041,7 @@
u_ddrphy_top
- 2351
+ 2363
2360
0
0
@@ -10310,7 +10310,7 @@
ddrphy_info
- 98
+ 101
60
0
0
@@ -10337,7 +10337,7 @@
ddrphy_reset_ctrl
- 77
+ 86
60
0
0
@@ -10363,7 +10363,7 @@
0
ddrphy_pll_lock_debounce
- 44
+ 45
22
0
0
@@ -10471,7 +10471,7 @@
0
i_dqs_group[0].u_ddrphy_data_slice
- 478
+ 479
308
0
0
@@ -10578,7 +10578,7 @@
data_slice_wrlvl
- 108
+ 106
76
0
0
@@ -10632,7 +10632,7 @@
dqsi_rdel_cal
- 169
+ 172
84
0
0
@@ -10687,7 +10687,7 @@
i_dqs_group[1].u_ddrphy_data_slice
- 332
+ 336
262
0
0
@@ -10794,7 +10794,7 @@
data_slice_wrlvl
- 102
+ 105
68
0
0
@@ -10821,7 +10821,7 @@
dqs_rddata_align
- 44
+ 45
74
0
0
@@ -10903,7 +10903,7 @@
i_dqs_group[2].u_ddrphy_data_slice
- 338
+ 334
262
0
0
@@ -10929,7 +10929,7 @@
0
data_slice_dqs_gate_cal
- 81
+ 82
61
0
0
@@ -10982,7 +10982,7 @@
gatecal
- 47
+ 48
35
0
0
@@ -11010,7 +11010,7 @@
data_slice_wrlvl
- 107
+ 106
68
0
0
@@ -11064,7 +11064,7 @@
dqsi_rdel_cal
- 101
+ 97
59
0
0
@@ -11119,7 +11119,7 @@
i_dqs_group[3].u_ddrphy_data_slice
- 341
+ 340
262
0
0
@@ -11226,7 +11226,7 @@
data_slice_wrlvl
- 103
+ 102
68
0
0
@@ -11445,7 +11445,7 @@
u_ipsxb_ddrc_top
- 1654
+ 1651
1761
88
0
@@ -11525,7 +11525,7 @@
mcdq_dcd_top
- 179
+ 178
158
0
0
@@ -11577,7 +11577,7 @@
0
mcdq_dcd_rowaddr
- 17
+ 12
8
0
0
@@ -11605,7 +11605,7 @@
mcdq_dcd_sm
- 51
+ 50
78
0
0
@@ -11633,7 +11633,7 @@
mcdq_dcp_top
- 854
+ 852
626
82
0
@@ -11659,7 +11659,7 @@
0
mcdq_dcp_back_ctrl
- 545
+ 543
406
0
0
@@ -12117,7 +12117,7 @@
TRDA2ACT_LOOP[0].trda2act_timing
- 8
+ 7
5
0
0
@@ -12549,7 +12549,7 @@
mcdq_timing_rd_pass
- 11
+ 10
7
0
0
@@ -12711,7 +12711,7 @@
timing_prea_pass
- 15
+ 16
12
0
0
@@ -12765,7 +12765,7 @@
timing_wr_pass
- 9
+ 8
5
0
0
@@ -13306,7 +13306,7 @@
u_user_cmd_fifo
- 41
+ 42
110
0
0
@@ -14957,8 +14957,8 @@
u_ddr_addr_ctr
- 280
- 434
+ 277
+ 432
0
0
0.5
@@ -15443,7 +15443,7 @@
u_ov5640
- 453
+ 455
504
0
0
@@ -15577,7 +15577,7 @@
coms2_reg_config
- 61
+ 63
36
0
0
@@ -15603,7 +15603,7 @@
1
u1
- 29
+ 31
9
0
0
@@ -16442,7 +16442,7 @@
u_zoom_hdmi_fifo
- 166
+ 148
139
0
0
@@ -16468,7 +16468,7 @@
0
U_ipml_fifo_zoom_hdmi_fifo
- 166
+ 148
139
0
0
@@ -16494,7 +16494,7 @@
0
U_ipml_fifo_ctrl
- 165
+ 147
138
0
0
@@ -17522,7 +17522,7 @@
udp_osd_inst
- 2209
+ 2212
1831
0
0
@@ -17601,7 +17601,7 @@
0
char_buf_reader_inst
- 175
+ 176
129
0
0
@@ -17628,7 +17628,7 @@
char_pic_rom_inst
- 42
+ 41
47
0
0
@@ -17818,7 +17818,7 @@
eth_udp_inst
- 1818
+ 1821
1541
0
0
@@ -17952,7 +17952,7 @@
u_arp
- 423
+ 422
424
0
0
@@ -17978,7 +17978,7 @@
0
u_arp_rx
- 215
+ 214
278
0
0
@@ -18114,7 +18114,7 @@
u_icmp
- 927
+ 929
628
0
0
@@ -18194,7 +18194,7 @@
u_icmp_tx
- 584
+ 586
312
0
0
@@ -18222,7 +18222,7 @@
u_udp
- 161
+ 163
185
0
0
@@ -18248,7 +18248,7 @@
0
u_udp_rx
- 161
+ 163
185
0
0
@@ -18440,7 +18440,7 @@
udp_wr_mem_inst
- 105
+ 106
190
0
0
@@ -18478,10 +18478,10 @@
RAM(GB)
- 0h:2m:39s
- 0h:4m:9s
- 0h:2m:46s
- 1,902
+ 0h:2m:59s
+ 0h:4m:43s
+ 0h:3m:5s
+ 1,901
WINDOWS 10 x86_64
Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz
32
@@ -18634,16 +18634,13 @@
Process macros using "Greedy".
- Design net nt_eth_rxc is routed by general path.
-
-
- Route-2036: The clock path from eth_rxc_ibuf/opit_1:OUT to udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/clk_dll/gopdll:CLK is routed by SRB.
+ Place-2001: The file D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/kkk.rcf can't be opened.
- Design net nt_cmos2_pclk is routed by general path.
+ Design net nt_eth_rxc is routed by general path.
- Route-2036: The clock path from cmos2_pclk_ibuf/opit_1:OUT to clkbufg_6/gopclkbufg:CLK is routed by SRB.
+ Route-2036: The clock path from eth_rxc_ibuf/opit_1:OUT to udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/clk_dll/gopdll:CLK is routed by SRB.
Design net u_ov5640/coms2_reg_config/clk_20k_regdiv is routed by general path.
@@ -18657,6 +18654,18 @@
Route-2036: The clock path from u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv:Q to u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg:CLK is routed by SRB.
+
+ Design net nt_cmos2_pclk is routed by general path.
+
+
+ Route-2036: The clock path from cmos2_pclk_ibuf/opit_1:OUT to clkbufg_7/gopclkbufg:CLK is routed by SRB.
+
+
+ Timing-4105: The worst slack of endpoint udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D of clock eth_rxc is 75ps(fast corner), but required hold violation threshold is 200ps.
+
+
+ STA-3017: There are 1 clock cross SRB paths do not meet the required hold violation threshold(200ps).
+
@@ -18947,7 +18956,7 @@
clkbufg_1/gopclkbufg
USCM_84_108
ntclkbufg_1
- 2506
+ 2505
0
u_sys_pll/u_pll_e3/goppll
CLKOUT0
@@ -18965,8 +18974,18 @@
clkbufg_3/gopclkbufg
- USCM_84_110
+ USCM_84_118
ntclkbufg_3
+ 733
+ 0
+ U_HDMI_PLL/u_pll_e3/goppll
+ CLKOUT0
+ PLL_158_303
+
+
+ clkbufg_4/gopclkbufg
+ USCM_84_110
+ ntclkbufg_4
233
0
u_sys_pll/u_pll_e3/goppll
@@ -18974,9 +18993,9 @@
PLL_158_55
- clkbufg_4/gopclkbufg
+ clkbufg_5/gopclkbufg
USCM_84_111
- ntclkbufg_4
+ ntclkbufg_5
167
0
hdmi_in_clk_ibuf/opit_1
@@ -18984,9 +19003,9 @@
IOL_163_6
- clkbufg_5/gopclkbufg
+ clkbufg_6/gopclkbufg
USCM_84_112
- ntclkbufg_5
+ ntclkbufg_6
118
0
cmos1_pclk_ibuf/opit_1
@@ -18994,9 +19013,9 @@
IOL_171_6
- clkbufg_6/gopclkbufg
- USCM_84_118
- ntclkbufg_6
+ clkbufg_7/gopclkbufg
+ USCM_84_119
+ ntclkbufg_7
118
0
cmos2_pclk_ibuf/opit_1
@@ -19004,9 +19023,9 @@
IOL_39_6
- clkbufg_7/gopclkbufg
+ clkbufg_8/gopclkbufg
USCM_84_114
- ntclkbufg_7
+ ntclkbufg_8
26
0
u_sys_pll/u_pll_e3/goppll
@@ -19017,7 +19036,7 @@
u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg
USCM_84_113
u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- 68
+ 71
0
u_sys_pll/u_pll_e3/goppll
CLKOUT1
@@ -19035,29 +19054,29 @@
u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg
- USCM_84_119
+ USCM_84_120
u_ov5640/coms1_reg_config/clock_20k
18
0
u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv
Q
- CLMA_182_12
+ CLMS_122_9
u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg
- USCM_84_120
+ USCM_84_121
u_ov5640/coms2_reg_config/clock_20k
18
0
u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv
Q
- CLMA_182_25
+ CLMA_122_12
udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg
USCM_84_109
gmii_clk
- 1860
+ 1861
0
udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0
CLKOUT
@@ -19094,7 +19113,7 @@
U_HDMI_PLL/u_pll_e3/goppll
PLL_158_303
CLKIN1
- ntR3907
+ ntR3950
-
-
USCMROUTE_0
@@ -19105,10 +19124,10 @@
U_HDMI_PLL/u_pll_e3/goppll
PLL_158_303
CLKIN2
- ntR2156
+ ntR2187
-
-
- GND_1215
+ GND_1222
Z
HARD0N1_156_305
@@ -19138,10 +19157,10 @@
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll
PLL_158_199
CLKIN2
- ntR2589
+ ntR2620
-
-
- GND_482
+ GND_465
Z
HARD0N1_156_197
@@ -19171,10 +19190,10 @@
u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll
PLL_158_179
CLKIN2
- ntR2593
+ ntR2624
-
-
- GND_1216
+ GND_1220
Z
HARD0N1_156_181
@@ -19204,13 +19223,24 @@
u_sys_pll/u_pll_e3/goppll
PLL_158_55
CLKIN2
- ntR2973
+ ntR3004
-
-
- GND_1214
+ GND_1221
Z
HARD0N1_156_57
+
+ U_HDMI_PLL/u_pll_e3/goppll
+ PLL_158_303
+ CLKOUT0
+ zoom_clk
+ 733
+ 0
+ ...
+ ...
+ ...
+
U_HDMI_PLL/u_pll_e3/goppll
PLL_158_303
@@ -19260,7 +19290,7 @@
PLL_158_55
CLKOUT0
rd3_clk
- 2507
+ 2506
0
...
...
@@ -19270,8 +19300,8 @@
u_sys_pll/u_pll_e3/goppll
PLL_158_55
CLKOUT1
- zoom_clk
- 810
+ ddr_clk
+ 77
0
...
...
diff --git a/project/report_timing/multimedia_video_processor.rtr b/project/report_timing/multimedia_video_processor.rtr
index 3eae1d4..033bfee 100644
--- a/project/report_timing/multimedia_video_processor.rtr
+++ b/project/report_timing/multimedia_video_processor.rtr
@@ -1,7 +1,7 @@
----------------------------------------------------------------------------------------------------
| Tool Version : Fabric Compiler (version 2022.2-SP1-Lite )
-| Date : Sat Nov 11 17:58:35 2023
+| Date : Wed Nov 15 19:40:13 2023
| Design : multimedia_video_processor
| Device : PGL50H
| Speed Grade : -6
@@ -20,8 +20,8 @@ Timing analysis mode : multi corner
Clock Period Waveform Type Loads Loads Sources
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
clk 20.000 {0 10} Declared 0 7 {clk}
- clk_50m 20.000 {0 10} Generated (clk) 2517 0 {u_sys_pll/u_pll_e3/goppll/CLKOUT0}
- clk_200m 5.000 {0 2.5} Generated (clk) 825 5 {u_sys_pll/u_pll_e3/goppll/CLKOUT1}
+ clk_50m 20.000 {0 10} Generated (clk) 2516 0 {u_sys_pll/u_pll_e3/goppll/CLKOUT0}
+ clk_200m 5.000 {0 2.5} Generated (clk) 75 5 {u_sys_pll/u_pll_e3/goppll/CLKOUT1}
ddrphy_clkin 10.000 {0 5} Generated (clk_200m) 5464 0 {u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV}
ioclk0 2.500 {0 1.25} Generated (clk_200m) 11 0 {u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT}
ioclk1 2.500 {0 1.25} Generated (clk_200m) 27 1 {u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT}
@@ -31,12 +31,12 @@ Timing analysis mode : multi corner
clk_25m 40.000 {0 20} Generated (clk) 26 2 {u_sys_pll/u_pll_e3/goppll/CLKOUT3}
clk_20k 50000.000 {0 25000} Generated (clk_25m) 38 0 {u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT}
clk_10m 100.000 {0 50} Generated (clk) 235 0 {u_sys_pll/u_pll_e3/goppll/CLKOUT4}
- clk_1080p60Hz 6.737 {0 3.368} Generated (clk) 0 0 {U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0}
+ clk_1080p60Hz 6.737 {0 3.368} Generated (clk) 750 0 {U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0}
clk_720p60Hz 13.474 {0 6.736} Generated (clk) 1635 1 {U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1}
cmos1_pclk 11.900 {0 5.95} Declared 118 0 {cmos1_pclk}
cmos2_pclk 11.900 {0 5.95} Declared 118 0 {cmos2_pclk}
hdmi_in_clk 6.666 {0 3.333} Declared 167 0 {hdmi_in_clk}
- eth_rxc 8.000 {0 4} Declared 1861 1 {eth_rxc}
+ eth_rxc 8.000 {0 4} Declared 1862 1 {eth_rxc}
==============================================================================================================================================================================================================================
Clock Groups:
@@ -66,39 +66,41 @@ Timing analysis mode : multi corner
Requested Estimated Requested Estimated
Clock Frequency Frequency Period Period Slack
----------------------------------------------------------------------------------------------------
- cmos1_pclk 84.034 MHz 161.186 MHz 11.900 6.204 5.696
- cmos2_pclk 84.034 MHz 131.423 MHz 11.900 7.609 4.291
- hdmi_in_clk 150.015 MHz 180.636 MHz 6.666 5.536 1.130
- eth_rxc 125.000 MHz 144.446 MHz 8.000 6.923 1.077
- clk_50m 50.000 MHz 109.349 MHz 20.000 9.145 10.855
- clk_200m 200.000 MHz 172.771 MHz 5.000 5.788 -0.788
- clk_25m 25.000 MHz 218.293 MHz 40.000 4.581 35.419
- clk_10m 10.000 MHz 171.644 MHz 100.000 5.826 94.174
- clk_720p60Hz 74.219 MHz 124.635 MHz 13.474 8.023 5.450
- clk_20k 0.020 MHz 201.939 MHz 50000.000 4.952 49995.048
- ddrphy_clkin 100.000 MHz 103.605 MHz 10.000 9.652 0.348
+ cmos1_pclk 84.034 MHz 151.630 MHz 11.900 6.595 5.305
+ cmos2_pclk 84.034 MHz 132.398 MHz 11.900 7.553 4.347
+ hdmi_in_clk 150.015 MHz 207.168 MHz 6.666 4.827 1.839
+ eth_rxc 125.000 MHz 143.390 MHz 8.000 6.974 1.026
+ clk_50m 50.000 MHz 103.670 MHz 20.000 9.646 10.354
+ clk_200m 200.000 MHz 257.798 MHz 5.000 3.879 1.121
+ clk_25m 25.000 MHz 222.272 MHz 40.000 4.499 35.501
+ clk_10m 10.000 MHz 184.775 MHz 100.000 5.412 94.588
+ clk_1080p60Hz 148.438 MHz 176.875 MHz 6.737 5.654 1.083
+ clk_720p60Hz 74.219 MHz 133.594 MHz 13.474 7.485 5.988
+ clk_20k 0.020 MHz 185.563 MHz 50000.000 5.389 49994.611
+ ddrphy_clkin 100.000 MHz 132.837 MHz 10.000 7.528 2.472
ioclk0 400.000 MHz 1237.624 MHz 2.500 0.808 1.692
ioclk1 400.000 MHz 1237.624 MHz 2.500 0.808 1.692
====================================================================================================
-Design Summary : Some Constraints Violated.
+Design Summary : All Constraints Met.
Setup Summary(Slow Corner):
****************************************************************************************************
TNS Failing TNS Total
Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- cmos1_pclk cmos1_pclk 5.696 0.000 0 251
- cmos2_pclk cmos2_pclk 4.291 0.000 0 251
- hdmi_in_clk hdmi_in_clk 1.130 0.000 0 311
- eth_rxc eth_rxc 1.077 0.000 0 5907
- clk_50m clk_50m 10.855 0.000 0 9498
- clk_200m clk_200m -0.788 -18.651 44 3769
- clk_25m clk_25m 35.419 0.000 0 30
- clk_10m clk_10m 94.174 0.000 0 1099
- clk_720p60Hz clk_720p60Hz 5.450 0.000 0 4786
- clk_20k clk_20k 49995.048 0.000 0 181
- ddrphy_clkin ddrphy_clkin 0.348 0.000 0 18193
+ cmos1_pclk cmos1_pclk 5.305 0.000 0 251
+ cmos2_pclk cmos2_pclk 4.347 0.000 0 251
+ hdmi_in_clk hdmi_in_clk 1.839 0.000 0 311
+ eth_rxc eth_rxc 1.026 0.000 0 5918
+ clk_50m clk_50m 10.354 0.000 0 9493
+ clk_200m clk_200m 1.121 0.000 0 258
+ clk_25m clk_25m 35.501 0.000 0 30
+ clk_10m clk_10m 94.588 0.000 0 1092
+ clk_1080p60Hz clk_1080p60Hz 1.083 0.000 0 3524
+ clk_720p60Hz clk_720p60Hz 5.988 0.000 0 4786
+ clk_20k clk_20k 49994.611 0.000 0 177
+ ddrphy_clkin ddrphy_clkin 2.472 0.000 0 18286
ioclk0 ioclk0 1.692 0.000 0 24
ioclk1 ioclk1 1.692 0.000 0 72
====================================================================================================
@@ -108,17 +110,18 @@ Hold Summary(Slow Corner):
THS Failing THS Total
Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- cmos1_pclk cmos1_pclk 0.199 0.000 0 251
- cmos2_pclk cmos2_pclk 0.415 0.000 0 251
- hdmi_in_clk hdmi_in_clk 0.191 0.000 0 311
- eth_rxc eth_rxc 0.381 0.000 0 5907
- clk_50m clk_50m 0.182 0.000 0 9498
- clk_200m clk_200m 0.241 0.000 0 3769
- clk_25m clk_25m 0.575 0.000 0 30
- clk_10m clk_10m 0.314 0.000 0 1099
- clk_720p60Hz clk_720p60Hz 0.313 0.000 0 4786
- clk_20k clk_20k 0.376 0.000 0 181
- ddrphy_clkin ddrphy_clkin 0.149 0.000 0 18193
+ cmos1_pclk cmos1_pclk 0.175 0.000 0 251
+ cmos2_pclk cmos2_pclk 0.407 0.000 0 251
+ hdmi_in_clk hdmi_in_clk 0.189 0.000 0 311
+ eth_rxc eth_rxc 0.157 0.000 0 5918
+ clk_50m clk_50m 0.201 0.000 0 9493
+ clk_200m clk_200m 0.315 0.000 0 258
+ clk_25m clk_25m 0.550 0.000 0 30
+ clk_10m clk_10m 0.287 0.000 0 1092
+ clk_1080p60Hz clk_1080p60Hz 0.212 0.000 0 3524
+ clk_720p60Hz clk_720p60Hz 0.314 0.000 0 4786
+ clk_20k clk_20k 0.372 0.000 0 177
+ ddrphy_clkin ddrphy_clkin 0.161 0.000 0 18286
ioclk0 ioclk0 0.450 0.000 0 24
ioclk1 ioclk1 0.450 0.000 0 72
====================================================================================================
@@ -128,11 +131,12 @@ Recovery Summary(Slow Corner):
TNS Failing TNS Total
Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- clk_50m clk_50m 16.039 0.000 0 192
- clk_200m clk_200m 1.103 0.000 0 175
- clk_10m clk_10m 97.793 0.000 0 1
- clk_720p60Hz clk_720p60Hz 8.580 0.000 0 717
- ddrphy_clkin ddrphy_clkin 5.474 0.000 0 2569
+ clk_50m clk_50m 15.776 0.000 0 192
+ clk_200m clk_200m 1.149 0.000 0 69
+ clk_10m clk_10m 97.797 0.000 0 1
+ clk_1080p60Hz clk_1080p60Hz 3.268 0.000 0 106
+ clk_720p60Hz clk_720p60Hz 8.940 0.000 0 717
+ ddrphy_clkin ddrphy_clkin 5.676 0.000 0 2569
====================================================================================================
Removal Summary(Slow Corner):
@@ -140,11 +144,12 @@ Removal Summary(Slow Corner):
THS Failing THS Total
Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- clk_50m clk_50m 0.555 0.000 0 192
- clk_200m clk_200m 0.554 0.000 0 175
- clk_10m clk_10m 1.312 0.000 0 1
- clk_720p60Hz clk_720p60Hz 1.244 0.000 0 717
- ddrphy_clkin ddrphy_clkin 0.779 0.000 0 2569
+ clk_50m clk_50m 0.610 0.000 0 192
+ clk_200m clk_200m 0.555 0.000 0 69
+ clk_10m clk_10m 1.263 0.000 0 1
+ clk_1080p60Hz clk_1080p60Hz 1.249 0.000 0 106
+ clk_720p60Hz clk_720p60Hz 0.984 0.000 0 717
+ ddrphy_clkin ddrphy_clkin 0.637 0.000 0 2569
====================================================================================================
Minimum Pulse Width Summary(Slow Corner):
@@ -155,11 +160,12 @@ Minimum Pulse Width Summary(Slow Corner):
cmos1_pclk 5.052 0.000 0 118
cmos2_pclk 5.052 0.000 0 118
hdmi_in_clk 2.435 0.000 0 167
- eth_rxc 2.483 0.000 0 1861
- clk_50m 8.862 0.000 0 2517
- clk_200m 1.362 0.000 0 825
- clk_25m 19.580 0.000 0 26
+ eth_rxc 2.483 0.000 0 1862
+ clk_50m 8.862 0.000 0 2516
+ clk_200m 1.880 0.000 0 75
+ clk_25m 19.380 0.000 0 26
clk_10m 49.102 0.000 0 235
+ clk_1080p60Hz 2.230 0.000 0 750
clk_720p60Hz 5.598 0.000 0 1635
clk_20k 24999.102 0.000 0 38
ddrphy_clkin 3.100 0.000 0 5464
@@ -174,17 +180,18 @@ Setup Summary(Fast Corner):
TNS Failing TNS Total
Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- cmos1_pclk cmos1_pclk 6.761 0.000 0 251
- cmos2_pclk cmos2_pclk 6.092 0.000 0 251
- hdmi_in_clk hdmi_in_clk 2.618 0.000 0 311
- eth_rxc eth_rxc 3.025 0.000 0 5907
- clk_50m clk_50m 13.413 0.000 0 9498
- clk_200m clk_200m 0.707 0.000 0 3769
- clk_25m clk_25m 36.725 0.000 0 30
- clk_10m clk_10m 95.894 0.000 0 1099
- clk_720p60Hz clk_720p60Hz 7.848 0.000 0 4786
- clk_20k clk_20k 49996.400 0.000 0 181
- ddrphy_clkin ddrphy_clkin 3.245 0.000 0 18193
+ cmos1_pclk cmos1_pclk 6.435 0.000 0 251
+ cmos2_pclk cmos2_pclk 5.869 0.000 0 251
+ hdmi_in_clk hdmi_in_clk 3.150 0.000 0 311
+ eth_rxc eth_rxc 3.051 0.000 0 5918
+ clk_50m clk_50m 12.954 0.000 0 9493
+ clk_200m clk_200m 2.129 0.000 0 258
+ clk_25m clk_25m 36.784 0.000 0 30
+ clk_10m clk_10m 96.148 0.000 0 1092
+ clk_1080p60Hz clk_1080p60Hz 2.488 0.000 0 3524
+ clk_720p60Hz clk_720p60Hz 8.191 0.000 0 4786
+ clk_20k clk_20k 49996.111 0.000 0 177
+ ddrphy_clkin ddrphy_clkin 4.645 0.000 0 18286
ioclk0 ioclk0 1.834 0.000 0 24
ioclk1 ioclk1 1.834 0.000 0 72
====================================================================================================
@@ -194,17 +201,18 @@ Hold Summary(Fast Corner):
THS Failing THS Total
Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- cmos1_pclk cmos1_pclk 0.108 0.000 0 251
- cmos2_pclk cmos2_pclk 0.254 0.000 0 251
- hdmi_in_clk hdmi_in_clk 0.106 0.000 0 311
- eth_rxc eth_rxc 0.252 0.000 0 5907
- clk_50m clk_50m 0.139 0.000 0 9498
- clk_200m clk_200m 0.196 0.000 0 3769
- clk_25m clk_25m 0.406 0.000 0 30
- clk_10m clk_10m 0.232 0.000 0 1099
- clk_720p60Hz clk_720p60Hz 0.251 0.000 0 4786
- clk_20k clk_20k 0.269 0.000 0 181
- ddrphy_clkin ddrphy_clkin 0.111 0.000 0 18193
+ cmos1_pclk cmos1_pclk 0.104 0.000 0 251
+ cmos2_pclk cmos2_pclk 0.250 0.000 0 251
+ hdmi_in_clk hdmi_in_clk 0.103 0.000 0 311
+ eth_rxc eth_rxc 0.075 0.000 0 5918
+ clk_50m clk_50m 0.143 0.000 0 9493
+ clk_200m clk_200m 0.242 0.000 0 258
+ clk_25m clk_25m 0.388 0.000 0 30
+ clk_10m clk_10m 0.232 0.000 0 1092
+ clk_1080p60Hz clk_1080p60Hz 0.160 0.000 0 3524
+ clk_720p60Hz clk_720p60Hz 0.252 0.000 0 4786
+ clk_20k clk_20k 0.273 0.000 0 177
+ ddrphy_clkin ddrphy_clkin 0.115 0.000 0 18286
ioclk0 ioclk0 0.383 0.000 0 24
ioclk1 ioclk1 0.383 0.000 0 72
====================================================================================================
@@ -214,11 +222,12 @@ Recovery Summary(Fast Corner):
TNS Failing TNS Total
Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- clk_50m clk_50m 17.096 0.000 0 192
- clk_200m clk_200m 2.157 0.000 0 175
- clk_10m clk_10m 98.359 0.000 0 1
- clk_720p60Hz clk_720p60Hz 9.915 0.000 0 717
- ddrphy_clkin ddrphy_clkin 6.770 0.000 0 2569
+ clk_50m clk_50m 16.962 0.000 0 192
+ clk_200m clk_200m 2.160 0.000 0 69
+ clk_10m clk_10m 98.381 0.000 0 1
+ clk_1080p60Hz clk_1080p60Hz 4.288 0.000 0 106
+ clk_720p60Hz clk_720p60Hz 10.123 0.000 0 717
+ ddrphy_clkin ddrphy_clkin 6.879 0.000 0 2569
====================================================================================================
Removal Summary(Fast Corner):
@@ -226,11 +235,12 @@ Removal Summary(Fast Corner):
THS Failing THS Total
Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints
----------------------------------------------------------------------------------------------------
- clk_50m clk_50m 0.418 0.000 0 192
- clk_200m clk_200m 0.452 0.000 0 175
- clk_10m clk_10m 0.915 0.000 0 1
- clk_720p60Hz clk_720p60Hz 0.851 0.000 0 717
- ddrphy_clkin ddrphy_clkin 0.555 0.000 0 2569
+ clk_50m clk_50m 0.454 0.000 0 192
+ clk_200m clk_200m 0.452 0.000 0 69
+ clk_10m clk_10m 0.873 0.000 0 1
+ clk_1080p60Hz clk_1080p60Hz 0.860 0.000 0 106
+ clk_720p60Hz clk_720p60Hz 0.722 0.000 0 717
+ ddrphy_clkin ddrphy_clkin 0.482 0.000 0 2569
====================================================================================================
Minimum Pulse Width Summary(Fast Corner):
@@ -241,11 +251,12 @@ Minimum Pulse Width Summary(Fast Corner):
cmos1_pclk 5.232 0.000 0 118
cmos2_pclk 5.232 0.000 0 118
hdmi_in_clk 2.615 0.000 0 167
- eth_rxc 2.787 0.000 0 1861
- clk_50m 9.090 0.000 0 2517
- clk_200m 1.590 0.000 0 825
- clk_25m 19.664 0.000 0 26
+ eth_rxc 2.787 0.000 0 1862
+ clk_50m 9.090 0.000 0 2516
+ clk_200m 2.004 0.000 0 75
+ clk_25m 19.504 0.000 0 26
clk_10m 49.282 0.000 0 235
+ clk_1080p60Hz 2.458 0.000 0 750
clk_720p60Hz 5.826 0.000 0 1635
clk_20k 24999.282 0.000 0 38
ddrphy_clkin 3.480 0.000 0 5464
@@ -259,8 +270,8 @@ Slow Corner
****************************************************************************************************
====================================================================================================
-Startpoint : cmos1_data[5] (port)
-Endpoint : u_ov5640/cmos1_d_d0[5]/opit_0/D
+Startpoint : cmos1_href (port)
+Endpoint : u_ov5640/cmos1_href_d0/opit_0/D
Path Group : cmos1_pclk
Path Type : max (slow corner)
Path Class : sequential timing path
@@ -273,20 +284,18 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 0.000 0.000 r
- Input external delay 1.000 1.000 r
+ Input external delay 1.000 1.000 f
- AB11 0.000 1.000 r cmos1_data[5] (port)
- net (fanout=1) 0.077 1.077 cmos1_data[5]
- IOBS_TB_156_0/DIN td 2.166 3.243 r cmos1_data_ibuf[5]/opit_0/O
- net (fanout=1) 0.000 3.243 cmos1_data_ibuf[5]/ntD
- IOL_159_5/RX_DATA_DD td 0.126 3.369 r cmos1_data_ibuf[5]/opit_1/OUT
- net (fanout=1) 2.329 5.698 nt_cmos1_data[5]
- CLMS_322_9/Y6CD td 0.149 5.847 r CLKROUTE_0/Z
- net (fanout=1) 5.216 11.063 ntR3901
- CLMS_146_9/M0 r u_ov5640/cmos1_d_d0[5]/opit_0/D
+ AB10 0.000 1.000 f cmos1_href (port)
+ net (fanout=1) 0.063 1.063 cmos1_href
+ IOBR_TB_148_0/DIN td 1.367 2.430 f cmos1_href_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.430 cmos1_href_ibuf/ntD
+ IOL_151_5/RX_DATA_DD td 0.127 2.557 f cmos1_href_ibuf/opit_1/OUT
+ net (fanout=1) 8.888 11.445 nt_cmos1_href
+ CLMA_150_12/M1 f u_ov5640/cmos1_href_d0/opit_0/D
- Data arrival time 11.063 Logic Levels: 3
- Logic: 2.441ns(24.257%), Route: 7.622ns(75.743%)
+ Data arrival time 11.445 Logic Levels: 2
+ Logic: 1.494ns(14.303%), Route: 8.951ns(85.697%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 11.900 11.900 r
@@ -296,26 +305,26 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 13.023 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.048 13.071 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 2.486 15.557 _N64
- USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 17.088 ntclkbufg_5
- CLMS_146_9/CLK r u_ov5640/cmos1_d_d0[5]/opit_0/CLK
+ USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 1.531 17.088 ntclkbufg_6
+ CLMA_150_12/CLK r u_ov5640/cmos1_href_d0/opit_0/CLK
clock pessimism 0.000 17.088
clock uncertainty -0.250 16.838
- Setup time -0.079 16.759
+ Setup time -0.088 16.750
- Data required time 16.759
+ Data required time 16.750
----------------------------------------------------------------------------------------------------
- Data required time 16.759
- Data arrival time 11.063
+ Data required time 16.750
+ Data arrival time 11.445
----------------------------------------------------------------------------------------------------
- Slack (MET) 5.696
+ Slack (MET) 5.305
====================================================================================================
====================================================================================================
-Startpoint : cmos1_data[4] (port)
-Endpoint : u_ov5640/cmos1_d_d0[4]/opit_0/D
+Startpoint : cmos1_data[6] (port)
+Endpoint : u_ov5640/cmos1_d_d0[6]/opit_0/D
Path Group : cmos1_pclk
Path Type : max (slow corner)
Path Class : sequential timing path
@@ -330,16 +339,16 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Clock cmos1_pclk (rising edge) 0.000 0.000 r
Input external delay 1.000 1.000 r
- W11 0.000 1.000 r cmos1_data[4] (port)
- net (fanout=1) 0.041 1.041 cmos1_data[4]
- IOBS_TB_132_0/DIN td 2.166 3.207 r cmos1_data_ibuf[4]/opit_0/O
- net (fanout=1) 0.000 3.207 cmos1_data_ibuf[4]/ntD
- IOL_135_5/RX_DATA_DD td 0.126 3.333 r cmos1_data_ibuf[4]/opit_1/OUT
- net (fanout=1) 7.830 11.163 nt_cmos1_data[4]
- CLMS_134_13/AD r u_ov5640/cmos1_d_d0[4]/opit_0/D
+ AA10 0.000 1.000 r cmos1_data[6] (port)
+ net (fanout=1) 0.080 1.080 cmos1_data[6]
+ IOBD_149_0/DIN td 2.166 3.246 r cmos1_data_ibuf[6]/opit_0/O
+ net (fanout=1) 0.000 3.246 cmos1_data_ibuf[6]/ntD
+ IOL_151_6/RX_DATA_DD td 0.126 3.372 r cmos1_data_ibuf[6]/opit_1/OUT
+ net (fanout=1) 7.463 10.835 nt_cmos1_data[6]
+ CLMS_150_41/M1 r u_ov5640/cmos1_d_d0[6]/opit_0/D
- Data arrival time 11.163 Logic Levels: 2
- Logic: 2.292ns(22.552%), Route: 7.871ns(77.448%)
+ Data arrival time 10.835 Logic Levels: 2
+ Logic: 2.292ns(23.305%), Route: 7.543ns(76.695%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 11.900 11.900 r
@@ -349,26 +358,26 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 13.023 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.048 13.071 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 2.486 15.557 _N64
- USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 17.088 ntclkbufg_5
- CLMS_134_13/CLK r u_ov5640/cmos1_d_d0[4]/opit_0/CLK
+ USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 1.531 17.088 ntclkbufg_6
+ CLMS_150_41/CLK r u_ov5640/cmos1_d_d0[6]/opit_0/CLK
clock pessimism 0.000 17.088
clock uncertainty -0.250 16.838
- Setup time 0.029 16.867
+ Setup time -0.079 16.759
- Data required time 16.867
+ Data required time 16.759
----------------------------------------------------------------------------------------------------
- Data required time 16.867
- Data arrival time 11.163
+ Data required time 16.759
+ Data arrival time 10.835
----------------------------------------------------------------------------------------------------
- Slack (MET) 5.704
+ Slack (MET) 5.924
====================================================================================================
====================================================================================================
-Startpoint : cmos1_href (port)
-Endpoint : u_ov5640/cmos1_href_d0/opit_0/D
+Startpoint : cmos1_data[0] (port)
+Endpoint : u_ov5640/cmos1_d_d0[0]/opit_0/D
Path Group : cmos1_pclk
Path Type : max (slow corner)
Path Class : sequential timing path
@@ -381,18 +390,18 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 0.000 0.000 r
- Input external delay 1.000 1.000 f
+ Input external delay 1.000 1.000 r
- AB10 0.000 1.000 f cmos1_href (port)
- net (fanout=1) 0.063 1.063 cmos1_href
- IOBR_TB_148_0/DIN td 1.367 2.430 f cmos1_href_ibuf/opit_0/O
- net (fanout=1) 0.000 2.430 cmos1_href_ibuf/ntD
- IOL_151_5/RX_DATA_DD td 0.127 2.557 f cmos1_href_ibuf/opit_1/OUT
- net (fanout=1) 8.583 11.140 nt_cmos1_href
- CLMS_146_9/AD f u_ov5640/cmos1_href_d0/opit_0/D
+ V11 0.000 1.000 r cmos1_data[0] (port)
+ net (fanout=1) 0.053 1.053 cmos1_data[0]
+ IOBD_133_0/DIN td 2.166 3.219 r cmos1_data_ibuf[0]/opit_0/O
+ net (fanout=1) 0.000 3.219 cmos1_data_ibuf[0]/ntD
+ IOL_135_6/RX_DATA_DD td 0.126 3.345 r cmos1_data_ibuf[0]/opit_1/OUT
+ net (fanout=1) 7.485 10.830 nt_cmos1_data[0]
+ CLMS_134_45/CD r u_ov5640/cmos1_d_d0[0]/opit_0/D
- Data arrival time 11.140 Logic Levels: 2
- Logic: 1.494ns(14.734%), Route: 8.646ns(85.266%)
+ Data arrival time 10.830 Logic Levels: 2
+ Logic: 2.292ns(23.316%), Route: 7.538ns(76.684%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 11.900 11.900 r
@@ -402,9 +411,9 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 13.023 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.048 13.071 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 2.486 15.557 _N64
- USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 17.088 ntclkbufg_5
- CLMS_146_9/CLK r u_ov5640/cmos1_href_d0/opit_0/CLK
+ USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 1.531 17.088 ntclkbufg_6
+ CLMS_134_45/CLK r u_ov5640/cmos1_d_d0[0]/opit_0/CLK
clock pessimism 0.000 17.088
clock uncertainty -0.250 16.838
@@ -413,22 +422,22 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 16.867
----------------------------------------------------------------------------------------------------
Data required time 16.867
- Data arrival time 11.140
+ Data arrival time 10.830
----------------------------------------------------------------------------------------------------
- Slack (MET) 5.727
+ Slack (MET) 6.037
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
+Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK
Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0
Path Group : cmos1_pclk
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 5.521
Launch Clock Delay : 5.188
- Clock Pessimism Removal : -0.333
+ Clock Pessimism Removal : -0.304
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -440,16 +449,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.123 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.048 1.171 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 2.486 3.657 _N64
- USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 5.188 ntclkbufg_5
- CLMA_138_36/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
+ USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 1.531 5.188 ntclkbufg_6
+ CLMA_138_60/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK
- CLMA_138_36/Q3 tco 0.221 5.409 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/Q
- net (fanout=24) 0.098 5.507 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wfull
- CLMA_138_36/B0 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0
+ CLMA_138_60/Q0 tco 0.222 5.410 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0
+ net (fanout=5) 0.088 5.498 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [8]
+ CLMA_138_61/A0 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0
- Data arrival time 5.507 Logic Levels: 0
- Logic: 0.221ns(69.279%), Route: 0.098ns(30.721%)
+ Data arrival time 5.498 Logic Levels: 0
+ Logic: 0.222ns(71.613%), Route: 0.088ns(28.387%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 0.000 0.000 r
@@ -459,33 +468,33 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.330 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.076 1.406 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 2.530 3.936 _N64
- USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 1.585 5.521 ntclkbufg_5
- CLMA_138_36/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK
- clock pessimism -0.333 5.188
- clock uncertainty 0.200 5.388
+ USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 1.585 5.521 ntclkbufg_6
+ CLMA_138_61/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK
+ clock pessimism -0.304 5.217
+ clock uncertainty 0.200 5.417
- Hold time -0.080 5.308
+ Hold time -0.094 5.323
- Data required time 5.308
+ Data required time 5.323
----------------------------------------------------------------------------------------------------
- Data required time 5.308
- Data arrival time 5.507
+ Data required time 5.323
+ Data arrival time 5.498
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.199
+ Slack (MET) 0.175
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK
-Endpoint : u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/L0
+Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK
+Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0
Path Group : cmos1_pclk
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 5.521
Launch Clock Delay : 5.188
- Clock Pessimism Removal : -0.333
+ Clock Pessimism Removal : -0.304
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -497,16 +506,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.123 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.048 1.171 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 2.486 3.657 _N64
- USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 5.188 ntclkbufg_5
- CLMA_154_28/CLK r u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK
+ USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 1.531 5.188 ntclkbufg_6
+ CLMA_138_56/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK
- CLMA_154_28/Q0 tco 0.222 5.410 f u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/Q
- net (fanout=2) 0.085 5.495 u_ov5640/u_mix_image/cnt0_h [0]
- CLMA_154_28/A0 f u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/L0
+ CLMA_138_56/Q1 tco 0.224 5.412 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Q1
+ net (fanout=5) 0.089 5.501 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [5]
+ CLMA_138_57/C0 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0
- Data arrival time 5.495 Logic Levels: 0
- Logic: 0.222ns(72.313%), Route: 0.085ns(27.687%)
+ Data arrival time 5.501 Logic Levels: 0
+ Logic: 0.224ns(71.565%), Route: 0.089ns(28.435%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 0.000 0.000 r
@@ -516,33 +525,33 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.330 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.076 1.406 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 2.530 3.936 _N64
- USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 1.585 5.521 ntclkbufg_5
- CLMA_154_28/CLK r u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK
- clock pessimism -0.333 5.188
- clock uncertainty 0.200 5.388
+ USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 1.585 5.521 ntclkbufg_6
+ CLMA_138_57/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK
+ clock pessimism -0.304 5.217
+ clock uncertainty 0.200 5.417
- Hold time -0.094 5.294
+ Hold time -0.093 5.324
- Data required time 5.294
+ Data required time 5.324
----------------------------------------------------------------------------------------------------
- Data required time 5.294
- Data arrival time 5.495
+ Data required time 5.324
+ Data arrival time 5.501
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.201
+ Slack (MET) 0.177
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK
-Endpoint : u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/L0
+Startpoint : u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK
+Endpoint : u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D
Path Group : cmos1_pclk
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 5.521
Launch Clock Delay : 5.188
- Clock Pessimism Removal : -0.333
+ Clock Pessimism Removal : -0.304
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -554,16 +563,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.123 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.048 1.171 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 2.486 3.657 _N64
- USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 5.188 ntclkbufg_5
- CLMA_150_28/CLK r u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK
+ USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 1.531 5.188 ntclkbufg_6
+ CLMA_138_44/CLK r u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK
- CLMA_150_28/Q0 tco 0.222 5.410 f u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/Q
- net (fanout=2) 0.085 5.495 u_ov5640/u_mix_image/image1_en
- CLMA_150_28/A0 f u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/L0
+ CLMA_138_44/Y0 tco 0.284 5.472 f u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/Q
+ net (fanout=1) 0.191 5.663 u_ov5640/cmos1_8_16bit/pdata_i2 [4]
+ CLMA_138_45/AD f u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D
- Data arrival time 5.495 Logic Levels: 0
- Logic: 0.222ns(72.313%), Route: 0.085ns(27.687%)
+ Data arrival time 5.663 Logic Levels: 0
+ Logic: 0.284ns(59.789%), Route: 0.191ns(40.211%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 0.000 0.000 r
@@ -573,31 +582,31 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.330 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.076 1.406 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 2.530 3.936 _N64
- USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 1.585 5.521 ntclkbufg_5
- CLMA_150_28/CLK r u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK
- clock pessimism -0.333 5.188
- clock uncertainty 0.200 5.388
+ USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 1.585 5.521 ntclkbufg_6
+ CLMA_138_45/CLK r u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/CLK
+ clock pessimism -0.304 5.217
+ clock uncertainty 0.200 5.417
- Hold time -0.094 5.294
+ Hold time 0.053 5.470
- Data required time 5.294
+ Data required time 5.470
----------------------------------------------------------------------------------------------------
- Data required time 5.294
- Data arrival time 5.495
+ Data required time 5.470
+ Data arrival time 5.663
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.201
+ Slack (MET) 0.193
====================================================================================================
====================================================================================================
-Startpoint : cmos2_data[7] (port)
-Endpoint : u_ov5640/cmos2_d_d0[7]/opit_0/D
+Startpoint : cmos2_data[6] (port)
+Endpoint : u_ov5640/cmos2_d_d0[6]/opit_0/D
Path Group : cmos2_pclk
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.551
+Clock Skew : 5.548 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.548
Launch Clock Delay : 0.000
Clock Pessimism Removal : 0.000
@@ -605,18 +614,18 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 0.000 0.000 r
- Input external delay 1.000 1.000 r
+ Input external delay 1.000 1.000 f
- AB9 0.000 1.000 r cmos2_data[7] (port)
- net (fanout=1) 0.080 1.080 cmos2_data[7]
- IOBS_TB_128_0/DIN td 2.166 3.246 r cmos2_data_ibuf[7]/opit_0/O
- net (fanout=1) 0.000 3.246 cmos2_data_ibuf[7]/ntD
- IOL_131_5/RX_DATA_DD td 0.126 3.372 r cmos2_data_ibuf[7]/opit_1/OUT
- net (fanout=1) 9.459 12.831 nt_cmos2_data[7]
- CLMS_130_37/M2 r u_ov5640/cmos2_d_d0[7]/opit_0/D
+ Y9 0.000 1.000 f cmos2_data[6] (port)
+ net (fanout=1) 0.078 1.078 cmos2_data[6]
+ IOBD_129_0/DIN td 1.513 2.591 f cmos2_data_ibuf[6]/opit_0/O
+ net (fanout=1) 0.000 2.591 cmos2_data_ibuf[6]/ntD
+ IOL_131_6/RX_DATA_DD td 0.127 2.718 f cmos2_data_ibuf[6]/opit_1/OUT
+ net (fanout=1) 10.045 12.763 nt_cmos2_data[6]
+ CLMA_138_8/M1 f u_ov5640/cmos2_d_d0[6]/opit_0/D
- Data arrival time 12.831 Logic Levels: 2
- Logic: 2.292ns(19.373%), Route: 9.539ns(80.627%)
+ Data arrival time 12.763 Logic Levels: 2
+ Logic: 1.640ns(13.942%), Route: 10.123ns(86.058%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 11.900 11.900 r
@@ -625,32 +634,32 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 1.047 13.018 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 13.018 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.082 13.100 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 2.820 15.920 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 15.920 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 17.451 ntclkbufg_6
- CLMS_130_37/CLK r u_ov5640/cmos2_d_d0[7]/opit_0/CLK
- clock pessimism 0.000 17.451
- clock uncertainty -0.250 17.201
+ net (fanout=1) 2.817 15.917 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 15.917 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 1.531 17.448 ntclkbufg_7
+ CLMA_138_8/CLK r u_ov5640/cmos2_d_d0[6]/opit_0/CLK
+ clock pessimism 0.000 17.448
+ clock uncertainty -0.250 17.198
- Setup time -0.079 17.122
+ Setup time -0.088 17.110
- Data required time 17.122
+ Data required time 17.110
----------------------------------------------------------------------------------------------------
- Data required time 17.122
- Data arrival time 12.831
+ Data required time 17.110
+ Data arrival time 12.763
----------------------------------------------------------------------------------------------------
- Slack (MET) 4.291
+ Slack (MET) 4.347
====================================================================================================
====================================================================================================
-Startpoint : cmos2_data[2] (port)
-Endpoint : u_ov5640/cmos2_d_d0[2]/opit_0/D
+Startpoint : cmos2_data[5] (port)
+Endpoint : u_ov5640/cmos2_d_d0[5]/opit_0/D
Path Group : cmos2_pclk
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.551
+Clock Skew : 5.548 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.548
Launch Clock Delay : 0.000
Clock Pessimism Removal : 0.000
@@ -658,18 +667,20 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 0.000 0.000 r
- Input external delay 1.000 1.000 r
+ Input external delay 1.000 1.000 f
- T8 0.000 1.000 r cmos2_data[2] (port)
- net (fanout=1) 0.057 1.057 cmos2_data[2]
- IOBD_61_0/DIN td 2.166 3.223 r cmos2_data_ibuf[2]/opit_0/O
- net (fanout=1) 0.000 3.223 cmos2_data_ibuf[2]/ntD
- IOL_63_6/RX_DATA_DD td 0.126 3.349 r cmos2_data_ibuf[2]/opit_1/OUT
- net (fanout=1) 8.903 12.252 nt_cmos2_data[2]
- CLMA_134_40/M3 r u_ov5640/cmos2_d_d0[2]/opit_0/D
+ AB8 0.000 1.000 f cmos2_data[5] (port)
+ net (fanout=1) 0.084 1.084 cmos2_data[5]
+ IOBS_TB_116_0/DIN td 1.513 2.597 f cmos2_data_ibuf[5]/opit_0/O
+ net (fanout=1) 0.000 2.597 cmos2_data_ibuf[5]/ntD
+ IOL_119_5/RX_DATA_DD td 0.127 2.724 f cmos2_data_ibuf[5]/opit_1/OUT
+ net (fanout=1) 1.531 4.255 nt_cmos2_data[5]
+ CLMS_198_49/Y6CD td 0.134 4.389 f CLKROUTE_0/Z
+ net (fanout=1) 8.355 12.744 ntR3940
+ CLMA_138_8/M0 f u_ov5640/cmos2_d_d0[5]/opit_0/D
- Data arrival time 12.252 Logic Levels: 2
- Logic: 2.292ns(20.370%), Route: 8.960ns(79.630%)
+ Data arrival time 12.744 Logic Levels: 3
+ Logic: 1.774ns(15.106%), Route: 9.970ns(84.894%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 11.900 11.900 r
@@ -678,32 +689,32 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 1.047 13.018 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 13.018 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.082 13.100 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 2.820 15.920 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 15.920 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 17.451 ntclkbufg_6
- CLMA_134_40/CLK r u_ov5640/cmos2_d_d0[2]/opit_0/CLK
- clock pessimism 0.000 17.451
- clock uncertainty -0.250 17.201
+ net (fanout=1) 2.817 15.917 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 15.917 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 1.531 17.448 ntclkbufg_7
+ CLMA_138_8/CLK r u_ov5640/cmos2_d_d0[5]/opit_0/CLK
+ clock pessimism 0.000 17.448
+ clock uncertainty -0.250 17.198
- Setup time -0.079 17.122
+ Setup time -0.088 17.110
- Data required time 17.122
+ Data required time 17.110
----------------------------------------------------------------------------------------------------
- Data required time 17.122
- Data arrival time 12.252
+ Data required time 17.110
+ Data arrival time 12.744
----------------------------------------------------------------------------------------------------
- Slack (MET) 4.870
+ Slack (MET) 4.366
====================================================================================================
====================================================================================================
-Startpoint : cmos2_data[5] (port)
-Endpoint : u_ov5640/cmos2_d_d0[5]/opit_0/D
+Startpoint : cmos2_href (port)
+Endpoint : u_ov5640/cmos2_href_d0/opit_0/D
Path Group : cmos2_pclk
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.551
+Clock Skew : 5.595 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.595
Launch Clock Delay : 0.000
Clock Pessimism Removal : 0.000
@@ -713,16 +724,20 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Clock cmos2_pclk (rising edge) 0.000 0.000 r
Input external delay 1.000 1.000 f
- AB8 0.000 1.000 f cmos2_data[5] (port)
- net (fanout=1) 0.084 1.084 cmos2_data[5]
- IOBS_TB_116_0/DIN td 1.513 2.597 f cmos2_data_ibuf[5]/opit_0/O
- net (fanout=1) 0.000 2.597 cmos2_data_ibuf[5]/ntD
- IOL_119_5/RX_DATA_DD td 0.127 2.724 f cmos2_data_ibuf[5]/opit_1/OUT
- net (fanout=1) 9.489 12.213 nt_cmos2_data[5]
- CLMA_134_40/M0 f u_ov5640/cmos2_d_d0[5]/opit_0/D
+ AB5 0.000 1.000 f cmos2_href (port)
+ net (fanout=1) 0.093 1.093 cmos2_href
+ IOBS_TB_32_0/DIN td 1.367 2.460 f cmos2_href_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.460 cmos2_href_ibuf/ntD
+ IOL_35_5/RX_DATA_DD td 0.127 2.587 f cmos2_href_ibuf/opit_1/OUT
+ net (fanout=1) 0.780 3.367 nt_cmos2_href
+ CLMA_18_12/Y6AB td 0.132 3.499 f CLKROUTE_2/Z
+ net (fanout=1) 4.461 7.960 ntR3942
+ CLMA_18_80/Y6CD td 0.134 8.094 f CLKROUTE_1/Z
+ net (fanout=1) 4.777 12.871 ntR3941
+ CLMS_78_21/CD f u_ov5640/cmos2_href_d0/opit_0/D
- Data arrival time 12.213 Logic Levels: 2
- Logic: 1.640ns(14.626%), Route: 9.573ns(85.374%)
+ Data arrival time 12.871 Logic Levels: 4
+ Logic: 1.760ns(14.826%), Route: 10.111ns(85.174%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 11.900 11.900 r
@@ -731,34 +746,34 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 1.047 13.018 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 13.018 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.082 13.100 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 2.820 15.920 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 15.920 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 17.451 ntclkbufg_6
- CLMA_134_40/CLK r u_ov5640/cmos2_d_d0[5]/opit_0/CLK
- clock pessimism 0.000 17.451
- clock uncertainty -0.250 17.201
+ net (fanout=1) 2.817 15.917 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 15.917 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 1.578 17.495 ntclkbufg_7
+ CLMS_78_21/CLK r u_ov5640/cmos2_href_d0/opit_0/CLK
+ clock pessimism 0.000 17.495
+ clock uncertainty -0.250 17.245
- Setup time -0.088 17.113
+ Setup time 0.029 17.274
- Data required time 17.113
+ Data required time 17.274
----------------------------------------------------------------------------------------------------
- Data required time 17.113
- Data arrival time 12.213
+ Data required time 17.274
+ Data arrival time 12.871
----------------------------------------------------------------------------------------------------
- Slack (MET) 4.900
+ Slack (MET) 4.403
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK
-Endpoint : u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CE
+Startpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK
+Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L3
Path Group : cmos2_pclk
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.202
- Launch Clock Delay : 5.551
- Clock Pessimism Removal : -0.615
+Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 6.200
+ Launch Clock Delay : 5.548
+ Clock Pessimism Removal : -0.652
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -769,17 +784,17 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 1.047 1.118 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 1.118 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.082 1.200 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 2.820 4.020 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 4.020 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 5.551 ntclkbufg_6
- CLMS_150_41/CLK r u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK
+ net (fanout=1) 2.817 4.017 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 4.017 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 1.531 5.548 ntclkbufg_7
+ CLMA_138_41/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK
- CLMS_150_41/Q0 tco 0.222 5.773 f u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/Q
- net (fanout=5) 0.209 5.982 u_ov5640/cmos2_href_16bit
- CLMA_154_37/CE f u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CE
+ CLMA_138_41/Y2 tco 0.284 5.832 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/Q
+ net (fanout=3) 0.085 5.917 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2 [10]
+ CLMA_138_41/A3 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L3
- Data arrival time 5.982 Logic Levels: 0
- Logic: 0.222ns(51.508%), Route: 0.209ns(48.492%)
+ Data arrival time 5.917 Logic Levels: 0
+ Logic: 0.284ns(76.965%), Route: 0.085ns(23.035%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 0.000 0.000 r
@@ -788,34 +803,34 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 1.254 1.325 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 1.325 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.126 1.451 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 3.166 4.617 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 4.617 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 1.585 6.202 ntclkbufg_6
- CLMA_154_37/CLK r u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CLK
- clock pessimism -0.615 5.587
- clock uncertainty 0.200 5.787
+ net (fanout=1) 3.164 4.615 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 4.615 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 1.585 6.200 ntclkbufg_7
+ CLMA_138_41/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
+ clock pessimism -0.652 5.548
+ clock uncertainty 0.200 5.748
- Hold time -0.220 5.567
+ Hold time -0.238 5.510
- Data required time 5.567
+ Data required time 5.510
----------------------------------------------------------------------------------------------------
- Data required time 5.567
- Data arrival time 5.982
+ Data required time 5.510
+ Data arrival time 5.917
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.415
+ Slack (MET) 0.407
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK
-Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/L2
+Startpoint : u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK
+Endpoint : u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CE
Path Group : cmos2_pclk
Path Type : min (slow corner)
Path Class : sequential timing path
Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.202
- Launch Clock Delay : 5.551
- Clock Pessimism Removal : -0.622
+ Capture Clock Delay : 6.200
+ Launch Clock Delay : 5.548
+ Clock Pessimism Removal : -0.623
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -826,17 +841,17 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 1.047 1.118 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 1.118 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.082 1.200 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 2.820 4.020 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 4.020 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 5.551 ntclkbufg_6
- CLMA_150_52/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK
+ net (fanout=1) 2.817 4.017 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 4.017 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 1.531 5.548 ntclkbufg_7
+ CLMA_90_20/CLK r u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK
- CLMA_150_52/Q3 tco 0.221 5.772 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Q1
- net (fanout=5) 0.192 5.964 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/wr_addr [7]
- CLMS_150_53/C2 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/L2
+ CLMA_90_20/Q2 tco 0.224 5.772 f u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/Q
+ net (fanout=5) 0.210 5.982 u_ov5640/cmos2_href_16bit
+ CLMA_90_24/CE f u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CE
- Data arrival time 5.964 Logic Levels: 0
- Logic: 0.221ns(53.511%), Route: 0.192ns(46.489%)
+ Data arrival time 5.982 Logic Levels: 0
+ Logic: 0.224ns(51.613%), Route: 0.210ns(48.387%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 0.000 0.000 r
@@ -845,34 +860,34 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 1.254 1.325 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 1.325 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.126 1.451 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 3.166 4.617 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 4.617 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 1.585 6.202 ntclkbufg_6
- CLMS_150_53/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK
- clock pessimism -0.622 5.580
- clock uncertainty 0.200 5.780
+ net (fanout=1) 3.164 4.615 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 4.615 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 1.585 6.200 ntclkbufg_7
+ CLMA_90_24/CLK r u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CLK
+ clock pessimism -0.623 5.577
+ clock uncertainty 0.200 5.777
- Hold time -0.235 5.545
+ Hold time -0.220 5.557
- Data required time 5.545
+ Data required time 5.557
----------------------------------------------------------------------------------------------------
- Data required time 5.545
- Data arrival time 5.964
+ Data required time 5.557
+ Data arrival time 5.982
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.419
+ Slack (MET) 0.425
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK
-Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/L2
+Startpoint : u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK
+Endpoint : u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CE
Path Group : cmos2_pclk
Path Type : min (slow corner)
Path Class : sequential timing path
Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.202
- Launch Clock Delay : 5.551
- Clock Pessimism Removal : -0.622
+ Capture Clock Delay : 6.200
+ Launch Clock Delay : 5.548
+ Clock Pessimism Removal : -0.623
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -883,17 +898,17 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 1.047 1.118 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 1.118 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.082 1.200 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 2.820 4.020 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 4.020 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 1.531 5.551 ntclkbufg_6
- CLMA_150_48/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK
+ net (fanout=1) 2.817 4.017 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 4.017 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 1.531 5.548 ntclkbufg_7
+ CLMA_90_20/CLK r u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK
- CLMA_150_48/Q1 tco 0.224 5.775 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q1
- net (fanout=5) 0.194 5.969 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/wr_addr [1]
- CLMS_150_49/A2 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/L2
+ CLMA_90_20/Q2 tco 0.224 5.772 f u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/Q
+ net (fanout=5) 0.210 5.982 u_ov5640/cmos2_href_16bit
+ CLMA_90_24/CE f u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CE
- Data arrival time 5.969 Logic Levels: 0
- Logic: 0.224ns(53.589%), Route: 0.194ns(46.411%)
+ Data arrival time 5.982 Logic Levels: 0
+ Logic: 0.224ns(51.613%), Route: 0.210ns(48.387%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 0.000 0.000 r
@@ -902,21 +917,21 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 1.254 1.325 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 1.325 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.126 1.451 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 3.166 4.617 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 4.617 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 1.585 6.202 ntclkbufg_6
- CLMS_150_49/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK
- clock pessimism -0.622 5.580
- clock uncertainty 0.200 5.780
+ net (fanout=1) 3.164 4.615 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 4.615 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 1.585 6.200 ntclkbufg_7
+ CLMA_90_24/CLK r u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CLK
+ clock pessimism -0.623 5.577
+ clock uncertainty 0.200 5.777
- Hold time -0.235 5.545
+ Hold time -0.220 5.557
- Data required time 5.545
+ Data required time 5.557
----------------------------------------------------------------------------------------------------
- Data required time 5.545
- Data arrival time 5.969
+ Data required time 5.557
+ Data arrival time 5.982
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.424
+ Slack (MET) 0.425
====================================================================================================
====================================================================================================
@@ -941,28 +956,28 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.530 4.850 _N37
- USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.585 6.435 ntclkbufg_4
- CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
-
- CLMA_146_68/Q0 tco 0.287 6.722 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
- net (fanout=4) 1.542 8.264 wr1_data_in_valid
- td 0.288 8.552 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 8.552 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001
- CLMA_70_96/Y3 td 0.501 9.053 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Y1
- net (fanout=3) 0.417 9.470 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [3]
- CLMA_66_88/Y2 td 0.487 9.957 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm/Z
- net (fanout=1) 0.455 10.412 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wwptr [3]
- td 0.474 10.886 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_0/gateop_A2/Cout
- net (fanout=1) 0.000 10.886 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [2]
- CLMA_66_100/COUT td 0.058 10.944 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 10.944 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6]
- CLMA_66_104/Y1 td 0.498 11.442 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1
- net (fanout=1) 0.120 11.562 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158
- CLMA_66_104/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4
-
- Data arrival time 11.562 Logic Levels: 4
- Logic: 2.593ns(50.575%), Route: 2.534ns(49.425%)
+ USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.585 6.435 ntclkbufg_5
+ CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
+
+ CLMA_110_85/Q0 tco 0.289 6.724 r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
+ net (fanout=4) 0.769 7.493 wr1_data_in_valid
+ td 0.288 7.781 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 7.781 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959
+ CLMA_90_101/COUT td 0.058 7.839 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 7.839 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961
+ CLMA_90_105/Y1 td 0.498 8.337 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Y1
+ net (fanout=3) 0.658 8.995 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [5]
+ CLMS_74_105/Y3 td 0.210 9.205 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[5]_1/gateop_perm/Z
+ net (fanout=1) 0.517 9.722 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N109251
+ CLMA_90_100/COUT td 0.511 10.233 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout
+ net (fanout=1) 0.000 10.233 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6]
+ CLMA_90_104/Y1 td 0.498 10.731 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1
+ net (fanout=1) 0.122 10.853 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158
+ CLMA_90_104/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4
+
+ Data arrival time 10.853 Logic Levels: 5
+ Logic: 2.352ns(53.237%), Route: 2.066ns(46.763%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 6.666 6.666 r
@@ -972,9 +987,9 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 8.552 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.048 8.600 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.486 11.086 _N37
- USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.531 12.617 ntclkbufg_4
- CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.531 12.617 ntclkbufg_5
+ CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
clock pessimism 0.448 13.065
clock uncertainty -0.250 12.815
@@ -983,15 +998,15 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
Data required time 12.692
----------------------------------------------------------------------------------------------------
Data required time 12.692
- Data arrival time 11.562
+ Data arrival time 10.853
----------------------------------------------------------------------------------------------------
- Slack (MET) 1.130
+ Slack (MET) 1.839
====================================================================================================
====================================================================================================
Startpoint : u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0
+Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2
Path Group : hdmi_in_clk
Path Type : max (slow corner)
Path Class : sequential timing path
@@ -1010,28 +1025,24 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.530 4.850 _N37
- USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.585 6.435 ntclkbufg_4
- CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
-
- CLMA_146_68/Q0 tco 0.287 6.722 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
- net (fanout=4) 1.542 8.264 wr1_data_in_valid
- td 0.288 8.552 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 8.552 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001
- CLMA_70_96/COUT td 0.058 8.610 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 8.610 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003
- td 0.058 8.668 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 8.668 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005
- CLMA_70_100/COUT td 0.058 8.726 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 8.726 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007
- td 0.058 8.784 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 8.784 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009
- CLMA_70_104/Y3 td 0.501 9.285 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1
- net (fanout=3) 0.413 9.698 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11]
- CLMA_66_104/C0 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0
-
- Data arrival time 9.698 Logic Levels: 3
- Logic: 1.308ns(40.086%), Route: 1.955ns(59.914%)
+ USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.585 6.435 ntclkbufg_5
+ CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
+
+ CLMA_110_85/Q0 tco 0.289 6.724 r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
+ net (fanout=4) 0.769 7.493 wr1_data_in_valid
+ td 0.288 7.781 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 7.781 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959
+ CLMA_90_101/COUT td 0.058 7.839 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 7.839 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961
+ td 0.058 7.897 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 7.897 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963
+ CLMA_90_105/Y2 td 0.271 8.168 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Y0
+ net (fanout=3) 0.734 8.902 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [6]
+ CLMA_90_104/D2 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2
+
+ Data arrival time 8.902 Logic Levels: 2
+ Logic: 0.964ns(39.076%), Route: 1.503ns(60.924%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 6.666 6.666 r
@@ -1041,26 +1052,26 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 8.552 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.048 8.600 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.486 11.086 _N37
- USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.531 12.617 ntclkbufg_4
- CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.531 12.617 ntclkbufg_5
+ CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK
clock pessimism 0.448 13.065
clock uncertainty -0.250 12.815
- Setup time -0.196 12.619
+ Setup time -0.368 12.447
- Data required time 12.619
+ Data required time 12.447
----------------------------------------------------------------------------------------------------
- Data required time 12.619
- Data arrival time 9.698
+ Data required time 12.447
+ Data arrival time 8.902
----------------------------------------------------------------------------------------------------
- Slack (MET) 2.921
+ Slack (MET) 3.545
====================================================================================================
====================================================================================================
Startpoint : u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4
+Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1
Path Group : hdmi_in_clk
Path Type : max (slow corner)
Path Class : sequential timing path
@@ -1079,28 +1090,28 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.530 4.850 _N37
- USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.585 6.435 ntclkbufg_4
- CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
-
- CLMA_146_68/Q0 tco 0.287 6.722 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
- net (fanout=4) 1.542 8.264 wr1_data_in_valid
- td 0.288 8.552 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 8.552 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001
- CLMA_70_96/COUT td 0.058 8.610 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 8.610 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003
- td 0.058 8.668 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 8.668 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005
- CLMA_70_100/COUT td 0.058 8.726 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 8.726 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007
- td 0.058 8.784 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 8.784 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009
- CLMA_70_104/Y3 td 0.501 9.285 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1
- net (fanout=3) 0.413 9.698 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11]
- CLMS_66_105/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4
-
- Data arrival time 9.698 Logic Levels: 3
- Logic: 1.308ns(40.086%), Route: 1.955ns(59.914%)
+ USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.585 6.435 ntclkbufg_5
+ CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
+
+ CLMA_110_85/Q0 tco 0.289 6.724 r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
+ net (fanout=4) 0.769 7.493 wr1_data_in_valid
+ td 0.288 7.781 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 7.781 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959
+ CLMA_90_101/COUT td 0.058 7.839 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 7.839 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961
+ td 0.058 7.897 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 7.897 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963
+ CLMA_90_105/COUT td 0.058 7.955 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 7.955 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15965
+ td 0.058 8.013 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 8.013 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15967
+ CLMA_90_109/Y3 td 0.501 8.514 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1
+ net (fanout=3) 0.410 8.924 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11]
+ CLMA_90_104/C1 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1
+
+ Data arrival time 8.924 Logic Levels: 3
+ Logic: 1.310ns(52.632%), Route: 1.179ns(47.368%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 6.666 6.666 r
@@ -1110,26 +1121,26 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 8.552 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.048 8.600 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.486 11.086 _N37
- USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.531 12.617 ntclkbufg_4
- CLMS_66_105/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.531 12.617 ntclkbufg_5
+ CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
clock pessimism 0.448 13.065
clock uncertainty -0.250 12.815
- Setup time -0.123 12.692
+ Setup time -0.234 12.581
- Data required time 12.692
+ Data required time 12.581
----------------------------------------------------------------------------------------------------
- Data required time 12.692
- Data arrival time 9.698
+ Data required time 12.581
+ Data arrival time 8.924
----------------------------------------------------------------------------------------------------
- Slack (MET) 2.994
+ Slack (MET) 3.657
====================================================================================================
====================================================================================================
-Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK
-Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0
+Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK
+Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0
Path Group : hdmi_in_clk
Path Type : min (slow corner)
Path Class : sequential timing path
@@ -1148,16 +1159,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.886 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.048 1.934 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.486 4.420 _N37
- USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.531 5.951 ntclkbufg_4
- CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.531 5.951 ntclkbufg_5
+ CLMA_122_92/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK
- CLMA_110_85/Q2 tco 0.224 6.175 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/Q
- net (fanout=5) 0.088 6.263 u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [2]
- CLMA_110_85/D0 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0
+ CLMA_122_92/Q2 tco 0.224 6.175 f u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/Q
+ net (fanout=3) 0.086 6.261 u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt [2]
+ CLMA_122_92/D0 f u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0
- Data arrival time 6.263 Logic Levels: 0
- Logic: 0.224ns(71.795%), Route: 0.088ns(28.205%)
+ Data arrival time 6.261 Logic Levels: 0
+ Logic: 0.224ns(72.258%), Route: 0.086ns(27.742%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 0.000 0.000 r
@@ -1167,9 +1178,9 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.530 4.850 _N37
- USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.585 6.435 ntclkbufg_4
- CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.585 6.435 ntclkbufg_5
+ CLMA_122_92/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK
clock pessimism -0.484 5.951
clock uncertainty 0.200 6.151
@@ -1178,22 +1189,22 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 6.072
----------------------------------------------------------------------------------------------------
Data required time 6.072
- Data arrival time 6.263
+ Data arrival time 6.261
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.191
+ Slack (MET) 0.189
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/L0
+Startpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK
+Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L1
Path Group : hdmi_in_clk
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 6.435
Launch Clock Delay : 5.951
- Clock Pessimism Removal : -0.484
+ Clock Pessimism Removal : -0.455
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -1205,16 +1216,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.886 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.048 1.934 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.486 4.420 _N37
- USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.531 5.951 ntclkbufg_4
- CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.531 5.951 ntclkbufg_5
+ CLMA_90_105/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK
- CLMA_66_104/Q2 tco 0.224 6.175 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/Q
- net (fanout=24) 0.100 6.275 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wfull
- CLMA_66_104/D0 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/L0
+ CLMA_90_105/Q1 tco 0.224 6.175 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Q1
+ net (fanout=6) 0.089 6.264 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/wr_addr [5]
+ CLMA_90_104/D1 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L1
- Data arrival time 6.275 Logic Levels: 0
- Logic: 0.224ns(69.136%), Route: 0.100ns(30.864%)
+ Data arrival time 6.264 Logic Levels: 0
+ Logic: 0.224ns(71.565%), Route: 0.089ns(28.435%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 0.000 0.000 r
@@ -1224,26 +1235,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.530 4.850 _N37
- USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.585 6.435 ntclkbufg_4
- CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK
- clock pessimism -0.484 5.951
- clock uncertainty 0.200 6.151
+ USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.585 6.435 ntclkbufg_5
+ CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK
+ clock pessimism -0.455 5.980
+ clock uncertainty 0.200 6.180
- Hold time -0.079 6.072
+ Hold time -0.106 6.074
- Data required time 6.072
+ Data required time 6.074
----------------------------------------------------------------------------------------------------
- Data required time 6.072
- Data arrival time 6.275
+ Data required time 6.074
+ Data arrival time 6.264
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.203
+ Slack (MET) 0.190
====================================================================================================
====================================================================================================
-Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK
-Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/L0
+Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK
+Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0
Path Group : hdmi_in_clk
Path Type : min (slow corner)
Path Class : sequential timing path
@@ -1262,16 +1273,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.886 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.048 1.934 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.486 4.420 _N37
- USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.531 5.951 ntclkbufg_4
- CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.531 5.951 ntclkbufg_5
+ CLMS_118_93/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK
- CLMA_110_85/Q0 tco 0.222 6.173 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/Q
- net (fanout=13) 0.090 6.263 u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [0]
- CLMA_110_85/A0 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/L0
+ CLMS_118_93/Q2 tco 0.224 6.175 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/Q
+ net (fanout=5) 0.089 6.264 u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [2]
+ CLMS_118_93/D0 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0
- Data arrival time 6.263 Logic Levels: 0
- Logic: 0.222ns(71.154%), Route: 0.090ns(28.846%)
+ Data arrival time 6.264 Logic Levels: 0
+ Logic: 0.224ns(71.565%), Route: 0.089ns(28.435%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 0.000 0.000 r
@@ -1281,33 +1292,33 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 2.530 4.850 _N37
- USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 1.585 6.435 ntclkbufg_4
- CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 1.585 6.435 ntclkbufg_5
+ CLMS_118_93/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK
clock pessimism -0.484 5.951
clock uncertainty 0.200 6.151
- Hold time -0.094 6.057
+ Hold time -0.079 6.072
- Data required time 6.057
+ Data required time 6.072
----------------------------------------------------------------------------------------------------
- Data required time 6.057
- Data arrival time 6.263
+ Data required time 6.072
+ Data arrival time 6.264
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.206
+ Slack (MET) 0.192
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE
+Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/D
Path Group : eth_rxc
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 8.446
- Launch Clock Delay : 10.030
- Clock Pessimism Removal : 1.548
+Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 8.567
+ Launch Clock Delay : 10.153
+ Clock Pessimism Removal : 1.557
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -1322,35 +1333,27 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.585 10.030 gmii_clk
- CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-
- CLMA_202_140/Q2 tco 0.290 10.320 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q
- net (fanout=2) 0.494 10.814 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2]
- td 0.474 11.288 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 11.288 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2]
- CLMA_214_140/COUT td 0.058 11.346 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout
- net (fanout=1) 0.000 11.346 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4]
- td 0.058 11.404 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout
- net (fanout=1) 0.000 11.404 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6]
- CLMA_214_144/COUT td 0.058 11.462 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout
- net (fanout=1) 0.000 11.462 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8]
- td 0.058 11.520 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout
- net (fanout=1) 0.000 11.520 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10]
- CLMA_214_148/COUT td 0.058 11.578 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout
- net (fanout=1) 0.000 11.578 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12]
- CLMA_214_152/Y0 td 0.269 11.847 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0
- net (fanout=1) 0.713 12.560 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13]
- CLMA_210_141/Y3 td 0.612 13.172 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1
- net (fanout=18) 0.777 13.949 _N79
- CLMS_186_153/Y2 td 0.487 14.436 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z
- net (fanout=1) 0.502 14.938 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323
- CLMA_194_160/Y1 td 0.316 15.254 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z
- net (fanout=16) 0.796 16.050 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839
- CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE
-
- Data arrival time 16.050 Logic Levels: 7
- Logic: 2.738ns(45.482%), Route: 3.282ns(54.518%)
+ net (fanout=1862) 1.708 10.153 gmii_clk
+ CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+
+ CLMA_194_261/Q0 tco 0.289 10.442 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q
+ net (fanout=2) 0.817 11.259 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0]
+ CLMA_182_241/Y1 td 0.288 11.547 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z
+ net (fanout=1) 0.698 12.245 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159
+ CLMA_190_252/Y3 td 0.210 12.455 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z
+ net (fanout=1) 0.559 13.014 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179
+ CLMA_190_240/Y2 td 0.210 13.224 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z
+ net (fanout=2) 0.934 14.158 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446
+ CLMA_210_265/Y3 td 0.210 14.368 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z
+ net (fanout=6) 0.490 14.858 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187
+ CLMA_198_264/Y3 td 0.210 15.068 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z
+ net (fanout=187) 0.763 15.831 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319
+ CLMA_194_264/Y0 td 0.196 16.027 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[4]/opit_0_L5Q/Z
+ net (fanout=3) 0.733 16.760 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N642 [4]
+ CLMA_194_257/M1 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/D
+
+ Data arrival time 16.760 Logic Levels: 6
+ Logic: 1.613ns(24.414%), Route: 4.994ns(75.586%)
----------------------------------------------------------------------------------------------------
Clock eth_rxc (rising edge) 8.000 8.000 r
@@ -1363,32 +1366,32 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 2.574 12.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.553 14.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 14.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.531 16.446 gmii_clk
- CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CLK
- clock pessimism 1.548 17.994
- clock uncertainty -0.250 17.744
+ net (fanout=1862) 1.652 16.567 gmii_clk
+ CLMA_194_257/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/CLK
+ clock pessimism 1.557 18.124
+ clock uncertainty -0.250 17.874
- Setup time -0.617 17.127
+ Setup time -0.088 17.786
- Data required time 17.127
+ Data required time 17.786
----------------------------------------------------------------------------------------------------
- Data required time 17.127
- Data arrival time 16.050
+ Data required time 17.786
+ Data arrival time 16.760
----------------------------------------------------------------------------------------------------
- Slack (MET) 1.077
+ Slack (MET) 1.026
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE
+Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE
Path Group : eth_rxc
Path Type : max (slow corner)
Path Class : sequential timing path
Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 8.446
- Launch Clock Delay : 10.030
- Clock Pessimism Removal : 1.548
+ Capture Clock Delay : 8.567
+ Launch Clock Delay : 10.153
+ Clock Pessimism Removal : 1.550
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -1403,35 +1406,29 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.585 10.030 gmii_clk
- CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-
- CLMA_202_140/Q2 tco 0.290 10.320 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q
- net (fanout=2) 0.494 10.814 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2]
- td 0.474 11.288 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 11.288 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2]
- CLMA_214_140/COUT td 0.058 11.346 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout
- net (fanout=1) 0.000 11.346 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4]
- td 0.058 11.404 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout
- net (fanout=1) 0.000 11.404 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6]
- CLMA_214_144/COUT td 0.058 11.462 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout
- net (fanout=1) 0.000 11.462 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8]
- td 0.058 11.520 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout
- net (fanout=1) 0.000 11.520 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10]
- CLMA_214_148/COUT td 0.058 11.578 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout
- net (fanout=1) 0.000 11.578 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12]
- CLMA_214_152/Y0 td 0.269 11.847 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0
- net (fanout=1) 0.713 12.560 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13]
- CLMA_210_141/Y3 td 0.612 13.172 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1
- net (fanout=18) 0.777 13.949 _N79
- CLMS_186_153/Y2 td 0.487 14.436 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z
- net (fanout=1) 0.502 14.938 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323
- CLMA_194_160/Y1 td 0.316 15.254 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z
- net (fanout=16) 0.796 16.050 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839
- CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE
-
- Data arrival time 16.050 Logic Levels: 7
- Logic: 2.738ns(45.482%), Route: 3.282ns(54.518%)
+ net (fanout=1862) 1.708 10.153 gmii_clk
+ CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+
+ CLMA_194_261/Q0 tco 0.289 10.442 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q
+ net (fanout=2) 0.817 11.259 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0]
+ CLMA_182_241/Y1 td 0.288 11.547 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z
+ net (fanout=1) 0.698 12.245 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159
+ CLMA_190_252/Y3 td 0.210 12.455 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z
+ net (fanout=1) 0.559 13.014 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179
+ CLMA_190_240/Y2 td 0.210 13.224 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z
+ net (fanout=2) 0.934 14.158 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446
+ CLMA_210_265/Y3 td 0.210 14.368 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z
+ net (fanout=6) 0.490 14.858 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187
+ CLMA_198_264/Y3 td 0.210 15.068 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z
+ net (fanout=187) 0.672 15.740 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319
+ CLMA_202_272/CECO td 0.184 15.924 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT
+ net (fanout=1) 0.000 15.924 ntR2081
+ CLMA_202_276/CECO td 0.184 16.108 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT
+ net (fanout=6) 0.000 16.108 ntR2080
+ CLMA_202_280/CECI r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE
+
+ Data arrival time 16.108 Logic Levels: 7
+ Logic: 1.785ns(29.975%), Route: 4.170ns(70.025%)
----------------------------------------------------------------------------------------------------
Clock eth_rxc (rising edge) 8.000 8.000 r
@@ -1444,32 +1441,32 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 2.574 12.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.553 14.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 14.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.531 16.446 gmii_clk
- CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CLK
- clock pessimism 1.548 17.994
- clock uncertainty -0.250 17.744
+ net (fanout=1862) 1.652 16.567 gmii_clk
+ CLMA_202_280/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CLK
+ clock pessimism 1.550 18.117
+ clock uncertainty -0.250 17.867
- Setup time -0.617 17.127
+ Setup time -0.729 17.138
- Data required time 17.127
+ Data required time 17.138
----------------------------------------------------------------------------------------------------
- Data required time 17.127
- Data arrival time 16.050
+ Data required time 17.138
+ Data arrival time 16.108
----------------------------------------------------------------------------------------------------
- Slack (MET) 1.077
+ Slack (MET) 1.030
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE
+Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE
Path Group : eth_rxc
Path Type : max (slow corner)
Path Class : sequential timing path
Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 8.446
- Launch Clock Delay : 10.030
- Clock Pessimism Removal : 1.548
+ Capture Clock Delay : 8.567
+ Launch Clock Delay : 10.153
+ Clock Pessimism Removal : 1.550
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -1484,35 +1481,29 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.585 10.030 gmii_clk
- CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-
- CLMA_202_140/Q2 tco 0.290 10.320 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q
- net (fanout=2) 0.494 10.814 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2]
- td 0.474 11.288 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 11.288 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2]
- CLMA_214_140/COUT td 0.058 11.346 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout
- net (fanout=1) 0.000 11.346 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4]
- td 0.058 11.404 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout
- net (fanout=1) 0.000 11.404 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6]
- CLMA_214_144/COUT td 0.058 11.462 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout
- net (fanout=1) 0.000 11.462 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8]
- td 0.058 11.520 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout
- net (fanout=1) 0.000 11.520 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10]
- CLMA_214_148/COUT td 0.058 11.578 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout
- net (fanout=1) 0.000 11.578 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12]
- CLMA_214_152/Y0 td 0.269 11.847 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0
- net (fanout=1) 0.713 12.560 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13]
- CLMA_210_141/Y3 td 0.612 13.172 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1
- net (fanout=18) 0.777 13.949 _N79
- CLMS_186_153/Y2 td 0.487 14.436 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z
- net (fanout=1) 0.502 14.938 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323
- CLMA_194_160/Y1 td 0.316 15.254 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z
- net (fanout=16) 0.796 16.050 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839
- CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE
-
- Data arrival time 16.050 Logic Levels: 7
- Logic: 2.738ns(45.482%), Route: 3.282ns(54.518%)
+ net (fanout=1862) 1.708 10.153 gmii_clk
+ CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+
+ CLMA_194_261/Q0 tco 0.289 10.442 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q
+ net (fanout=2) 0.817 11.259 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0]
+ CLMA_182_241/Y1 td 0.288 11.547 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z
+ net (fanout=1) 0.698 12.245 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159
+ CLMA_190_252/Y3 td 0.210 12.455 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z
+ net (fanout=1) 0.559 13.014 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179
+ CLMA_190_240/Y2 td 0.210 13.224 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z
+ net (fanout=2) 0.934 14.158 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446
+ CLMA_210_265/Y3 td 0.210 14.368 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z
+ net (fanout=6) 0.490 14.858 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187
+ CLMA_198_264/Y3 td 0.210 15.068 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z
+ net (fanout=187) 0.672 15.740 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319
+ CLMA_202_272/CECO td 0.184 15.924 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT
+ net (fanout=1) 0.000 15.924 ntR2081
+ CLMA_202_276/CECO td 0.184 16.108 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT
+ net (fanout=6) 0.000 16.108 ntR2080
+ CLMA_202_280/CECI r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE
+
+ Data arrival time 16.108 Logic Levels: 7
+ Logic: 1.785ns(29.975%), Route: 4.170ns(70.025%)
----------------------------------------------------------------------------------------------------
Clock eth_rxc (rising edge) 8.000 8.000 r
@@ -1525,32 +1516,32 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 2.574 12.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.553 14.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 14.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.531 16.446 gmii_clk
- CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CLK
- clock pessimism 1.548 17.994
- clock uncertainty -0.250 17.744
+ net (fanout=1862) 1.652 16.567 gmii_clk
+ CLMA_202_280/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CLK
+ clock pessimism 1.550 18.117
+ clock uncertainty -0.250 17.867
- Setup time -0.617 17.127
+ Setup time -0.729 17.138
- Data required time 17.127
+ Data required time 17.138
----------------------------------------------------------------------------------------------------
- Data required time 17.127
- Data arrival time 16.050
+ Data required time 17.138
+ Data arrival time 16.108
----------------------------------------------------------------------------------------------------
- Slack (MET) 1.077
+ Slack (MET) 1.030
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK
-Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/A3
+Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D
Path Group : eth_rxc
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 10.030
- Launch Clock Delay : 8.446
- Clock Pessimism Removal : -1.584
+Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 10.153
+ Launch Clock Delay : 8.567
+ Clock Pessimism Removal : -1.550
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -1565,15 +1556,15 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOCKDLY_237_367/CLK_OUT td 2.574 4.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.553 6.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 6.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.531 8.446 gmii_clk
- CLMS_162_225/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK
+ net (fanout=1862) 1.652 8.567 gmii_clk
+ CLMA_194_288/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK
- CLMS_162_225/Q2 tco 0.224 8.670 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/Q
- net (fanout=5) 0.088 8.758 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg [3]
- CLMS_162_225/A3 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/A3
+ CLMA_194_288/Q0 tco 0.222 8.789 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/Q
+ net (fanout=3) 0.224 9.013 udp_osd_inst/eth_udp_inst/des_ip [30]
+ CLMA_198_288/AD f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D
- Data arrival time 8.758 Logic Levels: 0
- Logic: 0.224ns(71.795%), Route: 0.088ns(28.205%)
+ Data arrival time 9.013 Logic Levels: 0
+ Logic: 0.222ns(49.776%), Route: 0.224ns(50.224%)
----------------------------------------------------------------------------------------------------
Clock eth_rxc (rising edge) 0.000 0.000 r
@@ -1586,25 +1577,25 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.585 10.030 gmii_clk
- CLMS_162_225/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/CLK
- clock pessimism -1.584 8.446
- clock uncertainty 0.200 8.646
+ net (fanout=1862) 1.708 10.153 gmii_clk
+ CLMA_198_288/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/CLK
+ clock pessimism -1.550 8.603
+ clock uncertainty 0.200 8.803
- Hold time -0.269 8.377
+ Hold time 0.053 8.856
- Data required time 8.377
+ Data required time 8.856
----------------------------------------------------------------------------------------------------
- Data required time 8.377
- Data arrival time 8.758
+ Data required time 8.856
+ Data arrival time 9.013
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.381
+ Slack (MET) 0.157
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/CLK
-Endpoint : udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/Cin
+Startpoint : param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/CLK
+Endpoint : param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/Cin
Path Group : eth_rxc
Path Type : min (slow corner)
Path Class : sequential timing path
@@ -1626,17 +1617,17 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOCKDLY_237_367/CLK_OUT td 2.574 4.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.553 6.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 6.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.531 8.446 gmii_clk
- CLMS_186_213/CLK r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/CLK
+ net (fanout=1862) 1.531 8.446 gmii_clk
+ CLMA_250_212/CLK r param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/CLK
- CLMS_186_213/Q3 tco 0.221 8.667 f udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/Q
- net (fanout=2) 0.187 8.854 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length [12]
- td 0.136 8.990 f udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[12]/opit_0_A2Q21/Cout
- net (fanout=1) 0.000 8.990 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N168_1.co [10]
- f udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/Cin
+ CLMA_250_212/Q3 tco 0.221 8.667 f param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/Q
+ net (fanout=3) 0.188 8.855 param_manager_inst/param_offsetX/cnt [3]
+ CLMA_250_213/COUT td 0.118 8.973 r param_manager_inst/param_offsetX/N26_1.fsub_3/gateop_A2/Cout
+ net (fanout=1) 0.000 8.973 param_manager_inst/param_offsetX/N26_1.co [4]
+ CLMA_250_217/CIN r param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/Cin
- Data arrival time 8.990 Logic Levels: 0
- Logic: 0.357ns(65.625%), Route: 0.187ns(34.375%)
+ Data arrival time 8.973 Logic Levels: 1
+ Logic: 0.339ns(64.326%), Route: 0.188ns(35.674%)
----------------------------------------------------------------------------------------------------
Clock eth_rxc (rising edge) 0.000 0.000 r
@@ -1649,32 +1640,32 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.585 10.030 gmii_clk
- CLMA_186_212/CLK r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/CLK
+ net (fanout=1862) 1.585 10.030 gmii_clk
+ CLMA_250_217/CLK r param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/CLK
clock pessimism -1.555 8.475
clock uncertainty 0.200 8.675
- Hold time -0.071 8.604
+ Hold time -0.085 8.590
- Data required time 8.604
+ Data required time 8.590
----------------------------------------------------------------------------------------------------
- Data required time 8.604
- Data arrival time 8.990
+ Data required time 8.590
+ Data arrival time 8.973
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.386
+ Slack (MET) 0.383
====================================================================================================
====================================================================================================
-Startpoint : param_manager_inst/modify_H_flags_ff1/opit_0/CLK
-Endpoint : param_manager_inst/modify_H_load/opit_0_L5Q_perm/L2
+Startpoint : udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/CLK
+Endpoint : udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/Cin
Path Group : eth_rxc
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 10.030
Launch Clock Delay : 8.446
- Clock Pessimism Removal : -1.584
+ Clock Pessimism Removal : -1.555
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -1689,15 +1680,17 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOCKDLY_237_367/CLK_OUT td 2.574 4.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.553 6.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 6.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.531 8.446 gmii_clk
- CLMS_214_137/CLK r param_manager_inst/modify_H_flags_ff1/opit_0/CLK
+ net (fanout=1862) 1.531 8.446 gmii_clk
+ CLMA_198_224/CLK r udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/CLK
- CLMS_214_137/Y2 tco 0.284 8.730 f param_manager_inst/modify_H_flags_ff1/opit_0/Q
- net (fanout=1) 0.086 8.816 param_manager_inst/modify_H_flags_ff1
- CLMS_214_137/B2 f param_manager_inst/modify_H_load/opit_0_L5Q_perm/L2
+ CLMA_198_224/Q0 tco 0.222 8.668 f udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/Q
+ net (fanout=3) 0.086 8.754 udp_wr_mem_inst/data_count [1]
+ td 0.236 8.990 r udp_wr_mem_inst/N30_1.fsub_1/gateop_A2/Cout
+ net (fanout=1) 0.000 8.990 udp_wr_mem_inst/N30_1.co [2]
+ r udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/Cin
- Data arrival time 8.816 Logic Levels: 0
- Logic: 0.284ns(76.757%), Route: 0.086ns(23.243%)
+ Data arrival time 8.990 Logic Levels: 0
+ Logic: 0.458ns(84.191%), Route: 0.086ns(15.809%)
----------------------------------------------------------------------------------------------------
Clock eth_rxc (rising edge) 0.000 0.000 r
@@ -1710,19 +1703,19 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.585 10.030 gmii_clk
- CLMS_214_137/CLK r param_manager_inst/modify_H_load/opit_0_L5Q_perm/CLK
- clock pessimism -1.584 8.446
- clock uncertainty 0.200 8.646
+ net (fanout=1862) 1.585 10.030 gmii_clk
+ CLMS_198_225/CLK r udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/CLK
+ clock pessimism -1.555 8.475
+ clock uncertainty 0.200 8.675
- Hold time -0.221 8.425
+ Hold time -0.082 8.593
- Data required time 8.425
+ Data required time 8.593
----------------------------------------------------------------------------------------------------
- Data required time 8.425
- Data arrival time 8.816
+ Data required time 8.593
+ Data arrival time 8.990
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.391
+ Slack (MET) 0.397
====================================================================================================
====================================================================================================
@@ -1732,9 +1725,9 @@ Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctr
Path Group : clk_50m
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.378
- Launch Clock Delay : 5.930
+Clock Skew : -0.058 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.392
+ Launch Clock Delay : 5.909
Clock Pessimism Removal : 0.459
Location Delay Type Incr Path Logical Resource
@@ -1750,29 +1743,29 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.642 5.930 ntclkbufg_1
- DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
-
- DRM_82_4/QB0[0] tco 2.307 8.237 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0]
- net (fanout=6) 1.382 9.619 u_rotate_image/dout [0]
- CLMS_74_73/Y1 td 0.197 9.816 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z
- net (fanout=3) 1.147 10.963 u_rotate_image/addr_fifo_rd_en
- td 0.288 11.251 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 11.251 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637
- CLMS_78_9/Y3 td 0.501 11.752 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1
- net (fanout=1) 0.401 12.153 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [3]
- CLMS_74_13/Y3 td 0.210 12.363 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z
- net (fanout=3) 0.766 13.129 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [3]
- td 0.477 13.606 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2/Cout
- net (fanout=1) 0.000 13.606 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [2]
- CLMA_90_20/COUT td 0.058 13.664 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 13.664 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6]
- CLMA_90_24/Y1 td 0.498 14.162 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1
- net (fanout=1) 0.547 14.709 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21
- CLMA_94_16/C4 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
-
- Data arrival time 14.709 Logic Levels: 5
- Logic: 4.536ns(51.669%), Route: 4.243ns(48.331%)
+ net (fanout=2516) 1.621 5.909 ntclkbufg_1
+ DRM_54_24/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
+
+ DRM_54_24/QB0[0] tco 2.307 8.216 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0]
+ net (fanout=6) 1.422 9.638 u_rotate_image/dout [0]
+ CLMS_74_117/Y1 td 0.466 10.104 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z
+ net (fanout=3) 1.540 11.644 u_rotate_image/addr_fifo_rd_en
+ td 0.288 11.932 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 11.932 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576
+ CLMS_50_33/COUT td 0.058 11.990 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 11.990 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578
+ CLMS_50_37/Y1 td 0.498 12.488 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1
+ net (fanout=1) 0.527 13.015 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5]
+ CLMA_58_29/Y1 td 0.468 13.483 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z
+ net (fanout=3) 0.612 14.095 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5]
+ CLMA_58_36/COUT td 0.511 14.606 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout
+ net (fanout=1) 0.000 14.606 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6]
+ CLMA_58_40/Y1 td 0.498 15.104 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1
+ net (fanout=1) 0.120 15.224 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21
+ CLMA_58_40/C4 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
+
+ Data arrival time 15.224 Logic Levels: 6
+ Logic: 5.094ns(54.686%), Route: 4.221ns(45.314%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 20.000 20.000 r
@@ -1785,31 +1778,31 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 23.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.531 25.378 ntclkbufg_1
- CLMA_94_16/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK
- clock pessimism 0.459 25.837
- clock uncertainty -0.150 25.687
+ net (fanout=2516) 1.545 25.392 ntclkbufg_1
+ CLMA_58_40/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK
+ clock pessimism 0.459 25.851
+ clock uncertainty -0.150 25.701
- Setup time -0.123 25.564
+ Setup time -0.123 25.578
- Data required time 25.564
+ Data required time 25.578
----------------------------------------------------------------------------------------------------
- Data required time 25.564
- Data arrival time 14.709
+ Data required time 25.578
+ Data arrival time 15.224
----------------------------------------------------------------------------------------------------
- Slack (MET) 10.855
+ Slack (MET) 10.354
====================================================================================================
====================================================================================================
Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
-Endpoint : u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
Path Group : clk_50m
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.378
- Launch Clock Delay : 5.930
+Clock Skew : -0.061 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.389
+ Launch Clock Delay : 5.909
Clock Pessimism Removal : 0.459
Location Delay Type Incr Path Logical Resource
@@ -1825,29 +1818,27 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.642 5.930 ntclkbufg_1
- DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
-
- DRM_82_4/QB0[0] tco 2.307 8.237 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0]
- net (fanout=6) 1.130 9.367 u_rotate_image/dout [0]
- CLMS_74_73/Y3 td 0.465 9.832 f u_rotate_image/fifo_data_valid/opit_0_L5Q_perm/Z
- net (fanout=3) 0.774 10.606 u_rotate_image/N170
- td 0.288 10.894 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 10.894 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16662
- CLMA_58_92/Y3 td 0.501 11.395 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1
- net (fanout=1) 0.268 11.663 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11 [3]
- CLMA_58_89/Y3 td 0.459 12.122 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z
- net (fanout=1) 0.735 12.857 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/rrptr [3]
- td 0.477 13.334 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2/Cout
- net (fanout=1) 0.000 13.334 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [2]
- CLMS_50_93/COUT td 0.058 13.392 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 13.392 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [6]
- CLMS_50_97/Y0 td 0.159 13.551 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Y0
- net (fanout=1) 0.257 13.808 _N70
- CLMS_50_97/C4 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
-
- Data arrival time 13.808 Logic Levels: 5
- Logic: 4.714ns(59.838%), Route: 3.164ns(40.162%)
+ net (fanout=2516) 1.621 5.909 ntclkbufg_1
+ DRM_54_24/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
+
+ DRM_54_24/QB0[0] tco 2.307 8.216 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0]
+ net (fanout=6) 1.422 9.638 u_rotate_image/dout [0]
+ CLMS_74_117/Y1 td 0.466 10.104 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z
+ net (fanout=3) 1.540 11.644 u_rotate_image/addr_fifo_rd_en
+ td 0.288 11.932 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 11.932 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576
+ CLMS_50_33/COUT td 0.058 11.990 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 11.990 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578
+ CLMS_50_37/Y1 td 0.498 12.488 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1
+ net (fanout=1) 0.527 13.015 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5]
+ CLMA_58_29/Y1 td 0.468 13.483 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z
+ net (fanout=3) 0.405 13.888 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5]
+ CLMA_62_32/COUT td 0.511 14.399 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout
+ net (fanout=1) 0.000 14.399 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6]
+ CLMA_62_36/CIN r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
+
+ Data arrival time 14.399 Logic Levels: 5
+ Logic: 4.596ns(54.134%), Route: 3.894ns(45.866%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 20.000 20.000 r
@@ -1860,32 +1851,32 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 23.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.531 25.378 ntclkbufg_1
- CLMS_50_97/CLK r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK
- clock pessimism 0.459 25.837
- clock uncertainty -0.150 25.687
+ net (fanout=2516) 1.542 25.389 ntclkbufg_1
+ CLMA_62_36/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK
+ clock pessimism 0.459 25.848
+ clock uncertainty -0.150 25.698
- Setup time -0.123 25.564
+ Setup time -0.357 25.341
- Data required time 25.564
+ Data required time 25.341
----------------------------------------------------------------------------------------------------
- Data required time 25.564
- Data arrival time 13.808
+ Data required time 25.341
+ Data arrival time 14.399
----------------------------------------------------------------------------------------------------
- Slack (MET) 11.756
+ Slack (MET) 10.942
====================================================================================================
====================================================================================================
-Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
-Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
+Startpoint : image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK
+Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
Path Group : clk_50m
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.378
- Launch Clock Delay : 5.930
- Clock Pessimism Removal : 0.459
+Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.499
+ Launch Clock Delay : 5.996
+ Clock Pessimism Removal : 0.461
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -1900,29 +1891,37 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.642 5.930 ntclkbufg_1
- DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
-
- DRM_82_4/QB0[0] tco 2.307 8.237 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0]
- net (fanout=6) 1.382 9.619 u_rotate_image/dout [0]
- CLMS_74_73/Y1 td 0.197 9.816 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z
- net (fanout=3) 1.147 10.963 u_rotate_image/addr_fifo_rd_en
- td 0.288 11.251 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 11.251 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637
- CLMS_78_9/COUT td 0.058 11.309 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 11.309 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16639
- td 0.058 11.367 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 11.367 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16641
- CLMS_78_13/Y3 td 0.501 11.868 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/Y1
- net (fanout=1) 0.395 12.263 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [7]
- CLMS_74_13/Y1 td 0.212 12.475 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[7]/gateop_perm/Z
- net (fanout=3) 0.492 12.967 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [7]
- CLMA_94_12/COUT td 0.515 13.482 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 13.482 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6]
- CLMA_94_16/CIN r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
-
- Data arrival time 13.482 Logic Levels: 5
- Logic: 4.136ns(54.767%), Route: 3.416ns(45.233%)
+ net (fanout=2516) 1.708 5.996 ntclkbufg_1
+ CLMA_78_280/CLK r image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK
+
+ CLMA_78_280/Q2 tco 0.290 6.286 r image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/Q0
+ net (fanout=2) 0.417 6.703 image_filiter_inst/multiline_buffer_inst/hor_cnt [3]
+ CLMA_74_280/Y1 td 0.460 7.163 r image_filiter_inst/multiline_buffer_inst/N229_8/gateop_perm/Z
+ net (fanout=1) 0.407 7.570 image_filiter_inst/multiline_buffer_inst/_N104607
+ CLMS_78_285/Y2 td 0.286 7.856 r image_filiter_inst/multiline_buffer_inst/N229_11/gateop_perm/Z
+ net (fanout=5) 0.525 8.381 image_filiter_inst/multiline_buffer_inst/N229
+ CLMS_94_289/Y2 td 0.487 8.868 r image_filiter_inst/multiline_buffer_inst/N176_7/gateop_perm/Z
+ net (fanout=1) 0.403 9.271 image_filiter_inst/multiline_buffer_inst/N176
+ CLMA_90_284/Y2 td 0.478 9.749 r image_filiter_inst/multiline_buffer_inst/N189[1]_4/gateop_perm/Z
+ net (fanout=4) 0.839 10.588 image_filiter_inst/multiline_buffer_inst/rd_en [1]
+ td 0.234 10.822 f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 10.822 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N14178
+ CLMS_78_269/COUT td 0.058 10.880 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 10.880 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N14180
+ td 0.058 10.938 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 10.938 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N14182
+ CLMS_78_273/Y3 td 0.501 11.439 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/Y1
+ net (fanout=1) 0.519 11.958 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11 [7]
+ CLMS_94_273/Y3 td 0.465 12.423 f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm/Z
+ net (fanout=2) 0.847 13.270 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/rrptr [7]
+ CLMA_90_276/COUT td 0.515 13.785 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout
+ net (fanout=1) 0.000 13.785 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.co [6]
+ CLMA_90_280/Y1 td 0.498 14.283 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1
+ net (fanout=1) 0.447 14.730 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21
+ CLMA_90_272/C4 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
+
+ Data arrival time 14.730 Logic Levels: 9
+ Logic: 4.330ns(49.576%), Route: 4.404ns(50.424%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 20.000 20.000 r
@@ -1935,30 +1934,30 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 23.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.531 25.378 ntclkbufg_1
- CLMA_94_16/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK
- clock pessimism 0.459 25.837
- clock uncertainty -0.150 25.687
+ net (fanout=2516) 1.652 25.499 ntclkbufg_1
+ CLMA_90_272/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK
+ clock pessimism 0.461 25.960
+ clock uncertainty -0.150 25.810
- Setup time -0.357 25.330
+ Setup time -0.123 25.687
- Data required time 25.330
+ Data required time 25.687
----------------------------------------------------------------------------------------------------
- Data required time 25.330
- Data arrival time 13.482
+ Data required time 25.687
+ Data arrival time 14.730
----------------------------------------------------------------------------------------------------
- Slack (MET) 11.848
+ Slack (MET) 10.957
====================================================================================================
====================================================================================================
-Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK
-Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8]
+Startpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK
+Endpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10]
Path Group : clk_50m
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.088 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.925
+Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.873
Launch Clock Delay : 5.378
Clock Pessimism Removal : -0.459
@@ -1975,15 +1974,15 @@ Clock Skew : 0.088 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.531 5.378 ntclkbufg_1
- CLMA_90_12/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK
+ net (fanout=2516) 1.531 5.378 ntclkbufg_1
+ CLMS_50_117/CLK r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK
- CLMA_90_12/Q2 tco 0.224 5.602 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Q0
- net (fanout=3) 0.256 5.858 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [6]
- DRM_82_4/ADA0[8] f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8]
+ CLMS_50_117/Q0 tco 0.222 5.600 f u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0
+ net (fanout=5) 0.225 5.825 u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/wr_addr [8]
+ DRM_54_108/ADA0[10] f u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10]
- Data arrival time 5.858 Logic Levels: 0
- Logic: 0.224ns(46.667%), Route: 0.256ns(53.333%)
+ Data arrival time 5.825 Logic Levels: 0
+ Logic: 0.222ns(49.664%), Route: 0.225ns(50.336%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 0.000 0.000 r
@@ -1996,31 +1995,31 @@ Clock Skew : 0.088 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.637 5.925 ntclkbufg_1
- DRM_82_4/CLKA[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA
- clock pessimism -0.459 5.466
- clock uncertainty 0.000 5.466
+ net (fanout=2516) 1.585 5.873 ntclkbufg_1
+ DRM_54_108/CLKA[0] r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA
+ clock pessimism -0.459 5.414
+ clock uncertainty 0.000 5.414
- Hold time 0.210 5.676
+ Hold time 0.210 5.624
- Data required time 5.676
+ Data required time 5.624
----------------------------------------------------------------------------------------------------
- Data required time 5.676
- Data arrival time 5.858
+ Data required time 5.624
+ Data arrival time 5.825
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.182
+ Slack (MET) 0.201
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK
-Endpoint : u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D
+Startpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK
+Endpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/D
Path Group : clk_50m
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.899
- Launch Clock Delay : 5.403
+Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.873
+ Launch Clock Delay : 5.378
Clock Pessimism Removal : -0.466
Location Delay Type Incr Path Logical Resource
@@ -2036,15 +2035,15 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.556 5.403 ntclkbufg_1
- CLMA_58_88/CLK r u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK
+ net (fanout=2516) 1.531 5.378 ntclkbufg_1
+ CLMA_58_108/CLK r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK
- CLMA_58_88/Q3 tco 0.221 5.624 f u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/Q
- net (fanout=1) 0.084 5.708 u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr1 [8]
- CLMA_58_89/AD f u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D
+ CLMA_58_108/Q2 tco 0.224 5.602 f u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/Q
+ net (fanout=1) 0.084 5.686 u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr1 [2]
+ CLMA_58_109/CD f u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/D
- Data arrival time 5.708 Logic Levels: 0
- Logic: 0.221ns(72.459%), Route: 0.084ns(27.541%)
+ Data arrival time 5.686 Logic Levels: 0
+ Logic: 0.224ns(72.727%), Route: 0.084ns(27.273%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 0.000 0.000 r
@@ -2057,32 +2056,32 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.611 5.899 ntclkbufg_1
- CLMA_58_89/CLK r u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK
- clock pessimism -0.466 5.433
- clock uncertainty 0.000 5.433
+ net (fanout=2516) 1.585 5.873 ntclkbufg_1
+ CLMA_58_109/CLK r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK
+ clock pessimism -0.466 5.407
+ clock uncertainty 0.000 5.407
- Hold time 0.053 5.486
+ Hold time 0.053 5.460
- Data required time 5.486
+ Data required time 5.460
----------------------------------------------------------------------------------------------------
- Data required time 5.486
- Data arrival time 5.708
+ Data required time 5.460
+ Data arrival time 5.686
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.222
+ Slack (MET) 0.226
====================================================================================================
====================================================================================================
-Startpoint : image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK
-Endpoint : image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D
+Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2]
Path Group : clk_50m
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.873
- Launch Clock Delay : 5.378
- Clock Pessimism Removal : -0.495
+Clock Skew : 0.023 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.903
+ Launch Clock Delay : 5.421
+ Clock Pessimism Removal : -0.459
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -2097,15 +2096,15 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.531 5.378 ntclkbufg_1
- CLMA_98_148/CLK r image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK
+ net (fanout=2516) 1.574 5.421 ntclkbufg_1
+ CLMA_50_32/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK
- CLMA_98_148/Q3 tco 0.221 5.599 f image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/Q
- net (fanout=1) 0.084 5.683 image_filiter_inst2/hybrid_filter_inst/pixel_ff [27]
- CLMA_98_148/AD f image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D
+ CLMA_50_32/Q0 tco 0.222 5.643 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q0
+ net (fanout=4) 0.218 5.861 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [0]
+ DRM_54_24/ADA0[2] f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2]
- Data arrival time 5.683 Logic Levels: 0
- Logic: 0.221ns(72.459%), Route: 0.084ns(27.541%)
+ Data arrival time 5.861 Logic Levels: 0
+ Logic: 0.222ns(50.455%), Route: 0.218ns(49.545%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 0.000 0.000 r
@@ -2118,32 +2117,32 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.585 5.873 ntclkbufg_1
- CLMA_98_148/CLK r image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK
- clock pessimism -0.495 5.378
- clock uncertainty 0.000 5.378
+ net (fanout=2516) 1.615 5.903 ntclkbufg_1
+ DRM_54_24/CLKA[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA
+ clock pessimism -0.459 5.444
+ clock uncertainty 0.000 5.444
- Hold time 0.053 5.431
+ Hold time 0.186 5.630
- Data required time 5.431
+ Data required time 5.630
----------------------------------------------------------------------------------------------------
- Data required time 5.431
- Data arrival time 5.683
+ Data required time 5.630
+ Data arrival time 5.861
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.252
+ Slack (MET) 0.231
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/data_out_valid2/opit_0/CLK
-Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm/B3
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CE
Path Group : clk_200m
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 5.374
Launch Clock Delay : 5.867
- Clock Pessimism Removal : 0.439
+ Clock Pessimism Removal : 0.493
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -2156,31 +2155,27 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.585 5.867 ntR3909
- CLMA_242_124/CLK r u_zoom_image/data_out_valid2/opit_0/CLK
-
- CLMA_242_124/Q0 tco 0.289 6.156 r u_zoom_image/data_out_valid2/opit_0/Q
- net (fanout=34) 0.630 6.786 zoom_data_out_valid
- td 0.288 7.074 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 7.074 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16324
- CLMA_242_96/COUT td 0.058 7.132 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 7.132 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16326
- CLMA_242_100/Y1 td 0.475 7.607 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Y1
- net (fanout=3) 1.345 8.952 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2 [5]
- CLMA_246_176/Y2 td 0.210 9.162 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm/Z
- net (fanout=3) 0.417 9.579 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wwptr [5]
- td 0.474 10.053 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/gateop_A2/Cout
- net (fanout=1) 0.000 10.053 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6]
- CLMS_242_169/COUT td 0.058 10.111 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/gateop_A2/Cout
- net (fanout=1) 0.000 10.111 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8]
- CLMS_242_173/Y1 td 0.498 10.609 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/gateop_A2/Y1
- net (fanout=2) 0.416 11.025 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [9]
- CLMA_246_180/D3 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm/B3
-
- Data arrival time 11.025 Logic Levels: 5
- Logic: 2.350ns(45.560%), Route: 2.808ns(54.440%)
+ net (fanout=2) 1.078 4.282 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_90_197/Q1 tco 0.291 6.158 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q
+ net (fanout=2) 0.408 6.566 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15]
+ CLMS_94_197/Y0 td 0.487 7.053 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z
+ net (fanout=2) 0.123 7.176 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154
+ CLMA_94_196/Y2 td 0.478 7.654 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z
+ net (fanout=1) 0.120 7.774 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157
+ CLMA_94_196/Y3 td 0.287 8.061 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z
+ net (fanout=11) 0.438 8.499 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43
+ CLMA_90_185/CECO td 0.184 8.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 8.683 ntR1851
+ CLMA_90_193/CECO td 0.184 8.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 8.867 ntR1850
+ CLMA_90_197/CECI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 8.867 Logic Levels: 5
+ Logic: 1.911ns(63.700%), Route: 1.089ns(36.300%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 5.000 5.000 r
@@ -2191,34 +2186,34 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 7.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 8.843 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 8.843 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.531 10.374 ntR3909
- CLMA_246_180/CLK r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm/CLK
- clock pessimism 0.439 10.813
- clock uncertainty -0.150 10.663
+ net (fanout=2) 1.059 8.843 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.493 10.867
+ clock uncertainty -0.150 10.717
- Setup time -0.426 10.237
+ Setup time -0.729 9.988
- Data required time 10.237
+ Data required time 9.988
----------------------------------------------------------------------------------------------------
- Data required time 10.237
- Data arrival time 11.025
+ Data required time 9.988
+ Data arrival time 8.867
----------------------------------------------------------------------------------------------------
- Slack (VIOLATED) -0.788
+ Slack (MET) 1.121
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK
-Endpoint : u_zoom_image/mult_image_r0_0/N2/gopapm/X[0]
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE
Path Group : clk_200m
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.495
+Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.374
Launch Clock Delay : 5.867
- Clock Pessimism Removal : 0.439
+ Clock Pessimism Removal : 0.493
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -2231,17 +2226,27 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.585 5.867 ntR3909
- APM_206_140/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK
-
- APM_206_140/P[31] tco 1.067 6.934 f u_zoom_image/mult_fra0_0/N2/gopapm/P[7]
- net (fanout=3) 2.395 9.329 u_zoom_image/coe_mult_p0_0 [7]
- APM_206_328/X[0] f u_zoom_image/mult_image_r0_0/N2/gopapm/X[0]
-
- Data arrival time 9.329 Logic Levels: 0
- Logic: 1.067ns(30.820%), Route: 2.395ns(69.180%)
+ net (fanout=2) 1.078 4.282 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_90_197/Q1 tco 0.291 6.158 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q
+ net (fanout=2) 0.408 6.566 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15]
+ CLMS_94_197/Y0 td 0.487 7.053 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z
+ net (fanout=2) 0.123 7.176 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154
+ CLMA_94_196/Y2 td 0.478 7.654 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z
+ net (fanout=1) 0.120 7.774 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157
+ CLMA_94_196/Y3 td 0.287 8.061 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z
+ net (fanout=11) 0.438 8.499 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43
+ CLMA_90_185/CECO td 0.184 8.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 8.683 ntR1851
+ CLMA_90_193/CECO td 0.184 8.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 8.867 ntR1850
+ CLMA_90_197/CECI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 8.867 Logic Levels: 5
+ Logic: 1.911ns(63.700%), Route: 1.089ns(36.300%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 5.000 5.000 r
@@ -2252,34 +2257,34 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 7.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 8.843 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 8.843 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.652 10.495 ntR3909
- APM_206_328/CLK r u_zoom_image/mult_image_r0_0/N2/gopapm/CLK
- clock pessimism 0.439 10.934
- clock uncertainty -0.150 10.784
+ net (fanout=2) 1.059 8.843 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.493 10.867
+ clock uncertainty -0.150 10.717
- Setup time -2.243 8.541
+ Setup time -0.729 9.988
- Data required time 8.541
+ Data required time 9.988
----------------------------------------------------------------------------------------------------
- Data required time 8.541
- Data arrival time 9.329
+ Data required time 9.988
+ Data arrival time 8.867
----------------------------------------------------------------------------------------------------
- Slack (VIOLATED) -0.788
+ Slack (MET) 1.121
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK
-Endpoint : u_zoom_image/mult_image_r0_0/N2/gopapm/X[3]
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE
Path Group : clk_200m
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.495
+Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.374
Launch Clock Delay : 5.867
- Clock Pessimism Removal : 0.439
+ Clock Pessimism Removal : 0.493
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -2292,17 +2297,27 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.585 5.867 ntR3909
- APM_206_140/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK
-
- APM_206_140/P[34] tco 1.067 6.934 f u_zoom_image/mult_fra0_0/N2/gopapm/P[10]
- net (fanout=3) 2.347 9.281 u_zoom_image/coe_mult_p0_0 [10]
- APM_206_328/X[3] f u_zoom_image/mult_image_r0_0/N2/gopapm/X[3]
-
- Data arrival time 9.281 Logic Levels: 0
- Logic: 1.067ns(31.254%), Route: 2.347ns(68.746%)
+ net (fanout=2) 1.078 4.282 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_90_197/Q1 tco 0.291 6.158 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q
+ net (fanout=2) 0.408 6.566 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15]
+ CLMS_94_197/Y0 td 0.487 7.053 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z
+ net (fanout=2) 0.123 7.176 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154
+ CLMA_94_196/Y2 td 0.478 7.654 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z
+ net (fanout=1) 0.120 7.774 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157
+ CLMA_94_196/Y3 td 0.287 8.061 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z
+ net (fanout=11) 0.438 8.499 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43
+ CLMA_90_185/CECO td 0.184 8.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 8.683 ntR1851
+ CLMA_90_193/CECO td 0.184 8.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 8.867 ntR1850
+ CLMA_90_197/CECI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 8.867 Logic Levels: 5
+ Logic: 1.911ns(63.700%), Route: 1.089ns(36.300%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 5.000 5.000 r
@@ -2313,34 +2328,34 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 7.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 8.843 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 8.843 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.652 10.495 ntR3909
- APM_206_328/CLK r u_zoom_image/mult_image_r0_0/N2/gopapm/CLK
- clock pessimism 0.439 10.934
- clock uncertainty -0.150 10.784
+ net (fanout=2) 1.059 8.843 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.493 10.867
+ clock uncertainty -0.150 10.717
- Setup time -2.243 8.541
+ Setup time -0.729 9.988
- Data required time 8.541
+ Data required time 9.988
----------------------------------------------------------------------------------------------------
- Data required time 8.541
- Data arrival time 9.281
+ Data required time 9.988
+ Data arrival time 8.867
----------------------------------------------------------------------------------------------------
- Slack (VIOLATED) -0.740
+ Slack (MET) 1.121
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK
-Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[0]
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D
Path Group : clk_200m
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.990
+Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.867
Launch Clock Delay : 5.374
- Clock Pessimism Removal : -0.439
+ Clock Pessimism Removal : -0.464
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -2353,17 +2368,17 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.531 5.374 ntR3909
- APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK
+ net (fanout=2) 1.059 3.843 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.531 5.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMS_94_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK
- APM_206_240/PO[0] tco 0.297 5.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[0]
- net (fanout=1) 0.000 5.671 u_zoom_image/mult_image0[2] [0]
- APM_206_252/PI[0] r u_zoom_image/mult_image_g1/N2/gopapm/PI[0]
+ CLMS_94_193/Q0 tco 0.226 5.600 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/Q
+ net (fanout=3) 0.104 5.704 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d [1]
+ CLMA_94_192/M0 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D
- Data arrival time 5.671 Logic Levels: 0
- Logic: 0.297ns(100.000%), Route: 0.000ns(0.000%)
+ Data arrival time 5.704 Logic Levels: 0
+ Logic: 0.226ns(68.485%), Route: 0.104ns(31.515%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 0.000 0.000 r
@@ -2374,34 +2389,34 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.708 5.990 ntR3909
- APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK
- clock pessimism -0.439 5.551
- clock uncertainty 0.000 5.551
+ net (fanout=2) 1.078 4.282 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_94_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/CLK
+ clock pessimism -0.464 5.403
+ clock uncertainty 0.000 5.403
- Hold time -0.121 5.430
+ Hold time -0.014 5.389
- Data required time 5.430
+ Data required time 5.389
----------------------------------------------------------------------------------------------------
- Data required time 5.430
- Data arrival time 5.671
+ Data required time 5.389
+ Data arrival time 5.704
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.241
+ Slack (MET) 0.315
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK
-Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[1]
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4
Path Group : clk_200m
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.990
+Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.867
Launch Clock Delay : 5.374
- Clock Pessimism Removal : -0.439
+ Clock Pessimism Removal : -0.493
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -2414,17 +2429,17 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.531 5.374 ntR3909
- APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK
+ net (fanout=2) 1.059 3.843 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.531 5.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK
- APM_206_240/PO[1] tco 0.297 5.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[1]
- net (fanout=1) 0.000 5.671 u_zoom_image/mult_image0[2] [1]
- APM_206_252/PI[1] r u_zoom_image/mult_image_g1/N2/gopapm/PI[1]
+ CLMS_38_185/Q3 tco 0.221 5.595 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/Q
+ net (fanout=3) 0.087 5.682 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [4]
+ CLMS_38_185/D4 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4
- Data arrival time 5.671 Logic Levels: 0
- Logic: 0.297ns(100.000%), Route: 0.000ns(0.000%)
+ Data arrival time 5.682 Logic Levels: 0
+ Logic: 0.221ns(71.753%), Route: 0.087ns(28.247%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 0.000 0.000 r
@@ -2435,34 +2450,34 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.708 5.990 ntR3909
- APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK
- clock pessimism -0.439 5.551
- clock uncertainty 0.000 5.551
+ net (fanout=2) 1.078 4.282 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism -0.493 5.374
+ clock uncertainty 0.000 5.374
- Hold time -0.121 5.430
+ Hold time -0.034 5.340
- Data required time 5.430
+ Data required time 5.340
----------------------------------------------------------------------------------------------------
- Data required time 5.430
- Data arrival time 5.671
+ Data required time 5.340
+ Data arrival time 5.682
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.241
+ Slack (MET) 0.342
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK
-Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[2]
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4
Path Group : clk_200m
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.990
+Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.867
Launch Clock Delay : 5.374
- Clock Pessimism Removal : -0.439
+ Clock Pessimism Removal : -0.493
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -2475,17 +2490,17 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.531 5.374 ntR3909
- APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK
+ net (fanout=2) 1.059 3.843 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.531 5.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK
- APM_206_240/PO[2] tco 0.297 5.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[2]
- net (fanout=1) 0.000 5.671 u_zoom_image/mult_image0[2] [2]
- APM_206_252/PI[2] r u_zoom_image/mult_image_g1/N2/gopapm/PI[2]
+ CLMS_38_185/Q0 tco 0.222 5.596 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/Q
+ net (fanout=4) 0.087 5.683 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [2]
+ CLMS_38_185/B4 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4
- Data arrival time 5.671 Logic Levels: 0
- Logic: 0.297ns(100.000%), Route: 0.000ns(0.000%)
+ Data arrival time 5.683 Logic Levels: 0
+ Logic: 0.222ns(71.845%), Route: 0.087ns(28.155%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 0.000 0.000 r
@@ -2496,34 +2511,34 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.708 5.990 ntR3909
- APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK
- clock pessimism -0.439 5.551
- clock uncertainty 0.000 5.551
+ net (fanout=2) 1.078 4.282 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism -0.493 5.374
+ clock uncertainty 0.000 5.374
- Hold time -0.121 5.430
+ Hold time -0.035 5.339
- Data required time 5.430
+ Data required time 5.339
----------------------------------------------------------------------------------------------------
- Data required time 5.430
- Data arrival time 5.671
+ Data required time 5.339
+ Data arrival time 5.683
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.241
+ Slack (MET) 0.344
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D
+Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
+Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D
Path Group : clk_25m
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 5.383
Launch Clock Delay : 5.877
- Clock Pessimism Removal : 0.494
+ Clock Pessimism Removal : 0.465
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -2537,26 +2552,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-
- CLMA_182_17/Q0 tco 0.289 6.166 r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q
- net (fanout=4) 0.557 6.723 u_ov5640/coms1_reg_config/clock_20k_cnt [0]
- CLMA_182_13/Y2 td 0.487 7.210 r u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z
- net (fanout=1) 0.403 7.613 u_ov5640/coms1_reg_config/_N9664
- CLMA_186_16/Y0 td 0.210 7.823 r u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z
- net (fanout=13) 0.777 8.600 u_ov5640/coms1_reg_config/N8
- CLMA_182_12/COUT td 0.507 9.107 r u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Cout
- net (fanout=1) 0.000 9.107 u_ov5640/coms1_reg_config/_N16248
- td 0.058 9.165 r u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Cout
- net (fanout=1) 0.000 9.165 u_ov5640/coms1_reg_config/_N16250
- CLMA_182_16/Y3 td 0.501 9.666 r u_ov5640/coms1_reg_config/N11_2_7/gateop_A2/Y1
- net (fanout=1) 0.563 10.229 u_ov5640/coms1_reg_config/N1114 [8]
- CLMA_182_17/M2 r u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D
-
- Data arrival time 10.229 Logic Levels: 4
- Logic: 2.052ns(47.151%), Route: 2.300ns(52.849%)
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMS_122_13/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
+
+ CLMS_122_13/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q
+ net (fanout=4) 0.406 6.574 u_ov5640/coms2_reg_config/clock_20k_cnt [0]
+ CLMA_122_16/Y3 td 0.468 7.042 r u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z
+ net (fanout=1) 0.560 7.602 u_ov5640/coms2_reg_config/_N9749
+ CLMA_122_16/Y2 td 0.210 7.812 r u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z
+ net (fanout=13) 0.569 8.381 u_ov5640/coms2_reg_config/N8
+ td 0.477 8.858 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout
+ net (fanout=1) 0.000 8.858 u_ov5640/coms2_reg_config/_N16307
+ CLMS_122_17/COUT td 0.058 8.916 r u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout
+ net (fanout=1) 0.000 8.916 u_ov5640/coms2_reg_config/_N16309
+ CLMS_122_21/Y1 td 0.498 9.414 r u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y1
+ net (fanout=1) 0.704 10.118 u_ov5640/coms2_reg_config/N1114 [10]
+ CLMS_122_17/M3 r u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D
+
+ Data arrival time 10.118 Logic Levels: 4
+ Logic: 2.002ns(47.206%), Route: 2.239ns(52.794%)
----------------------------------------------------------------------------------------------------
Clock clk_25m (rising edge) 40.000 40.000 r
@@ -2568,26 +2583,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.758 42.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 42.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 43.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 45.383 ntclkbufg_7
- CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK
- clock pessimism 0.494 45.877
- clock uncertainty -0.150 45.727
+ USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 45.383 ntclkbufg_8
+ CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK
+ clock pessimism 0.465 45.848
+ clock uncertainty -0.150 45.698
- Setup time -0.079 45.648
+ Setup time -0.079 45.619
- Data required time 45.648
+ Data required time 45.619
----------------------------------------------------------------------------------------------------
- Data required time 45.648
- Data arrival time 10.229
+ Data required time 45.619
+ Data arrival time 10.118
----------------------------------------------------------------------------------------------------
- Slack (MET) 35.419
+ Slack (MET) 35.501
====================================================================================================
====================================================================================================
Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D
+Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D
Path Group : clk_25m
Path Type : max (slow corner)
Path Class : sequential timing path
@@ -2608,26 +2623,24 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_21/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-
- CLMA_182_21/Q2 tco 0.290 6.167 r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q
- net (fanout=4) 0.548 6.715 u_ov5640/coms2_reg_config/clock_20k_cnt [0]
- CLMA_186_16/Y1 td 0.468 7.183 r u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z
- net (fanout=1) 0.398 7.581 u_ov5640/coms2_reg_config/_N9736
- CLMA_186_20/Y1 td 0.304 7.885 r u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z
- net (fanout=13) 0.644 8.529 u_ov5640/coms2_reg_config/N8
- td 0.477 9.006 f u_ov5640/coms2_reg_config/N11_2_1/gateop_A2/Cout
- net (fanout=1) 0.000 9.006 u_ov5640/coms2_reg_config/_N16399
- CLMA_182_21/COUT td 0.058 9.064 r u_ov5640/coms2_reg_config/N11_2_3/gateop_A2/Cout
- net (fanout=1) 0.000 9.064 u_ov5640/coms2_reg_config/_N16401
- CLMA_182_25/Y1 td 0.498 9.562 r u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Y1
- net (fanout=1) 0.622 10.184 u_ov5640/coms2_reg_config/N1114 [6]
- CLMA_182_20/M1 r u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D
-
- Data arrival time 10.184 Logic Levels: 4
- Logic: 2.095ns(48.642%), Route: 2.212ns(51.358%)
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMS_122_13/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
+
+ CLMS_122_13/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q
+ net (fanout=4) 0.406 6.574 u_ov5640/coms2_reg_config/clock_20k_cnt [0]
+ CLMA_122_16/Y3 td 0.468 7.042 r u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z
+ net (fanout=1) 0.560 7.602 u_ov5640/coms2_reg_config/_N9749
+ CLMA_122_16/Y2 td 0.210 7.812 r u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z
+ net (fanout=13) 0.569 8.381 u_ov5640/coms2_reg_config/N8
+ td 0.477 8.858 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout
+ net (fanout=1) 0.000 8.858 u_ov5640/coms2_reg_config/_N16307
+ CLMS_122_17/Y3 td 0.501 9.359 r u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Y1
+ net (fanout=1) 0.747 10.106 u_ov5640/coms2_reg_config/N1114 [8]
+ CLMS_122_17/M2 r u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D
+
+ Data arrival time 10.106 Logic Levels: 3
+ Logic: 1.947ns(46.039%), Route: 2.282ns(53.961%)
----------------------------------------------------------------------------------------------------
Clock clk_25m (rising edge) 40.000 40.000 r
@@ -2639,9 +2652,9 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.758 42.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 42.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 43.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 45.383 ntclkbufg_7
- CLMA_182_20/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/CLK
+ USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 45.383 ntclkbufg_8
+ CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK
clock pessimism 0.465 45.848
clock uncertainty -0.150 45.698
@@ -2650,15 +2663,15 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
Data required time 45.619
----------------------------------------------------------------------------------------------------
Data required time 45.619
- Data arrival time 10.184
+ Data arrival time 10.106
----------------------------------------------------------------------------------------------------
- Slack (MET) 35.435
+ Slack (MET) 35.513
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/D
+Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
+Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D
Path Group : clk_25m
Path Type : max (slow corner)
Path Class : sequential timing path
@@ -2679,24 +2692,26 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-
- CLMA_182_17/Q0 tco 0.289 6.166 r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q
- net (fanout=4) 0.557 6.723 u_ov5640/coms1_reg_config/clock_20k_cnt [0]
- CLMA_182_13/Y2 td 0.487 7.210 r u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z
- net (fanout=1) 0.403 7.613 u_ov5640/coms1_reg_config/_N9664
- CLMA_186_16/Y0 td 0.210 7.823 r u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z
- net (fanout=13) 0.598 8.421 u_ov5640/coms1_reg_config/N8
- td 0.477 8.898 f u_ov5640/coms1_reg_config/N11_2_1/gateop_A2/Cout
- net (fanout=1) 0.000 8.898 u_ov5640/coms1_reg_config/_N16246
- CLMA_182_12/Y3 td 0.501 9.399 r u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Y1
- net (fanout=1) 0.770 10.169 u_ov5640/coms1_reg_config/N1114 [4]
- CLMA_182_16/M0 r u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/D
-
- Data arrival time 10.169 Logic Levels: 3
- Logic: 1.964ns(45.760%), Route: 2.328ns(54.240%)
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMS_122_13/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
+
+ CLMS_122_13/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q
+ net (fanout=4) 0.406 6.574 u_ov5640/coms2_reg_config/clock_20k_cnt [0]
+ CLMA_122_16/Y3 td 0.468 7.042 r u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z
+ net (fanout=1) 0.560 7.602 u_ov5640/coms2_reg_config/_N9749
+ CLMA_122_16/Y2 td 0.210 7.812 r u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z
+ net (fanout=13) 0.569 8.381 u_ov5640/coms2_reg_config/N8
+ td 0.477 8.858 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout
+ net (fanout=1) 0.000 8.858 u_ov5640/coms2_reg_config/_N16307
+ CLMS_122_17/COUT td 0.058 8.916 r u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout
+ net (fanout=1) 0.000 8.916 u_ov5640/coms2_reg_config/_N16309
+ CLMS_122_21/Y0 td 0.267 9.183 f u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y0
+ net (fanout=1) 0.710 9.893 u_ov5640/coms2_reg_config/N1114 [9]
+ CLMS_122_17/M1 f u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D
+
+ Data arrival time 9.893 Logic Levels: 4
+ Logic: 1.771ns(44.099%), Route: 2.245ns(55.901%)
----------------------------------------------------------------------------------------------------
Clock clk_25m (rising edge) 40.000 40.000 r
@@ -2708,20 +2723,20 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.758 42.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 42.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 43.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 45.383 ntclkbufg_7
- CLMA_182_16/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK
+ USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 45.383 ntclkbufg_8
+ CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/CLK
clock pessimism 0.465 45.848
clock uncertainty -0.150 45.698
- Setup time -0.079 45.619
+ Setup time -0.088 45.610
- Data required time 45.619
+ Data required time 45.610
----------------------------------------------------------------------------------------------------
- Data required time 45.619
- Data arrival time 10.169
+ Data required time 45.610
+ Data arrival time 9.893
----------------------------------------------------------------------------------------------------
- Slack (MET) 35.450
+ Slack (MET) 35.717
====================================================================================================
====================================================================================================
@@ -2748,16 +2763,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 3.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 5.383 ntclkbufg_7
- CLMA_182_12/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+ USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 5.383 ntclkbufg_8
+ CLMS_122_9/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
- CLMA_182_12/Q1 tco 0.229 5.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 0.332 5.944 u_ov5640/coms1_reg_config/clk_20k_regdiv
- CLMA_182_12/M0 r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
+ CLMS_122_9/Q1 tco 0.224 5.607 f u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 0.302 5.909 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ CLMS_122_9/M0 f u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
- Data arrival time 5.944 Logic Levels: 0
- Logic: 0.229ns(40.820%), Route: 0.332ns(59.180%)
+ Data arrival time 5.909 Logic Levels: 0
+ Logic: 0.224ns(42.586%), Route: 0.302ns(57.414%)
----------------------------------------------------------------------------------------------------
Clock clk_25m (rising edge) 0.000 0.000 r
@@ -2769,20 +2784,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_12/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMS_122_9/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
clock pessimism -0.494 5.383
clock uncertainty 0.000 5.383
- Hold time -0.014 5.369
+ Hold time -0.024 5.359
- Data required time 5.369
+ Data required time 5.359
----------------------------------------------------------------------------------------------------
- Data required time 5.369
- Data arrival time 5.944
+ Data required time 5.359
+ Data arrival time 5.909
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.575
+ Slack (MET) 0.550
====================================================================================================
====================================================================================================
@@ -2809,16 +2824,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 3.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 5.383 ntclkbufg_7
- CLMA_182_25/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+ USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 5.383 ntclkbufg_8
+ CLMA_122_12/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK
- CLMA_182_25/Q1 tco 0.229 5.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 0.468 6.080 u_ov5640/coms2_reg_config/clk_20k_regdiv
- CLMA_182_25/M0 r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
+ CLMA_122_12/Q1 tco 0.229 5.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 0.338 5.950 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ CLMA_122_12/M0 r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
- Data arrival time 6.080 Logic Levels: 0
- Logic: 0.229ns(32.855%), Route: 0.468ns(67.145%)
+ Data arrival time 5.950 Logic Levels: 0
+ Logic: 0.229ns(40.388%), Route: 0.338ns(59.612%)
----------------------------------------------------------------------------------------------------
Clock clk_25m (rising edge) 0.000 0.000 r
@@ -2830,9 +2845,9 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_25/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMA_122_12/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
clock pessimism -0.494 5.383
clock uncertainty 0.000 5.383
@@ -2841,15 +2856,15 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 5.369
----------------------------------------------------------------------------------------------------
Data required time 5.369
- Data arrival time 6.080
+ Data arrival time 5.950
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.711
+ Slack (MET) 0.581
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK
-Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D
+Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK
+Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D
Path Group : clk_25m
Path Type : min (slow corner)
Path Class : sequential timing path
@@ -2870,18 +2885,18 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 3.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 5.383 ntclkbufg_7
- CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK
+ USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 5.383 ntclkbufg_8
+ CLMS_118_13/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK
- CLMA_182_17/Y0 tco 0.284 5.667 f u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/Q
- net (fanout=2) 0.086 5.753 u_ov5640/coms1_reg_config/clock_20k_cnt [5]
- CLMA_182_16/Y0 td 0.232 5.985 f u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Y0
- net (fanout=1) 0.193 6.178 u_ov5640/coms1_reg_config/N1114 [5]
- CLMA_182_17/AD f u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D
+ CLMS_118_13/Q0 tco 0.222 5.605 f u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/Q
+ net (fanout=3) 0.086 5.691 u_ov5640/coms1_reg_config/clock_20k_cnt [1]
+ CLMS_118_13/Y0 td 0.229 5.920 r u_ov5640/coms1_reg_config/N11_2_1/gateop_A2/Y0
+ net (fanout=1) 0.104 6.024 u_ov5640/coms1_reg_config/N1114 [1]
+ CLMS_118_13/M0 r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D
- Data arrival time 6.178 Logic Levels: 1
- Logic: 0.516ns(64.906%), Route: 0.279ns(35.094%)
+ Data arrival time 6.024 Logic Levels: 1
+ Logic: 0.451ns(70.359%), Route: 0.190ns(29.641%)
----------------------------------------------------------------------------------------------------
Clock clk_25m (rising edge) 0.000 0.000 r
@@ -2893,33 +2908,33 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMS_118_13/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK
clock pessimism -0.494 5.383
clock uncertainty 0.000 5.383
- Hold time 0.053 5.436
+ Hold time -0.014 5.369
- Data required time 5.436
+ Data required time 5.369
----------------------------------------------------------------------------------------------------
- Data required time 5.436
- Data arrival time 6.178
+ Data required time 5.369
+ Data arrival time 6.024
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.742
+ Slack (MET) 0.655
====================================================================================================
====================================================================================================
Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-Endpoint : ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/L4
+Endpoint : ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE
Path Group : clk_10m
Path Type : max (slow corner)
Path Class : sequential timing path
Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.378
- Launch Clock Delay : 5.873
- Clock Pessimism Removal : 0.459
+ Capture Clock Delay : 5.499
+ Launch Clock Delay : 5.996
+ Clock Pessimism Removal : 0.461
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -2933,28 +2948,28 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.078 4.288 clk_10m
- USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.585 5.873 ntclkbufg_3
- CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-
- CLMS_242_113/Q3 tco 0.288 6.161 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
- net (fanout=3) 0.420 6.581 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
- CLMS_246_113/Y2 td 0.487 7.068 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
- net (fanout=1) 0.120 7.188 ms72xx_ctl/ms7200_ctl/_N95853
- CLMS_246_113/Y0 td 0.210 7.398 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
- net (fanout=6) 0.421 7.819 ms72xx_ctl/ms7200_ctl/_N95857
- CLMS_242_117/Y1 td 0.304 8.123 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
- net (fanout=15) 0.790 8.913 ms72xx_ctl/ms7200_ctl/N261
- CLMA_226_104/Y1 td 0.212 9.125 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
- net (fanout=4) 0.550 9.675 ms72xx_ctl/ms7200_ctl/N2093 [4]
- CLMA_230_108/Y0 td 0.210 9.885 r ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/Z
- net (fanout=2) 0.608 10.493 ms72xx_ctl/ms7200_ctl/state_n [1]
- CLMS_226_105/Y0 td 0.487 10.980 r ms72xx_ctl/ms7200_ctl/N1797/gateop_perm/Z
- net (fanout=1) 0.412 11.392 ms72xx_ctl/ms7200_ctl/N1797
- CLMA_230_105/A4 r ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/L4
-
- Data arrival time 11.392 Logic Levels: 6
- Logic: 2.198ns(39.826%), Route: 3.321ns(60.174%)
+ USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.708 5.996 ntclkbufg_4
+ CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_218_329/Q2 tco 0.290 6.286 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
+ net (fanout=3) 0.271 6.557 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
+ CLMS_218_333/Y3 td 0.459 7.016 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
+ net (fanout=1) 0.257 7.273 ms72xx_ctl/ms7200_ctl/_N96627
+ CLMS_218_333/Y0 td 0.210 7.483 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
+ net (fanout=6) 0.412 7.895 ms72xx_ctl/ms7200_ctl/_N96632
+ CLMS_222_329/Y0 td 0.210 8.105 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
+ net (fanout=15) 0.564 8.669 ms72xx_ctl/ms7200_ctl/N261
+ CLMS_214_321/Y0 td 0.320 8.989 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
+ net (fanout=4) 0.548 9.537 ms72xx_ctl/ms7200_ctl/N2093 [4]
+ CLMA_222_324/Y1 td 0.212 9.749 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z
+ net (fanout=12) 0.560 10.309 ms72xx_ctl/ms7200_ctl/N1955
+ CLMA_230_324/CECO td 0.184 10.493 r ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 10.493 ntR1800
+ CLMA_230_328/CECI r ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 10.493 Logic Levels: 6
+ Logic: 1.885ns(41.917%), Route: 2.612ns(58.083%)
----------------------------------------------------------------------------------------------------
Clock clk_10m (rising edge) 100.000 100.000 r
@@ -2966,33 +2981,33 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.758 102.688 _N69
PLL_158_55/CLK_OUT4 td 0.100 102.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.059 103.847 clk_10m
- USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.531 105.378 ntclkbufg_3
- CLMA_230_105/CLK r ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/CLK
- clock pessimism 0.459 105.837
- clock uncertainty -0.150 105.687
+ USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.652 105.499 ntclkbufg_4
+ CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.461 105.960
+ clock uncertainty -0.150 105.810
- Setup time -0.121 105.566
+ Setup time -0.729 105.081
- Data required time 105.566
+ Data required time 105.081
----------------------------------------------------------------------------------------------------
- Data required time 105.566
- Data arrival time 11.392
+ Data required time 105.081
+ Data arrival time 10.493
----------------------------------------------------------------------------------------------------
- Slack (MET) 94.174
+ Slack (MET) 94.588
====================================================================================================
====================================================================================================
Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-Endpoint : ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CE
+Endpoint : ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE
Path Group : clk_10m
Path Type : max (slow corner)
Path Class : sequential timing path
Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.378
- Launch Clock Delay : 5.873
- Clock Pessimism Removal : 0.459
+ Capture Clock Delay : 5.499
+ Launch Clock Delay : 5.996
+ Clock Pessimism Removal : 0.461
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -3006,28 +3021,28 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.078 4.288 clk_10m
- USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.585 5.873 ntclkbufg_3
- CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-
- CLMS_242_113/Q3 tco 0.288 6.161 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
- net (fanout=3) 0.420 6.581 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
- CLMS_246_113/Y2 td 0.487 7.068 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
- net (fanout=1) 0.120 7.188 ms72xx_ctl/ms7200_ctl/_N95853
- CLMS_246_113/Y0 td 0.210 7.398 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
- net (fanout=6) 0.421 7.819 ms72xx_ctl/ms7200_ctl/_N95857
- CLMS_242_117/Y1 td 0.304 8.123 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
- net (fanout=15) 0.790 8.913 ms72xx_ctl/ms7200_ctl/N261
- CLMA_226_104/Y1 td 0.212 9.125 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
- net (fanout=4) 0.550 9.675 ms72xx_ctl/ms7200_ctl/N2093 [4]
- CLMA_230_108/Y0 td 0.210 9.885 r ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/Z
- net (fanout=2) 0.656 10.541 ms72xx_ctl/ms7200_ctl/state_n [1]
- CLMS_226_105/Y1 td 0.197 10.738 f ms72xx_ctl/ms7200_ctl/N8_7/gateop_perm/Z
- net (fanout=3) 0.102 10.840 ms72xx_ctl/ms7200_ctl/N8
- CLMS_226_105/CE f ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CE
-
- Data arrival time 10.840 Logic Levels: 6
- Logic: 1.908ns(38.414%), Route: 3.059ns(61.586%)
+ USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.708 5.996 ntclkbufg_4
+ CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_218_329/Q2 tco 0.290 6.286 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
+ net (fanout=3) 0.271 6.557 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
+ CLMS_218_333/Y3 td 0.459 7.016 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
+ net (fanout=1) 0.257 7.273 ms72xx_ctl/ms7200_ctl/_N96627
+ CLMS_218_333/Y0 td 0.210 7.483 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
+ net (fanout=6) 0.412 7.895 ms72xx_ctl/ms7200_ctl/_N96632
+ CLMS_222_329/Y0 td 0.210 8.105 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
+ net (fanout=15) 0.564 8.669 ms72xx_ctl/ms7200_ctl/N261
+ CLMS_214_321/Y0 td 0.320 8.989 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
+ net (fanout=4) 0.548 9.537 ms72xx_ctl/ms7200_ctl/N2093 [4]
+ CLMA_222_324/Y1 td 0.212 9.749 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z
+ net (fanout=12) 0.560 10.309 ms72xx_ctl/ms7200_ctl/N1955
+ CLMA_230_324/CECO td 0.184 10.493 r ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 10.493 ntR1800
+ CLMA_230_328/CECI r ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 10.493 Logic Levels: 6
+ Logic: 1.885ns(41.917%), Route: 2.612ns(58.083%)
----------------------------------------------------------------------------------------------------
Clock clk_10m (rising edge) 100.000 100.000 r
@@ -3039,33 +3054,33 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.758 102.688 _N69
PLL_158_55/CLK_OUT4 td 0.100 102.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.059 103.847 clk_10m
- USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.531 105.378 ntclkbufg_3
- CLMS_226_105/CLK r ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CLK
- clock pessimism 0.459 105.837
- clock uncertainty -0.150 105.687
+ USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.652 105.499 ntclkbufg_4
+ CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.461 105.960
+ clock uncertainty -0.150 105.810
- Setup time -0.617 105.070
+ Setup time -0.729 105.081
- Data required time 105.070
+ Data required time 105.081
----------------------------------------------------------------------------------------------------
- Data required time 105.070
- Data arrival time 10.840
+ Data required time 105.081
+ Data arrival time 10.493
----------------------------------------------------------------------------------------------------
- Slack (MET) 94.230
+ Slack (MET) 94.588
====================================================================================================
====================================================================================================
Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-Endpoint : ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CE
+Endpoint : ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE
Path Group : clk_10m
Path Type : max (slow corner)
Path Class : sequential timing path
Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.378
- Launch Clock Delay : 5.873
- Clock Pessimism Removal : 0.459
+ Capture Clock Delay : 5.499
+ Launch Clock Delay : 5.996
+ Clock Pessimism Removal : 0.461
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -3079,28 +3094,28 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.078 4.288 clk_10m
- USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.585 5.873 ntclkbufg_3
- CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-
- CLMS_242_113/Q3 tco 0.288 6.161 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
- net (fanout=3) 0.420 6.581 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
- CLMS_246_113/Y2 td 0.487 7.068 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
- net (fanout=1) 0.120 7.188 ms72xx_ctl/ms7200_ctl/_N95853
- CLMS_246_113/Y0 td 0.210 7.398 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
- net (fanout=6) 0.421 7.819 ms72xx_ctl/ms7200_ctl/_N95857
- CLMS_242_117/Y1 td 0.304 8.123 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
- net (fanout=15) 0.790 8.913 ms72xx_ctl/ms7200_ctl/N261
- CLMA_226_104/Y1 td 0.212 9.125 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
- net (fanout=4) 0.550 9.675 ms72xx_ctl/ms7200_ctl/N2093 [4]
- CLMA_230_108/Y0 td 0.210 9.885 r ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/Z
- net (fanout=2) 0.656 10.541 ms72xx_ctl/ms7200_ctl/state_n [1]
- CLMS_226_105/Y1 td 0.197 10.738 f ms72xx_ctl/ms7200_ctl/N8_7/gateop_perm/Z
- net (fanout=3) 0.102 10.840 ms72xx_ctl/ms7200_ctl/N8
- CLMS_226_105/CE f ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CE
-
- Data arrival time 10.840 Logic Levels: 6
- Logic: 1.908ns(38.414%), Route: 3.059ns(61.586%)
+ USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.708 5.996 ntclkbufg_4
+ CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_218_329/Q2 tco 0.290 6.286 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
+ net (fanout=3) 0.271 6.557 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
+ CLMS_218_333/Y3 td 0.459 7.016 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
+ net (fanout=1) 0.257 7.273 ms72xx_ctl/ms7200_ctl/_N96627
+ CLMS_218_333/Y0 td 0.210 7.483 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
+ net (fanout=6) 0.412 7.895 ms72xx_ctl/ms7200_ctl/_N96632
+ CLMS_222_329/Y0 td 0.210 8.105 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
+ net (fanout=15) 0.564 8.669 ms72xx_ctl/ms7200_ctl/N261
+ CLMS_214_321/Y0 td 0.320 8.989 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
+ net (fanout=4) 0.548 9.537 ms72xx_ctl/ms7200_ctl/N2093 [4]
+ CLMA_222_324/Y1 td 0.212 9.749 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z
+ net (fanout=12) 0.560 10.309 ms72xx_ctl/ms7200_ctl/N1955
+ CLMA_230_324/CECO td 0.184 10.493 r ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 10.493 ntR1800
+ CLMA_230_328/CECI r ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 10.493 Logic Levels: 6
+ Logic: 1.885ns(41.917%), Route: 2.612ns(58.083%)
----------------------------------------------------------------------------------------------------
Clock clk_10m (rising edge) 100.000 100.000 r
@@ -3112,33 +3127,33 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.758 102.688 _N69
PLL_158_55/CLK_OUT4 td 0.100 102.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.059 103.847 clk_10m
- USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.531 105.378 ntclkbufg_3
- CLMS_226_105/CLK r ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CLK
- clock pessimism 0.459 105.837
- clock uncertainty -0.150 105.687
+ USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.652 105.499 ntclkbufg_4
+ CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.461 105.960
+ clock uncertainty -0.150 105.810
- Setup time -0.617 105.070
+ Setup time -0.729 105.081
- Data required time 105.070
+ Data required time 105.081
----------------------------------------------------------------------------------------------------
- Data required time 105.070
- Data arrival time 10.840
+ Data required time 105.081
+ Data arrival time 10.493
----------------------------------------------------------------------------------------------------
- Slack (MET) 94.230
+ Slack (MET) 94.588
====================================================================================================
====================================================================================================
-Startpoint : ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK
-Endpoint : ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D
+Startpoint : ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK
+Endpoint : ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D
Path Group : clk_10m
Path Type : min (slow corner)
Path Class : sequential timing path
Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.873
- Launch Clock Delay : 5.378
- Clock Pessimism Removal : -0.466
+ Capture Clock Delay : 5.996
+ Launch Clock Delay : 5.499
+ Clock Pessimism Removal : -0.468
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -3152,16 +3167,16 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT4 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.059 3.847 clk_10m
- USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.531 5.378 ntclkbufg_3
- CLMS_202_113/CLK r ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK
+ USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.652 5.499 ntclkbufg_4
+ CLMA_194_305/CLK r ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK
- CLMS_202_113/Q0 tco 0.226 5.604 r ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/Q
- net (fanout=2) 0.103 5.707 ms72xx_ctl/iic_dri_tx/receiv_data [1]
- CLMA_202_112/M0 r ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D
+ CLMA_194_305/Y2 tco 0.284 5.783 f ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/Q
+ net (fanout=2) 0.085 5.868 ms72xx_ctl/iic_dri_tx/receiv_data [5]
+ CLMA_194_304/CD f ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D
- Data arrival time 5.707 Logic Levels: 0
- Logic: 0.226ns(68.693%), Route: 0.103ns(31.307%)
+ Data arrival time 5.868 Logic Levels: 0
+ Logic: 0.284ns(76.965%), Route: 0.085ns(23.035%)
----------------------------------------------------------------------------------------------------
Clock clk_10m (rising edge) 0.000 0.000 r
@@ -3173,33 +3188,33 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.078 4.288 clk_10m
- USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.585 5.873 ntclkbufg_3
- CLMA_202_112/CLK r ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/CLK
- clock pessimism -0.466 5.407
- clock uncertainty 0.000 5.407
+ USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.708 5.996 ntclkbufg_4
+ CLMA_194_304/CLK r ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/CLK
+ clock pessimism -0.468 5.528
+ clock uncertainty 0.000 5.528
- Hold time -0.014 5.393
+ Hold time 0.053 5.581
- Data required time 5.393
+ Data required time 5.581
----------------------------------------------------------------------------------------------------
- Data required time 5.393
- Data arrival time 5.707
+ Data required time 5.581
+ Data arrival time 5.868
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.314
+ Slack (MET) 0.287
====================================================================================================
====================================================================================================
-Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK
-Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADB0[9]
+Startpoint : ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK
+Endpoint : ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D
Path Group : clk_10m
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.873
- Launch Clock Delay : 5.378
- Clock Pessimism Removal : -0.459
+Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.996
+ Launch Clock Delay : 5.499
+ Clock Pessimism Removal : -0.468
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -3213,16 +3228,16 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT4 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.059 3.847 clk_10m
- USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.531 5.378 ntclkbufg_3
- CLMA_230_117/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK
+ USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.652 5.499 ntclkbufg_4
+ CLMA_194_305/CLK r ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK
- CLMA_230_117/Q0 tco 0.226 5.604 r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q0
- net (fanout=3) 0.220 5.824 ms72xx_ctl/ms7200_ctl/cmd_index [4]
- DRM_234_108/ADB0[9] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADB0[9]
+ CLMA_194_305/Q0 tco 0.226 5.725 r ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/Q
+ net (fanout=2) 0.103 5.828 ms72xx_ctl/iic_dri_tx/receiv_data [1]
+ CLMA_194_304/M0 r ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D
- Data arrival time 5.824 Logic Levels: 0
- Logic: 0.226ns(50.673%), Route: 0.220ns(49.327%)
+ Data arrival time 5.828 Logic Levels: 0
+ Logic: 0.226ns(68.693%), Route: 0.103ns(31.307%)
----------------------------------------------------------------------------------------------------
Clock clk_10m (rising edge) 0.000 0.000 r
@@ -3234,33 +3249,33 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.078 4.288 clk_10m
- USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.585 5.873 ntclkbufg_3
- DRM_234_108/CLKB[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0]
- clock pessimism -0.459 5.414
- clock uncertainty 0.000 5.414
+ USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.708 5.996 ntclkbufg_4
+ CLMA_194_304/CLK r ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/CLK
+ clock pessimism -0.468 5.528
+ clock uncertainty 0.000 5.528
- Hold time 0.079 5.493
+ Hold time -0.014 5.514
- Data required time 5.493
+ Data required time 5.514
----------------------------------------------------------------------------------------------------
- Data required time 5.493
- Data arrival time 5.824
+ Data required time 5.514
+ Data arrival time 5.828
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.331
+ Slack (MET) 0.314
====================================================================================================
====================================================================================================
-Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK
-Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9]
+Startpoint : ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/CLK
+Endpoint : ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/D
Path Group : clk_10m
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.873
- Launch Clock Delay : 5.378
- Clock Pessimism Removal : -0.459
+Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.996
+ Launch Clock Delay : 5.499
+ Clock Pessimism Removal : -0.468
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -3274,16 +3289,16 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT4 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.059 3.847 clk_10m
- USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.531 5.378 ntclkbufg_3
- CLMA_230_117/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK
+ USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.652 5.499 ntclkbufg_4
+ CLMA_194_305/CLK r ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/CLK
- CLMA_230_117/Q0 tco 0.222 5.600 f ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q0
- net (fanout=3) 0.315 5.915 ms72xx_ctl/ms7200_ctl/cmd_index [4]
- DRM_234_108/ADA0[9] f ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9]
+ CLMA_194_305/Q2 tco 0.224 5.723 f ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/Q
+ net (fanout=1) 0.192 5.915 ms72xx_ctl/iic_dri_tx/receiv_data [7]
+ CLMA_194_304/AD f ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/D
Data arrival time 5.915 Logic Levels: 0
- Logic: 0.222ns(41.341%), Route: 0.315ns(58.659%)
+ Logic: 0.224ns(53.846%), Route: 0.192ns(46.154%)
----------------------------------------------------------------------------------------------------
Clock clk_10m (rising edge) 0.000 0.000 r
@@ -3295,38 +3310,38 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.078 4.288 clk_10m
- USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.585 5.873 ntclkbufg_3
- DRM_234_108/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
- clock pessimism -0.459 5.414
- clock uncertainty 0.000 5.414
+ USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.708 5.996 ntclkbufg_4
+ CLMA_194_304/CLK r ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/CLK
+ clock pessimism -0.468 5.528
+ clock uncertainty 0.000 5.528
- Hold time 0.161 5.575
+ Hold time 0.053 5.581
- Data required time 5.575
+ Data required time 5.581
----------------------------------------------------------------------------------------------------
- Data required time 5.575
+ Data required time 5.581
Data arrival time 5.915
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.340
+ Slack (MET) 0.334
====================================================================================================
====================================================================================================
-Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE
-Path Group : clk_720p60Hz
+Startpoint : u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+Endpoint : u_zoom_image/mult_image_g1_0/N2/gopapm/X[3]
+Path Group : clk_1080p60Hz
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 8.831
- Launch Clock Delay : 9.434
- Clock Pessimism Removal : 0.567
+Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 8.835
+ Launch Clock Delay : 9.563
+ Clock Pessimism Removal : 0.551
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
@@ -3336,79 +3351,406 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
- PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.599 7.849 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.585 9.434 ntclkbufg_2
- CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-
- CLMS_186_117/Q2 tco 0.290 9.724 r u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0
- net (fanout=1) 0.857 10.581 pos_y[7]
- CLMA_186_116/COUT td 0.515 11.096 r udp_osd_inst/N29.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 11.096 udp_osd_inst/N29.co [6]
- CLMA_186_120/Y1 td 0.498 11.594 r udp_osd_inst/N29.eq_4/gateop_A2/Y1
- net (fanout=5) 0.410 12.004 udp_osd_inst/N29
- CLMA_190_120/Y3 td 0.287 12.291 r udp_osd_inst/N69_5/gateop_perm/Z
- net (fanout=2) 0.551 12.842 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64
- CLMA_186_112/Y1 td 0.212 13.054 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z
- net (fanout=2) 0.401 13.455 udp_osd_inst/char_osd_inst/row_pixels_ready
- CLMA_186_108/Y2 td 0.210 13.665 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z
- net (fanout=6) 0.587 14.252 udp_osd_inst/char_osd_inst/char_next
- CLMA_182_88/Y3 td 0.210 14.462 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z
- net (fanout=1) 0.253 14.715 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79
- CLMA_182_88/Y2 td 0.210 14.925 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z
- net (fanout=3) 0.548 15.473 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518
- CLMA_186_80/Y0 td 0.341 15.814 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z
- net (fanout=1) 0.540 16.354 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786
- CLMA_182_73/CECO td 0.170 16.524 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT
- net (fanout=4) 0.000 16.524 ntR2038
- CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE
-
- Data arrival time 16.524 Logic Levels: 9
- Logic: 2.943ns(41.509%), Route: 4.147ns(58.491%)
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.708 9.563 ntclkbufg_3
+ APM_206_264/CLK r u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+
+ APM_206_264/P[34] tco 1.067 10.630 f u_zoom_image/mult_fra1_0/N2/gopapm/P[10]
+ net (fanout=3) 2.016 12.646 u_zoom_image/coe_mult_p1_0 [10]
+ APM_206_140/X[3] f u_zoom_image/mult_image_g1_0/N2/gopapm/X[3]
+
+ Data arrival time 12.646 Logic Levels: 0
+ Logic: 1.067ns(34.609%), Route: 2.016ns(65.391%)
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 13.473 13.473 r
- P20 0.000 13.473 r clk (port)
- net (fanout=1) 0.074 13.547 clk
- IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 15.355 clk_ibuf/ntD
- IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.758 16.161 _N69
- PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 1.059 17.320 rd3_clk
- USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 19.106 ntR3907
- PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.571 20.773 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.531 22.304 ntclkbufg_2
- CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK
- clock pessimism 0.567 22.871
- clock uncertainty -0.150 22.721
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.618 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 9.424 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 10.583 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 12.369 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 14.040 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.531 15.571 ntclkbufg_3
+ APM_206_140/CLK r u_zoom_image/mult_image_g1_0/N2/gopapm/CLK
+ clock pessimism 0.551 16.122
+ clock uncertainty -0.150 15.972
- Setup time -0.747 21.974
+ Setup time -2.243 13.729
- Data required time 21.974
+ Data required time 13.729
----------------------------------------------------------------------------------------------------
- Data required time 21.974
- Data arrival time 16.524
+ Data required time 13.729
+ Data arrival time 12.646
----------------------------------------------------------------------------------------------------
- Slack (MET) 5.450
+ Slack (MET) 1.083
====================================================================================================
====================================================================================================
-Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE
+Startpoint : u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+Endpoint : u_zoom_image/mult_image_g1_0/N2/gopapm/X[0]
+Path Group : clk_1080p60Hz
+Path Type : max (slow corner)
+Path Class : sequential timing path
+Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 8.835
+ Launch Clock Delay : 9.563
+ Clock Pessimism Removal : 0.551
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.708 9.563 ntclkbufg_3
+ APM_206_264/CLK r u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+
+ APM_206_264/P[31] tco 1.067 10.630 f u_zoom_image/mult_fra1_0/N2/gopapm/P[7]
+ net (fanout=3) 2.000 12.630 u_zoom_image/coe_mult_p1_0 [7]
+ APM_206_140/X[0] f u_zoom_image/mult_image_g1_0/N2/gopapm/X[0]
+
+ Data arrival time 12.630 Logic Levels: 0
+ Logic: 1.067ns(34.790%), Route: 2.000ns(65.210%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.618 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 9.424 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 10.583 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 12.369 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 14.040 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.531 15.571 ntclkbufg_3
+ APM_206_140/CLK r u_zoom_image/mult_image_g1_0/N2/gopapm/CLK
+ clock pessimism 0.551 16.122
+ clock uncertainty -0.150 15.972
+
+ Setup time -2.243 13.729
+
+ Data required time 13.729
+----------------------------------------------------------------------------------------------------
+ Data required time 13.729
+ Data arrival time 12.630
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 1.099
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK
+Endpoint : u_zoom_image/mult_image_g0_0/N2/gopapm/X[1]
+Path Group : clk_1080p60Hz
+Path Type : max (slow corner)
+Path Class : sequential timing path
+Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 8.835
+ Launch Clock Delay : 9.563
+ Clock Pessimism Removal : 0.551
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.708 9.563 ntclkbufg_3
+ APM_206_264/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK
+
+ APM_206_264/P[8] tco 1.067 10.630 f u_zoom_image/mult_fra0_0/N2/gopapm/P[8]
+ net (fanout=3) 1.968 12.598 u_zoom_image/coe_mult_p0_0 [8]
+ APM_206_128/X[1] f u_zoom_image/mult_image_g0_0/N2/gopapm/X[1]
+
+ Data arrival time 12.598 Logic Levels: 0
+ Logic: 1.067ns(35.157%), Route: 1.968ns(64.843%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.618 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 9.424 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 10.583 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 12.369 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 14.040 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.531 15.571 ntclkbufg_3
+ APM_206_128/CLK r u_zoom_image/mult_image_g0_0/N2/gopapm/CLK
+ clock pessimism 0.551 16.122
+ clock uncertainty -0.150 15.972
+
+ Setup time -2.243 13.729
+
+ Data required time 13.729
+----------------------------------------------------------------------------------------------------
+ Data required time 13.729
+ Data arrival time 12.598
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 1.131
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK
+Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7]
+Path Group : clk_1080p60Hz
+Path Type : min (slow corner)
+Path Class : sequential timing path
+Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 9.440
+ Launch Clock Delay : 8.835
+ Clock Pessimism Removal : -0.569
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.882 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 2.688 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 3.847 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 5.633 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 7.304 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.531 8.835 ntclkbufg_3
+ CLMA_146_76/CLK r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK
+
+ CLMA_146_76/Q2 tco 0.224 9.059 f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Q0
+ net (fanout=3) 0.234 9.293 u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/wr_addr [2]
+ DRM_142_68/ADA0[7] f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7]
+
+ Data arrival time 9.293 Logic Levels: 0
+ Logic: 0.224ns(48.908%), Route: 0.234ns(51.092%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.585 9.440 ntclkbufg_3
+ DRM_142_68/CLKA[0] r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA
+ clock pessimism -0.569 8.871
+ clock uncertainty 0.000 8.871
+
+ Hold time 0.210 9.081
+
+ Data required time 9.081
+----------------------------------------------------------------------------------------------------
+ Data required time 9.081
+ Data arrival time 9.293
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 0.212
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK
+Endpoint : u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5]
+Path Group : clk_1080p60Hz
+Path Type : min (slow corner)
+Path Class : sequential timing path
+Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 9.440
+ Launch Clock Delay : 8.835
+ Clock Pessimism Removal : -0.569
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.882 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 2.688 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 3.847 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 5.633 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 7.304 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.531 8.835 ntclkbufg_3
+ CLMS_174_177/CLK r u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK
+
+ CLMS_174_177/Q1 tco 0.224 9.059 f u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/Q1
+ net (fanout=6) 0.221 9.280 u_zoom_image/wr_addr1 [2]
+ DRM_178_168/ADA0[5] f u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5]
+
+ Data arrival time 9.280 Logic Levels: 0
+ Logic: 0.224ns(50.337%), Route: 0.221ns(49.663%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.585 9.440 ntclkbufg_3
+ DRM_178_168/CLKA[0] r u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism -0.569 8.871
+ clock uncertainty 0.000 8.871
+
+ Hold time 0.161 9.032
+
+ Data required time 9.032
+----------------------------------------------------------------------------------------------------
+ Data required time 9.032
+ Data arrival time 9.280
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 0.248
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_zoom_image/image_valid[2][1]/opit_0/CLK
+Endpoint : u_zoom_image/image_valid[3][1]/opit_0/D
+Path Group : clk_1080p60Hz
+Path Type : min (slow corner)
+Path Class : sequential timing path
+Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 9.440
+ Launch Clock Delay : 8.835
+ Clock Pessimism Removal : -0.605
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.882 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 2.688 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 3.847 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 5.633 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 7.304 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.531 8.835 ntclkbufg_3
+ CLMA_210_153/CLK r u_zoom_image/image_valid[2][1]/opit_0/CLK
+
+ CLMA_210_153/Q3 tco 0.221 9.056 f u_zoom_image/image_valid[2][1]/opit_0/Q
+ net (fanout=1) 0.084 9.140 u_zoom_image/image_valid[2] [1]
+ CLMA_210_153/AD f u_zoom_image/image_valid[3][1]/opit_0/D
+
+ Data arrival time 9.140 Logic Levels: 0
+ Logic: 0.221ns(72.459%), Route: 0.084ns(27.541%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.585 9.440 ntclkbufg_3
+ CLMA_210_153/CLK r u_zoom_image/image_valid[3][1]/opit_0/CLK
+ clock pessimism -0.605 8.835
+ clock uncertainty 0.000 8.835
+
+ Hold time 0.053 8.888
+
+ Data required time 8.888
+----------------------------------------------------------------------------------------------------
+ Data required time 8.888
+ Data arrival time 9.140
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 0.252
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin
Path Group : clk_720p60Hz
Path Type : max (slow corner)
Path Class : sequential timing path
Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 8.831
- Launch Clock Delay : 9.434
- Clock Pessimism Removal : 0.567
+ Capture Clock Delay : 8.952
+ Launch Clock Delay : 9.557
+ Clock Pessimism Removal : 0.569
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -3423,37 +3765,35 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
+ net (fanout=1) 1.861 6.149 ntR3950
PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 1.599 7.849 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.585 9.434 ntclkbufg_2
- CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-
- CLMS_186_117/Q2 tco 0.290 9.724 r u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0
- net (fanout=1) 0.857 10.581 pos_y[7]
- CLMA_186_116/COUT td 0.515 11.096 r udp_osd_inst/N29.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 11.096 udp_osd_inst/N29.co [6]
- CLMA_186_120/Y1 td 0.498 11.594 r udp_osd_inst/N29.eq_4/gateop_A2/Y1
- net (fanout=5) 0.410 12.004 udp_osd_inst/N29
- CLMA_190_120/Y3 td 0.287 12.291 r udp_osd_inst/N69_5/gateop_perm/Z
- net (fanout=2) 0.551 12.842 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64
- CLMA_186_112/Y1 td 0.212 13.054 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z
- net (fanout=2) 0.401 13.455 udp_osd_inst/char_osd_inst/row_pixels_ready
- CLMA_186_108/Y2 td 0.210 13.665 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z
- net (fanout=6) 0.587 14.252 udp_osd_inst/char_osd_inst/char_next
- CLMA_182_88/Y3 td 0.210 14.462 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z
- net (fanout=1) 0.253 14.715 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79
- CLMA_182_88/Y2 td 0.210 14.925 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z
- net (fanout=3) 0.548 15.473 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518
- CLMA_186_80/Y0 td 0.341 15.814 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z
- net (fanout=1) 0.540 16.354 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786
- CLMA_182_73/CECO td 0.170 16.524 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT
- net (fanout=4) 0.000 16.524 ntR2038
- CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE
-
- Data arrival time 16.524 Logic Levels: 9
- Logic: 2.943ns(41.509%), Route: 4.147ns(58.491%)
+ net (fanout=1635) 1.708 9.557 ntclkbufg_2
+ CLMA_214_292/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK
+
+ CLMA_214_292/Q1 tco 0.291 9.848 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/Q1
+ net (fanout=3) 0.549 10.397 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt [5]
+ CLMA_218_284/Y1 td 0.304 10.701 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_20/gateop_perm/Z
+ net (fanout=1) 0.736 11.437 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107752
+ CLMA_214_280/Y1 td 0.468 11.905 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_29/gateop_perm/Z
+ net (fanout=3) 0.268 12.173 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N98274
+ CLMA_214_284/Y1 td 0.212 12.385 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_7/gateop_perm/Z
+ net (fanout=15) 0.990 13.375 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en
+ td 0.474 13.849 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q1/Cout
+ net (fanout=1) 0.000 13.849 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13665
+ CLMS_186_277/COUT td 0.058 13.907 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 13.907 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13667
+ CLMS_186_281/Y1 td 0.498 14.405 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1
+ net (fanout=3) 0.461 14.866 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N84 [5]
+ CLMA_186_292/Y2 td 0.478 15.344 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm/Z
+ net (fanout=1) 0.644 15.988 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rrptr [5]
+ CLMS_190_285/COUT td 0.511 16.499 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.eq_2/gateop_A2/Cout
+ net (fanout=1) 0.000 16.499 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.co [6]
+ CLMS_190_289/CIN r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin
+
+ Data arrival time 16.499 Logic Levels: 7
+ Logic: 3.294ns(47.450%), Route: 3.648ns(52.550%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 13.473 13.473 r
@@ -3466,36 +3806,36 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 17.320 rd3_clk
USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 19.106 ntR3907
+ net (fanout=1) 1.786 19.106 ntR3950
PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 1.571 20.773 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.531 22.304 ntclkbufg_2
- CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK
- clock pessimism 0.567 22.871
- clock uncertainty -0.150 22.721
+ net (fanout=1635) 1.652 22.425 ntclkbufg_2
+ CLMS_190_289/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK
+ clock pessimism 0.569 22.994
+ clock uncertainty -0.150 22.844
- Setup time -0.747 21.974
+ Setup time -0.357 22.487
- Data required time 21.974
+ Data required time 22.487
----------------------------------------------------------------------------------------------------
- Data required time 21.974
- Data arrival time 16.524
+ Data required time 22.487
+ Data arrival time 16.499
----------------------------------------------------------------------------------------------------
- Slack (MET) 5.450
+ Slack (MET) 5.988
====================================================================================================
====================================================================================================
-Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE
+Startpoint : u_sync_vg/pos_x[2]/opit_0/CLK
+Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE
Path Group : clk_720p60Hz
Path Type : max (slow corner)
Path Class : sequential timing path
Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 8.831
- Launch Clock Delay : 9.434
- Clock Pessimism Removal : 0.567
+ Capture Clock Delay : 8.952
+ Launch Clock Delay : 9.557
+ Clock Pessimism Removal : 0.569
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -3510,37 +3850,128 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
+ net (fanout=1) 1.861 6.149 ntR3950
PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 1.599 7.849 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.585 9.434 ntclkbufg_2
- CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-
- CLMS_186_117/Q2 tco 0.290 9.724 r u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0
- net (fanout=1) 0.857 10.581 pos_y[7]
- CLMA_186_116/COUT td 0.515 11.096 r udp_osd_inst/N29.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 11.096 udp_osd_inst/N29.co [6]
- CLMA_186_120/Y1 td 0.498 11.594 r udp_osd_inst/N29.eq_4/gateop_A2/Y1
- net (fanout=5) 0.410 12.004 udp_osd_inst/N29
- CLMA_190_120/Y3 td 0.287 12.291 r udp_osd_inst/N69_5/gateop_perm/Z
- net (fanout=2) 0.551 12.842 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64
- CLMA_186_112/Y1 td 0.212 13.054 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z
- net (fanout=2) 0.401 13.455 udp_osd_inst/char_osd_inst/row_pixels_ready
- CLMA_186_108/Y2 td 0.210 13.665 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z
- net (fanout=6) 0.587 14.252 udp_osd_inst/char_osd_inst/char_next
- CLMA_182_88/Y3 td 0.210 14.462 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z
- net (fanout=1) 0.253 14.715 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79
- CLMA_182_88/Y2 td 0.210 14.925 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z
- net (fanout=3) 0.548 15.473 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518
- CLMA_186_80/Y0 td 0.341 15.814 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z
- net (fanout=1) 0.540 16.354 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786
- CLMA_182_73/CECO td 0.170 16.524 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT
- net (fanout=4) 0.000 16.524 ntR2038
- CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE
-
- Data arrival time 16.524 Logic Levels: 9
- Logic: 2.943ns(41.509%), Route: 4.147ns(58.491%)
+ net (fanout=1635) 1.708 9.557 ntclkbufg_2
+ CLMA_242_252/CLK r u_sync_vg/pos_x[2]/opit_0/CLK
+
+ CLMA_242_252/Q0 tco 0.289 9.846 r u_sync_vg/pos_x[2]/opit_0/Q
+ net (fanout=2) 0.770 10.616 pos_x[2]
+ td 0.326 10.942 f udp_osd_inst/N26.lt_0/gateop_A2/Cout
+ net (fanout=1) 0.000 10.942 udp_osd_inst/N26.co [2]
+ CLMA_230_244/COUT td 0.058 11.000 r udp_osd_inst/N26.lt_2/gateop_A2/Cout
+ net (fanout=1) 0.000 11.000 udp_osd_inst/N26.co [6]
+ CLMA_230_248/Y1 td 0.498 11.498 r udp_osd_inst/N26.lt_4/gateop_A2/Y1
+ net (fanout=4) 0.645 12.143 udp_osd_inst/N26
+ CLMA_250_257/Y2 td 0.210 12.353 r udp_osd_inst/N69_5/gateop_perm/Z
+ net (fanout=2) 0.257 12.610 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64
+ CLMA_250_257/Y3 td 0.210 12.820 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z
+ net (fanout=2) 0.401 13.221 udp_osd_inst/char_osd_inst/row_pixels_ready
+ CLMA_250_261/Y1 td 0.212 13.433 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z
+ net (fanout=12) 0.631 14.064 udp_osd_inst/char_osd_inst/char_next
+ CLMA_246_284/Y2 td 0.210 14.274 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z
+ net (fanout=1) 0.253 14.527 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74
+ CLMA_246_284/Y1 td 0.212 14.739 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z
+ net (fanout=3) 0.403 15.142 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126
+ CLMA_250_284/Y0 td 0.210 15.352 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z
+ net (fanout=1) 0.395 15.747 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786
+ CLMA_254_288/CECO td 0.184 15.931 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT
+ net (fanout=4) 0.000 15.931 ntR2066
+ CLMA_254_292/CECI r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE
+
+ Data arrival time 15.931 Logic Levels: 9
+ Logic: 2.619ns(41.089%), Route: 3.755ns(58.911%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 13.473 13.473 r
+ P20 0.000 13.473 r clk (port)
+ net (fanout=1) 0.074 13.547 clk
+ IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 15.355 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 16.161 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 17.320 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 19.106 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.571 20.773 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.652 22.425 ntclkbufg_2
+ CLMA_254_292/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK
+ clock pessimism 0.569 22.994
+ clock uncertainty -0.150 22.844
+
+ Setup time -0.729 22.115
+
+ Data required time 22.115
+----------------------------------------------------------------------------------------------------
+ Data required time 22.115
+ Data arrival time 15.931
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 6.184
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_sync_vg/pos_x[2]/opit_0/CLK
+Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE
+Path Group : clk_720p60Hz
+Path Type : max (slow corner)
+Path Class : sequential timing path
+Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 8.952
+ Launch Clock Delay : 9.557
+ Clock Pessimism Removal : 0.569
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.599 7.849 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.708 9.557 ntclkbufg_2
+ CLMA_242_252/CLK r u_sync_vg/pos_x[2]/opit_0/CLK
+
+ CLMA_242_252/Q0 tco 0.289 9.846 r u_sync_vg/pos_x[2]/opit_0/Q
+ net (fanout=2) 0.770 10.616 pos_x[2]
+ td 0.326 10.942 f udp_osd_inst/N26.lt_0/gateop_A2/Cout
+ net (fanout=1) 0.000 10.942 udp_osd_inst/N26.co [2]
+ CLMA_230_244/COUT td 0.058 11.000 r udp_osd_inst/N26.lt_2/gateop_A2/Cout
+ net (fanout=1) 0.000 11.000 udp_osd_inst/N26.co [6]
+ CLMA_230_248/Y1 td 0.498 11.498 r udp_osd_inst/N26.lt_4/gateop_A2/Y1
+ net (fanout=4) 0.645 12.143 udp_osd_inst/N26
+ CLMA_250_257/Y2 td 0.210 12.353 r udp_osd_inst/N69_5/gateop_perm/Z
+ net (fanout=2) 0.257 12.610 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64
+ CLMA_250_257/Y3 td 0.210 12.820 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z
+ net (fanout=2) 0.401 13.221 udp_osd_inst/char_osd_inst/row_pixels_ready
+ CLMA_250_261/Y1 td 0.212 13.433 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z
+ net (fanout=12) 0.631 14.064 udp_osd_inst/char_osd_inst/char_next
+ CLMA_246_284/Y2 td 0.210 14.274 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z
+ net (fanout=1) 0.253 14.527 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74
+ CLMA_246_284/Y1 td 0.212 14.739 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z
+ net (fanout=3) 0.403 15.142 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126
+ CLMA_250_284/Y0 td 0.210 15.352 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z
+ net (fanout=1) 0.395 15.747 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786
+ CLMA_254_288/CECO td 0.184 15.931 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT
+ net (fanout=4) 0.000 15.931 ntR2066
+ CLMA_254_292/CECI r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE
+
+ Data arrival time 15.931 Logic Levels: 9
+ Logic: 2.619ns(41.089%), Route: 3.755ns(58.911%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 13.473 13.473 r
@@ -3553,29 +3984,29 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 17.320 rd3_clk
USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 19.106 ntR3907
+ net (fanout=1) 1.786 19.106 ntR3950
PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 1.571 20.773 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.531 22.304 ntclkbufg_2
- CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CLK
- clock pessimism 0.567 22.871
- clock uncertainty -0.150 22.721
+ net (fanout=1635) 1.652 22.425 ntclkbufg_2
+ CLMA_254_292/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK
+ clock pessimism 0.569 22.994
+ clock uncertainty -0.150 22.844
- Setup time -0.747 21.974
+ Setup time -0.729 22.115
- Data required time 21.974
+ Data required time 22.115
----------------------------------------------------------------------------------------------------
- Data required time 21.974
- Data arrival time 16.524
+ Data required time 22.115
+ Data arrival time 15.931
----------------------------------------------------------------------------------------------------
- Slack (MET) 5.450
+ Slack (MET) 6.184
====================================================================================================
====================================================================================================
-Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK
-Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4
+Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK
+Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4
Path Group : clk_720p60Hz
Path Type : min (slow corner)
Path Class : sequential timing path
@@ -3597,16 +4028,16 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 5.633 ntR3907
+ net (fanout=1) 1.786 5.633 ntR3950
PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 1.571 7.300 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT
net (fanout=1635) 1.531 8.831 ntclkbufg_2
- CLMA_266_132/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK
+ CLMA_250_177/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK
- CLMA_266_132/Q1 tco 0.224 9.055 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/Q
- net (fanout=1) 0.084 9.139 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[4] [1]
- CLMS_266_133/C4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4
+ CLMA_250_177/Q2 tco 0.224 9.055 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/Q
+ net (fanout=1) 0.084 9.139 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/dividend_t[13] [9]
+ CLMA_250_176/A4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4
Data arrival time 9.139 Logic Levels: 0
Logic: 0.224ns(72.727%), Route: 0.084ns(27.273%)
@@ -3622,36 +4053,36 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
+ net (fanout=1) 1.861 6.149 ntR3950
PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 1.599 7.849 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
net (fanout=1635) 1.585 9.434 ntclkbufg_2
- CLMS_266_133/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/CLK
+ CLMA_250_176/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK
clock pessimism -0.574 8.860
clock uncertainty 0.000 8.860
- Hold time -0.034 8.826
+ Hold time -0.035 8.825
- Data required time 8.826
+ Data required time 8.825
----------------------------------------------------------------------------------------------------
- Data required time 8.826
+ Data required time 8.825
Data arrival time 9.139
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.313
+ Slack (MET) 0.314
====================================================================================================
====================================================================================================
-Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK
-Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4
+Startpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK
+Endpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04
Path Group : clk_720p60Hz
Path Type : min (slow corner)
Path Class : sequential timing path
Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 9.434
- Launch Clock Delay : 8.831
- Clock Pessimism Removal : -0.574
+ Capture Clock Delay : 9.557
+ Launch Clock Delay : 8.952
+ Clock Pessimism Removal : -0.576
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -3666,19 +4097,19 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 5.633 ntR3907
+ net (fanout=1) 1.786 5.633 ntR3950
PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 1.571 7.300 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.531 8.831 ntclkbufg_2
- CLMA_262_132/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK
+ net (fanout=1635) 1.652 8.952 ntclkbufg_2
+ CLMA_230_280/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK
- CLMA_262_132/Q2 tco 0.224 9.055 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/Q
- net (fanout=1) 0.084 9.139 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[1] [3]
- CLMS_262_133/A4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4
+ CLMA_230_280/Q1 tco 0.224 9.176 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1
+ net (fanout=2) 0.085 9.261 udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3]
+ CLMA_230_281/C4 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04
- Data arrival time 9.139 Logic Levels: 0
- Logic: 0.224ns(72.727%), Route: 0.084ns(27.273%)
+ Data arrival time 9.261 Logic Levels: 0
+ Logic: 0.224ns(72.492%), Route: 0.085ns(27.508%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 0.000 0.000 r
@@ -3691,36 +4122,36 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
+ net (fanout=1) 1.861 6.149 ntR3950
PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 1.599 7.849 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.585 9.434 ntclkbufg_2
- CLMS_262_133/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/CLK
- clock pessimism -0.574 8.860
- clock uncertainty 0.000 8.860
+ net (fanout=1635) 1.708 9.557 ntclkbufg_2
+ CLMA_230_281/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK
+ clock pessimism -0.576 8.981
+ clock uncertainty 0.000 8.981
- Hold time -0.035 8.825
+ Hold time -0.034 8.947
- Data required time 8.825
+ Data required time 8.947
----------------------------------------------------------------------------------------------------
- Data required time 8.825
- Data arrival time 9.139
+ Data required time 8.947
+ Data arrival time 9.261
----------------------------------------------------------------------------------------------------
Slack (MET) 0.314
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK
-Endpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04
+Startpoint : u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK
+Endpoint : u_sync_vg/pos_y[4]/opit_0_A2Q21/I04
Path Group : clk_720p60Hz
Path Type : min (slow corner)
Path Class : sequential timing path
Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 9.434
- Launch Clock Delay : 8.831
- Clock Pessimism Removal : -0.574
+ Capture Clock Delay : 9.557
+ Launch Clock Delay : 8.952
+ Clock Pessimism Removal : -0.576
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -3735,19 +4166,19 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 5.633 ntR3907
+ net (fanout=1) 1.786 5.633 ntR3950
PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 1.571 7.300 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.531 8.831 ntclkbufg_2
- CLMA_174_52/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK
+ net (fanout=1635) 1.652 8.952 ntclkbufg_2
+ CLMS_246_253/CLK r u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK
- CLMA_174_52/Q1 tco 0.224 9.055 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1
- net (fanout=2) 0.085 9.140 udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3]
- CLMS_174_53/C4 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04
+ CLMS_246_253/Q1 tco 0.224 9.176 f u_sync_vg/v_count[3]/opit_0_L5Q_perm/Q
+ net (fanout=7) 0.089 9.265 u_sync_vg/v_count [3]
+ CLMA_246_252/C4 f u_sync_vg/pos_y[4]/opit_0_A2Q21/I04
- Data arrival time 9.140 Logic Levels: 0
- Logic: 0.224ns(72.492%), Route: 0.085ns(27.508%)
+ Data arrival time 9.265 Logic Levels: 0
+ Logic: 0.224ns(71.565%), Route: 0.089ns(28.435%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 0.000 0.000 r
@@ -3760,36 +4191,36 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
+ net (fanout=1) 1.861 6.149 ntR3950
PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 1.599 7.849 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.585 9.434 ntclkbufg_2
- CLMS_174_53/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK
- clock pessimism -0.574 8.860
- clock uncertainty 0.000 8.860
+ net (fanout=1635) 1.708 9.557 ntclkbufg_2
+ CLMA_246_252/CLK r u_sync_vg/pos_y[4]/opit_0_A2Q21/CLK
+ clock pessimism -0.576 8.981
+ clock uncertainty 0.000 8.981
- Hold time -0.034 8.826
+ Hold time -0.034 8.947
- Data required time 8.826
+ Data required time 8.947
----------------------------------------------------------------------------------------------------
- Data required time 8.826
- Data arrival time 9.140
+ Data required time 8.947
+ Data arrival time 9.265
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.314
+ Slack (MET) 0.318
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
-Endpoint : u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
+Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
+Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
Path Group : clk_20k
Path Type : max (slow corner)
Path Class : sequential timing path
Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 9.014
- Launch Clock Delay : 9.812
- Clock Pessimism Removal : 0.762
+ Capture Clock Delay : 9.367
+ Launch Clock Delay : 10.251
+ Clock Pessimism Removal : 0.848
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -3803,26 +4234,26 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 2.059 8.227 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 8.227 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.585 9.812 u_ov5640/coms2_reg_config/clock_20k
- DRM_178_24/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
-
- DRM_178_24/QB0[5] tco 2.286 12.098 r u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5]
- net (fanout=1) 0.543 12.641 u_ov5640/coms2_reg_config/i2c_data [21]
- CLMA_174_32/Y3 td 0.459 13.100 r u_ov5640/coms2_reg_config/u1/N267_29/gateop/F
- net (fanout=1) 0.407 13.507 u_ov5640/coms2_reg_config/u1/_N25904
- CLMS_174_29/Y2 td 0.210 13.717 r u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z
- net (fanout=1) 0.259 13.976 u_ov5640/coms2_reg_config/u1/_N25910
- CLMS_174_29/Y1 td 0.274 14.250 r u_ov5640/coms2_reg_config/u1/N267_36/gateop/F
- net (fanout=1) 0.263 14.513 u_ov5640/coms2_reg_config/u1/_N25911
- CLMS_174_25/DD r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
-
- Data arrival time 14.513 Logic Levels: 3
- Logic: 3.229ns(68.688%), Route: 1.472ns(31.312%)
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.498 8.666 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 8.666 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.585 10.251 u_ov5640/coms1_reg_config/clock_20k
+ DRM_142_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
+
+ DRM_142_4/QB0[6] tco 2.286 12.537 r u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6]
+ net (fanout=1) 0.573 13.110 u_ov5640/coms1_reg_config/i2c_data [22]
+ CLMA_146_12/Y1 td 0.460 13.570 r u_ov5640/coms1_reg_config/u1/N267_29/gateop/F
+ net (fanout=1) 0.580 14.150 u_ov5640/coms1_reg_config/u1/_N25311
+ CLMA_138_16/Y0 td 0.210 14.360 r u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z
+ net (fanout=1) 0.256 14.616 u_ov5640/coms1_reg_config/u1/_N25317
+ CLMA_138_16/Y2 td 0.295 14.911 r u_ov5640/coms1_reg_config/u1/N267_36/gateop/F
+ net (fanout=1) 0.447 15.358 u_ov5640/coms1_reg_config/u1/_N25318
+ CLMA_138_9/AD r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
+
+ Data arrival time 15.358 Logic Levels: 3
+ Logic: 3.251ns(63.658%), Route: 1.856ns(36.342%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 50000.000 50000.000 r
@@ -3834,36 +4265,36 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.758 50002.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 50002.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 50003.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 50005.383 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.229 50005.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.871 50007.483 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 50007.483 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.531 50009.014 u_ov5640/coms2_reg_config/clock_20k
- CLMS_174_25/CLK r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK
- clock pessimism 0.762 50009.776
- clock uncertainty -0.050 50009.726
+ USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 50005.383 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.229 50005.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.224 50007.836 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 50007.836 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.531 50009.367 u_ov5640/coms1_reg_config/clock_20k
+ CLMA_138_9/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK
+ clock pessimism 0.848 50010.215
+ clock uncertainty -0.050 50010.165
- Setup time -0.165 50009.561
+ Setup time -0.196 50009.969
- Data required time 50009.561
+ Data required time 50009.969
----------------------------------------------------------------------------------------------------
- Data required time 50009.561
- Data arrival time 14.513
+ Data required time 50009.969
+ Data arrival time 15.358
----------------------------------------------------------------------------------------------------
- Slack (MET) 49995.048
+ Slack (MET) 49994.611
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
-Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
+Startpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
+Endpoint : u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4
Path Group : clk_20k
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 9.247
- Launch Clock Delay : 10.099
+Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 9.258
+ Launch Clock Delay : 10.167
Clock Pessimism Removal : 0.816
Location Delay Type Incr Path Logical Resource
@@ -3878,26 +4309,26 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 2.346 8.514 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 8.514 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.585 10.099 u_ov5640/coms1_reg_config/clock_20k
- DRM_178_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
-
- DRM_178_4/QB0[6] tco 2.307 12.406 f u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6]
- net (fanout=1) 0.619 13.025 u_ov5640/coms1_reg_config/i2c_data [22]
- CLMS_174_9/Y2 td 0.478 13.503 r u_ov5640/coms1_reg_config/u1/N267_29/gateop/F
- net (fanout=1) 0.119 13.622 u_ov5640/coms1_reg_config/u1/_N25461
- CLMA_174_8/Y0 td 0.210 13.832 r u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z
- net (fanout=1) 0.120 13.952 u_ov5640/coms1_reg_config/u1/_N25467
- CLMA_174_8/Y1 td 0.274 14.226 r u_ov5640/coms1_reg_config/u1/N267_36/gateop/F
- net (fanout=1) 0.444 14.670 u_ov5640/coms1_reg_config/u1/_N25468
- CLMA_174_16/DD r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
-
- Data arrival time 14.670 Logic Levels: 3
- Logic: 3.269ns(71.516%), Route: 1.302ns(28.484%)
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMA_122_12/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.357 8.525 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ USCM_84_121/CLK_USCM td 0.000 8.525 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.642 10.167 u_ov5640/coms2_reg_config/clock_20k
+ DRM_82_4/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
+
+ DRM_82_4/QB0[5] tco 2.286 12.453 r u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5]
+ net (fanout=1) 0.501 12.954 u_ov5640/coms2_reg_config/i2c_data [21]
+ CLMS_78_9/Y1 td 0.460 13.414 r u_ov5640/coms2_reg_config/u1/N267_29/gateop/F
+ net (fanout=1) 0.612 14.026 u_ov5640/coms2_reg_config/u1/_N25853
+ CLMA_90_12/Y2 td 0.210 14.236 r u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z
+ net (fanout=1) 0.257 14.493 u_ov5640/coms2_reg_config/u1/_N25859
+ CLMA_90_12/Y6AB td 0.259 14.752 r u_ov5640/coms2_reg_config/u1/N267_37_muxf6/F
+ net (fanout=1) 0.258 15.010 u_ov5640/coms2_reg_config/u1/N267
+ CLMA_90_13/A4 r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4
+
+ Data arrival time 15.010 Logic Levels: 3
+ Logic: 3.215ns(66.384%), Route: 1.628ns(33.616%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 50000.000 50000.000 r
@@ -3909,37 +4340,37 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.758 50002.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 50002.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 50003.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 50005.383 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.229 50005.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 2.104 50007.716 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 50007.716 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.531 50009.247 u_ov5640/coms1_reg_config/clock_20k
- CLMA_174_16/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK
- clock pessimism 0.816 50010.063
- clock uncertainty -0.050 50010.013
+ USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 50005.383 ntclkbufg_8
+ CLMA_122_12/Q1 tco 0.229 50005.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.115 50007.727 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ USCM_84_121/CLK_USCM td 0.000 50007.727 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.531 50009.258 u_ov5640/coms2_reg_config/clock_20k
+ CLMA_90_13/CLK r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.816 50010.074
+ clock uncertainty -0.050 50010.024
- Setup time -0.165 50009.848
+ Setup time -0.121 50009.903
- Data required time 50009.848
+ Data required time 50009.903
----------------------------------------------------------------------------------------------------
- Data required time 50009.848
- Data arrival time 14.670
+ Data required time 50009.903
+ Data arrival time 15.010
----------------------------------------------------------------------------------------------------
- Slack (MET) 49995.178
+ Slack (MET) 49994.893
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/reg_index[2]/opit_0_inv_A2Q21/CLK
-Endpoint : u_ov5640/coms1_reg_config/reg_index[6]/opit_0_inv_A2Q21/CE
+Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
+Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3
Path Group : clk_20k
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 9.247
- Launch Clock Delay : 10.099
- Clock Pessimism Removal : 0.823
+Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 9.367
+ Launch Clock Delay : 10.251
+ Clock Pessimism Removal : 0.848
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -3953,30 +4384,22 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 2.346 8.514 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 8.514 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.585 10.099 u_ov5640/coms1_reg_config/clock_20k
- CLMS_174_13/CLK r u_ov5640/coms1_reg_config/reg_index[2]/opit_0_inv_A2Q21/CLK
-
- CLMS_174_13/Q0 tco 0.289 10.388 r u_ov5640/coms1_reg_config/reg_index[2]/opit_0_inv_A2Q21/Q0
- net (fanout=5) 0.475 10.863 u_ov5640/coms1_reg_config/reg_index [1]
- CLMA_182_13/Y1 td 0.304 11.167 r u_ov5640/coms1_reg_config/N26_mux2/gateop_perm/Z
- net (fanout=1) 0.730 11.897 u_ov5640/coms1_reg_config/_N9682
- CLMS_174_9/Y3 td 0.210 12.107 r u_ov5640/coms1_reg_config/N26_mux6_3/gateop_perm/Z
- net (fanout=2) 0.557 12.664 u_ov5640/coms1_reg_config/_N9690
- CLMS_174_21/Y2 td 0.210 12.874 r u_ov5640/coms1_reg_config/N1134_1/gateop_perm/Z
- net (fanout=4) 0.123 12.997 u_ov5640/coms1_reg_config/_N96528
- CLMS_174_21/Y0 td 0.487 13.484 r u_ov5640/coms1_reg_config/N1169/gateop_perm/Z
- net (fanout=3) 0.413 13.897 u_ov5640/coms1_reg_config/N1169
- CLMS_174_13/CECO td 0.184 14.081 r u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/CEOUT
- net (fanout=2) 0.000 14.081 ntR1983
- CLMS_174_17/CECI r u_ov5640/coms1_reg_config/reg_index[6]/opit_0_inv_A2Q21/CE
-
- Data arrival time 14.081 Logic Levels: 5
- Logic: 1.684ns(42.290%), Route: 2.298ns(57.710%)
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.498 8.666 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 8.666 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.585 10.251 u_ov5640/coms1_reg_config/clock_20k
+ DRM_142_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
+
+ DRM_142_4/QA0[9] tco 2.331 12.582 r u_ov5640/coms1_reg_config/reg_data/iGopDrm/QA0[9]
+ net (fanout=1) 0.664 13.246 u_ov5640/coms1_reg_config/i2c_data [8]
+ CLMA_146_8/Y1 td 0.603 13.849 r u_ov5640/coms1_reg_config/u1/N267_18_muxf7/F
+ net (fanout=1) 0.585 14.434 u_ov5640/coms1_reg_config/u1/_N25300
+ CLMA_138_9/A0 r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3
+
+ Data arrival time 14.434 Logic Levels: 1
+ Logic: 2.934ns(70.141%), Route: 1.249ns(29.859%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 50000.000 50000.000 r
@@ -3988,37 +4411,37 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.758 50002.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 50002.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 50003.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 50005.383 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.229 50005.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 2.104 50007.716 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 50007.716 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.531 50009.247 u_ov5640/coms1_reg_config/clock_20k
- CLMS_174_17/CLK r u_ov5640/coms1_reg_config/reg_index[6]/opit_0_inv_A2Q21/CLK
- clock pessimism 0.823 50010.070
- clock uncertainty -0.050 50010.020
+ USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 50005.383 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.229 50005.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.224 50007.836 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 50007.836 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.531 50009.367 u_ov5640/coms1_reg_config/clock_20k
+ CLMA_138_9/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK
+ clock pessimism 0.848 50010.215
+ clock uncertainty -0.050 50010.165
- Setup time -0.729 50009.291
+ Setup time -0.194 50009.971
- Data required time 50009.291
+ Data required time 50009.971
----------------------------------------------------------------------------------------------------
- Data required time 50009.291
- Data arrival time 14.081
+ Data required time 50009.971
+ Data arrival time 14.434
----------------------------------------------------------------------------------------------------
- Slack (MET) 49995.210
+ Slack (MET) 49995.537
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5]
+Startpoint : u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21/I00
Path Group : clk_20k
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 10.099
- Launch Clock Delay : 9.247
- Clock Pessimism Removal : -0.816
+Clock Skew : 0.031 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 10.147
+ Launch Clock Delay : 9.293
+ Clock Pessimism Removal : -0.823
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -4032,20 +4455,20 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 3.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 5.383 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.229 5.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 2.104 7.716 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 7.716 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.531 9.247 u_ov5640/coms1_reg_config/clock_20k
- CLMA_182_13/CLK r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
+ USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 5.383 ntclkbufg_8
+ CLMA_122_12/Q1 tco 0.229 5.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.115 7.727 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ USCM_84_121/CLK_USCM td 0.000 7.727 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.566 9.293 u_ov5640/coms2_reg_config/clock_20k
+ CLMA_78_12/CLK r u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
- CLMA_182_13/Q0 tco 0.222 9.469 f u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q
- net (fanout=6) 0.351 9.820 u_ov5640/coms1_reg_config/reg_index [0]
- DRM_178_4/ADA0[5] f u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5]
+ CLMA_78_12/Q0 tco 0.222 9.515 f u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q
+ net (fanout=6) 0.087 9.602 u_ov5640/coms2_reg_config/reg_index [0]
+ CLMS_78_13/A0 f u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21/I00
- Data arrival time 9.820 Logic Levels: 0
- Logic: 0.222ns(38.743%), Route: 0.351ns(61.257%)
+ Data arrival time 9.602 Logic Levels: 0
+ Logic: 0.222ns(71.845%), Route: 0.087ns(28.155%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 0.000 0.000 r
@@ -4057,37 +4480,37 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 2.346 8.514 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 8.514 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.585 10.099 u_ov5640/coms1_reg_config/clock_20k
- DRM_178_4/CLKA[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
- clock pessimism -0.816 9.283
- clock uncertainty 0.000 9.283
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMA_122_12/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.357 8.525 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ USCM_84_121/CLK_USCM td 0.000 8.525 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.622 10.147 u_ov5640/coms2_reg_config/clock_20k
+ CLMS_78_13/CLK r u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21/CLK
+ clock pessimism -0.823 9.324
+ clock uncertainty 0.000 9.324
- Hold time 0.161 9.444
+ Hold time -0.094 9.230
- Data required time 9.444
+ Data required time 9.230
----------------------------------------------------------------------------------------------------
- Data required time 9.444
- Data arrival time 9.820
+ Data required time 9.230
+ Data arrival time 9.602
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.376
+ Slack (MET) 0.372
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5]
+Startpoint : u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5]
Path Group : clk_20k
Path Type : min (slow corner)
Path Class : sequential timing path
Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 9.812
- Launch Clock Delay : 9.014
- Clock Pessimism Removal : -0.762
+ Capture Clock Delay : 10.251
+ Launch Clock Delay : 9.367
+ Clock Pessimism Removal : -0.848
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -4101,20 +4524,20 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 3.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 5.383 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.229 5.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.871 7.483 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 7.483 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.531 9.014 u_ov5640/coms2_reg_config/clock_20k
- CLMA_182_32/CLK r u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
+ USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 5.383 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.229 5.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.224 7.836 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 7.836 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.531 9.367 u_ov5640/coms1_reg_config/clock_20k
+ CLMA_146_12/CLK r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
- CLMA_182_32/Q0 tco 0.222 9.236 f u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q
- net (fanout=6) 0.353 9.589 u_ov5640/coms2_reg_config/reg_index [0]
- DRM_178_24/ADA0[5] f u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5]
+ CLMA_146_12/Q0 tco 0.222 9.589 f u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q
+ net (fanout=6) 0.359 9.948 u_ov5640/coms1_reg_config/reg_index [0]
+ DRM_142_4/ADA0[5] f u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5]
- Data arrival time 9.589 Logic Levels: 0
- Logic: 0.222ns(38.609%), Route: 0.353ns(61.391%)
+ Data arrival time 9.948 Logic Levels: 0
+ Logic: 0.222ns(38.210%), Route: 0.359ns(61.790%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 0.000 0.000 r
@@ -4126,37 +4549,37 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 2.059 8.227 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 8.227 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.585 9.812 u_ov5640/coms2_reg_config/clock_20k
- DRM_178_24/CLKA[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKA[0]
- clock pessimism -0.762 9.050
- clock uncertainty 0.000 9.050
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.498 8.666 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 8.666 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.585 10.251 u_ov5640/coms1_reg_config/clock_20k
+ DRM_142_4/CLKA[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
+ clock pessimism -0.848 9.403
+ clock uncertainty 0.000 9.403
- Hold time 0.161 9.211
+ Hold time 0.161 9.564
- Data required time 9.211
+ Data required time 9.564
----------------------------------------------------------------------------------------------------
- Data required time 9.211
- Data arrival time 9.589
+ Data required time 9.564
+ Data arrival time 9.948
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.378
+ Slack (MET) 0.384
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/L0
+Startpoint : u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/L0
Path Group : clk_20k
Path Type : min (slow corner)
Path Class : sequential timing path
Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 9.812
- Launch Clock Delay : 9.014
- Clock Pessimism Removal : -0.798
+ Capture Clock Delay : 10.251
+ Launch Clock Delay : 9.367
+ Clock Pessimism Removal : -0.884
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -4170,20 +4593,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.059 3.852 clk_25m
- USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.531 5.383 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.229 5.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.871 7.483 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 7.483 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.531 9.014 u_ov5640/coms2_reg_config/clock_20k
- CLMS_174_25/CLK r u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/CLK
+ USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.531 5.383 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.229 5.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.224 7.836 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 7.836 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.531 9.367 u_ov5640/coms1_reg_config/clock_20k
+ CLMA_134_12/CLK r u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/CLK
- CLMS_174_25/Q0 tco 0.222 9.236 f u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/Q
- net (fanout=2) 0.085 9.321 u_ov5640/coms2_reg_config/u1/sclk
- CLMS_174_25/A0 f u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/L0
+ CLMA_134_12/Q0 tco 0.222 9.589 f u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/Q
+ net (fanout=3) 0.086 9.675 u_ov5640/coms1_reg_config/tr_end
+ CLMA_134_12/A0 f u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/L0
- Data arrival time 9.321 Logic Levels: 0
- Logic: 0.222ns(72.313%), Route: 0.085ns(27.687%)
+ Data arrival time 9.675 Logic Levels: 0
+ Logic: 0.222ns(72.078%), Route: 0.086ns(27.922%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 0.000 0.000 r
@@ -4195,37 +4618,37 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 1.078 4.292 clk_25m
- USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 1.585 5.877 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 2.059 8.227 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 8.227 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 1.585 9.812 u_ov5640/coms2_reg_config/clock_20k
- CLMS_174_25/CLK r u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/CLK
- clock pessimism -0.798 9.014
- clock uncertainty 0.000 9.014
+ USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 1.585 5.877 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 2.498 8.666 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 8.666 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 1.585 10.251 u_ov5640/coms1_reg_config/clock_20k
+ CLMA_134_12/CLK r u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/CLK
+ clock pessimism -0.884 9.367
+ clock uncertainty 0.000 9.367
- Hold time -0.094 8.920
+ Hold time -0.094 9.273
- Data required time 8.920
+ Data required time 9.273
----------------------------------------------------------------------------------------------------
- Data required time 8.920
- Data arrival time 9.321
+ Data required time 9.273
+ Data arrival time 9.675
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.401
+ Slack (MET) 0.402
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0
Path Group : ddrphy_clkin
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 10.665
Launch Clock Delay : 11.394
- Clock Pessimism Removal : 0.675
+ Clock Pessimism Removal : 0.693
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -4238,41 +4661,41 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK
-
- CLMA_22_124/Q2 tco 0.289 11.683 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/Q
- net (fanout=5) 1.236 12.919 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [6]
- CLMA_30_168/Y3 td 0.210 13.129 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
- net (fanout=2) 0.407 13.536 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
- td 0.477 14.013 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 14.013 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
- CLMA_34_168/Y2 td 0.271 14.284 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0
- net (fanout=1) 0.554 14.838 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2]
- CLMA_30_160/Y3 td 0.210 15.048 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z
- net (fanout=4) 0.690 15.738 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2]
- CLMA_30_172/COUT td 0.502 16.240 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
- net (fanout=1) 0.000 16.240 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576
- CLMA_30_176/Y0 td 0.269 16.509 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
- net (fanout=4) 1.536 18.045 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
- CLMA_30_248/Y0 td 0.487 18.532 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z
- net (fanout=40) 0.995 19.527 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196
- CLMS_38_245/Y1 td 0.468 19.995 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[2]/gateop/F
- net (fanout=1) 0.470 20.465 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24359
- CLMS_22_245/D3 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
-
- Data arrival time 20.465 Logic Levels: 7
- Logic: 3.183ns(35.090%), Route: 5.888ns(64.910%)
+ CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_10_133/Q2 tco 0.290 11.684 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q
+ net (fanout=5) 0.687 12.371 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2]
+ CLMS_18_149/Y1 td 0.288 12.659 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
+ net (fanout=2) 0.402 13.061 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
+ td 0.477 13.538 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
+ net (fanout=1) 0.000 13.538 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
+ CLMS_18_145/Y3 td 0.501 14.039 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1
+ net (fanout=1) 0.661 14.700 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3]
+ CLMS_46_145/Y1 td 0.304 15.004 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z
+ net (fanout=4) 0.406 15.410 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3]
+ CLMA_50_144/COUT td 0.507 15.917 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
+ net (fanout=1) 0.000 15.917 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534
+ CLMA_50_148/Y0 td 0.269 16.186 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
+ net (fanout=4) 0.267 16.453 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
+ CLMS_46_149/Y0 td 0.285 16.738 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z
+ net (fanout=40) 0.720 17.458 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975
+ CLMA_62_164/Y2 td 0.478 17.936 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[12]/gateop/F
+ net (fanout=1) 0.402 18.338 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24148
+ CLMA_58_161/C3 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0
+
+ Data arrival time 18.338 Logic Levels: 7
+ Logic: 3.399ns(48.949%), Route: 3.545ns(51.051%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -4283,42 +4706,42 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 12.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 13.843 zoom_clk
+ net (fanout=2) 1.059 13.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 16.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 16.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.531 20.665 ntclkbufg_0
- CLMS_22_245/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK
- clock pessimism 0.675 21.340
- clock uncertainty -0.150 21.190
+ CLMA_58_161/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK
+ clock pessimism 0.693 21.358
+ clock uncertainty -0.150 21.208
- Setup time -0.377 20.813
+ Setup time -0.398 20.810
- Data required time 20.813
+ Data required time 20.810
----------------------------------------------------------------------------------------------------
- Data required time 20.813
- Data arrival time 20.465
+ Data required time 20.810
+ Data arrival time 18.338
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.348
+ Slack (MET) 2.472
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/I2
Path Group : ddrphy_clkin
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 10.786
+Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 10.665
Launch Clock Delay : 11.394
- Clock Pessimism Removal : 0.675
+ Clock Pessimism Removal : 0.693
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -4331,41 +4754,41 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK
-
- CLMA_22_124/Q2 tco 0.289 11.683 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/Q
- net (fanout=5) 1.236 12.919 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [6]
- CLMA_30_168/Y3 td 0.210 13.129 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
- net (fanout=2) 0.407 13.536 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
- td 0.477 14.013 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 14.013 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
- CLMA_34_168/Y2 td 0.271 14.284 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0
- net (fanout=1) 0.554 14.838 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2]
- CLMA_30_160/Y3 td 0.210 15.048 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z
- net (fanout=4) 0.690 15.738 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2]
- CLMA_30_172/COUT td 0.502 16.240 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
- net (fanout=1) 0.000 16.240 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576
- CLMA_30_176/Y0 td 0.269 16.509 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
- net (fanout=4) 1.536 18.045 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
- CLMA_30_248/Y0 td 0.493 18.538 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z
- net (fanout=40) 0.749 19.287 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196
- CLMA_34_268/Y3 td 0.468 19.755 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[10]/gateop/F
- net (fanout=1) 0.768 20.523 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24367
- CLMS_22_265/B3 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
-
- Data arrival time 20.523 Logic Levels: 7
- Logic: 3.189ns(34.933%), Route: 5.940ns(65.067%)
+ CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_10_133/Q2 tco 0.290 11.684 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q
+ net (fanout=5) 0.687 12.371 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2]
+ CLMS_18_149/Y1 td 0.288 12.659 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
+ net (fanout=2) 0.402 13.061 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
+ td 0.477 13.538 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
+ net (fanout=1) 0.000 13.538 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
+ CLMS_18_145/Y3 td 0.501 14.039 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1
+ net (fanout=1) 0.661 14.700 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3]
+ CLMS_46_145/Y1 td 0.304 15.004 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z
+ net (fanout=4) 0.406 15.410 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3]
+ CLMA_50_144/COUT td 0.507 15.917 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
+ net (fanout=1) 0.000 15.917 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534
+ CLMA_50_148/Y0 td 0.269 16.186 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
+ net (fanout=4) 0.406 16.592 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
+ CLMS_46_145/Y0 td 0.285 16.877 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/gateop_perm/Z
+ net (fanout=56) 0.635 17.512 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906
+ CLMS_50_157/Y2 td 0.210 17.722 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[15]/gateop_perm/Z
+ net (fanout=1) 0.581 18.303 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23991
+ CLMA_58_156/C2 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/I2
+
+ Data arrival time 18.303 Logic Levels: 7
+ Logic: 3.131ns(45.318%), Route: 3.778ns(54.682%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -4376,42 +4799,42 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 12.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 13.843 zoom_clk
+ net (fanout=2) 1.059 13.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 16.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 16.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.652 20.786 ntclkbufg_0
- CLMS_22_265/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK
- clock pessimism 0.675 21.461
- clock uncertainty -0.150 21.311
+ net (fanout=5464) 1.531 20.665 ntclkbufg_0
+ CLMA_58_156/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK
+ clock pessimism 0.693 21.358
+ clock uncertainty -0.150 21.208
- Setup time -0.377 20.934
+ Setup time -0.391 20.817
- Data required time 20.934
+ Data required time 20.817
----------------------------------------------------------------------------------------------------
- Data required time 20.934
- Data arrival time 20.523
+ Data required time 20.817
+ Data arrival time 18.303
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.411
+ Slack (MET) 2.514
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/I2
Path Group : ddrphy_clkin
Path Type : max (slow corner)
Path Class : sequential timing path
-Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 10.665
Launch Clock Delay : 11.394
- Clock Pessimism Removal : 0.675
+ Clock Pessimism Removal : 0.693
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -4424,41 +4847,41 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK
-
- CLMA_22_124/Q2 tco 0.289 11.683 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/Q
- net (fanout=5) 1.236 12.919 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [6]
- CLMA_30_168/Y3 td 0.210 13.129 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
- net (fanout=2) 0.407 13.536 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
- td 0.477 14.013 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 14.013 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
- CLMA_34_168/Y2 td 0.271 14.284 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0
- net (fanout=1) 0.554 14.838 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2]
- CLMA_30_160/Y3 td 0.210 15.048 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z
- net (fanout=4) 0.690 15.738 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2]
- CLMA_30_172/COUT td 0.502 16.240 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
- net (fanout=1) 0.000 16.240 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576
- CLMA_30_176/Y0 td 0.269 16.509 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
- net (fanout=4) 1.536 18.045 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
- CLMA_30_248/Y0 td 0.493 18.538 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z
- net (fanout=40) 0.731 19.269 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196
- CLMA_30_248/Y1 td 0.468 19.737 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[0]/gateop/F
- net (fanout=1) 0.638 20.375 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24357
- CLMS_22_245/A3 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0
-
- Data arrival time 20.375 Logic Levels: 7
- Logic: 3.189ns(35.508%), Route: 5.792ns(64.492%)
+ CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_10_133/Q2 tco 0.290 11.684 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q
+ net (fanout=5) 0.687 12.371 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2]
+ CLMS_18_149/Y1 td 0.288 12.659 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
+ net (fanout=2) 0.402 13.061 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
+ td 0.477 13.538 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
+ net (fanout=1) 0.000 13.538 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
+ CLMS_18_145/Y3 td 0.501 14.039 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1
+ net (fanout=1) 0.661 14.700 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3]
+ CLMS_46_145/Y1 td 0.304 15.004 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z
+ net (fanout=4) 0.406 15.410 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3]
+ CLMA_50_144/COUT td 0.507 15.917 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
+ net (fanout=1) 0.000 15.917 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534
+ CLMA_50_148/Y0 td 0.269 16.186 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
+ net (fanout=4) 0.406 16.592 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
+ CLMS_46_145/Y0 td 0.294 16.886 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/gateop_perm/Z
+ net (fanout=56) 0.643 17.529 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906
+ CLMA_62_160/Y3 td 0.210 17.739 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[14]/gateop_perm/Z
+ net (fanout=1) 0.554 18.293 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23990
+ CLMA_58_161/A2 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/I2
+
+ Data arrival time 18.293 Logic Levels: 7
+ Logic: 3.140ns(45.514%), Route: 3.759ns(54.486%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -4469,42 +4892,42 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 12.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 13.843 zoom_clk
+ net (fanout=2) 1.059 13.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 16.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 16.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.531 20.665 ntclkbufg_0
- CLMS_22_245/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK
- clock pessimism 0.675 21.340
- clock uncertainty -0.150 21.190
+ CLMA_58_161/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK
+ clock pessimism 0.693 21.358
+ clock uncertainty -0.150 21.208
- Setup time -0.397 20.793
+ Setup time -0.388 20.820
- Data required time 20.793
+ Data required time 20.820
----------------------------------------------------------------------------------------------------
- Data required time 20.793
- Data arrival time 20.375
+ Data required time 20.820
+ Data arrival time 18.293
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.418
+ Slack (MET) 2.527
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WD
Path Group : ddrphy_clkin
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 11.394
Launch Clock Delay : 10.665
- Clock Pessimism Removal : -0.675
+ Clock Pessimism Removal : -0.693
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -4517,25 +4940,25 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 6.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.531 10.665 ntclkbufg_0
- CLMA_58_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK
+ CLMA_50_96/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/CLK
- CLMA_58_124/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/Q
- net (fanout=2) 0.361 11.248 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [22]
- CLMS_50_129/DD f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD
+ CLMA_50_96/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/Q
+ net (fanout=2) 0.355 11.242 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [16]
+ CLMS_34_97/AD f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WD
- Data arrival time 11.248 Logic Levels: 0
- Logic: 0.222ns(38.079%), Route: 0.361ns(61.921%)
+ Data arrival time 11.242 Logic Levels: 0
+ Logic: 0.222ns(38.475%), Route: 0.355ns(61.525%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -4546,41 +4969,41 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMS_50_129/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK
- clock pessimism -0.675 10.719
- clock uncertainty 0.000 10.719
+ CLMS_34_97/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WCLK
+ clock pessimism -0.693 10.701
+ clock uncertainty 0.000 10.701
- Hold time 0.380 11.099
+ Hold time 0.380 11.081
- Data required time 11.099
+ Data required time 11.081
----------------------------------------------------------------------------------------------------
- Data required time 11.099
- Data arrival time 11.248
+ Data required time 11.081
+ Data arrival time 11.242
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.149
+ Slack (MET) 0.161
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WD
Path Group : ddrphy_clkin
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 11.394
- Launch Clock Delay : 10.665
+Clock Skew : 0.022 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 11.436
+ Launch Clock Delay : 10.721
Clock Pessimism Removal : -0.693
Location Delay Type Incr Path Logical Resource
@@ -4594,25 +5017,25 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 6.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.531 10.665 ntclkbufg_0
- CLMA_58_144/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
+ net (fanout=5464) 1.587 10.721 ntclkbufg_0
+ CLMS_42_85/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK
- CLMA_58_144/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0
- net (fanout=7) 0.356 11.243 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
- CLMS_62_145/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0
+ CLMS_42_85/Q1 tco 0.224 10.945 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/Q
+ net (fanout=2) 0.342 11.287 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [12]
+ CLMS_38_81/DD f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WD
- Data arrival time 11.243 Logic Levels: 0
- Logic: 0.222ns(38.408%), Route: 0.356ns(61.592%)
+ Data arrival time 11.287 Logic Levels: 0
+ Logic: 0.224ns(39.576%), Route: 0.342ns(60.424%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -4623,41 +5046,41 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMS_62_145/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WCLK
- clock pessimism -0.693 10.701
- clock uncertainty 0.000 10.701
+ net (fanout=5464) 1.627 11.436 ntclkbufg_0
+ CLMS_38_81/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK
+ clock pessimism -0.693 10.743
+ clock uncertainty 0.000 10.743
- Hold time 0.380 11.081
+ Hold time 0.380 11.123
- Data required time 11.081
+ Data required time 11.123
----------------------------------------------------------------------------------------------------
- Data required time 11.081
- Data arrival time 11.243
+ Data required time 11.123
+ Data arrival time 11.287
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.162
+ Slack (MET) 0.164
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0
Path Group : ddrphy_clkin
Path Type : min (slow corner)
Path Class : sequential timing path
-Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 11.394
- Launch Clock Delay : 10.665
+Clock Skew : 0.062 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 11.446
+ Launch Clock Delay : 10.691
Clock Pessimism Removal : -0.693
Location Delay Type Incr Path Logical Resource
@@ -4671,25 +5094,25 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 6.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.531 10.665 ntclkbufg_0
- CLMA_58_144/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
+ net (fanout=5464) 1.557 10.691 ntclkbufg_0
+ CLMA_34_76/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
- CLMA_58_144/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0
- net (fanout=7) 0.356 11.243 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
- CLMS_62_145/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0
+ CLMA_34_76/Q0 tco 0.222 10.913 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0
+ net (fanout=44) 0.392 11.305 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
+ CLMS_42_81/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0
- Data arrival time 11.243 Logic Levels: 0
- Logic: 0.222ns(38.408%), Route: 0.356ns(61.592%)
+ Data arrival time 11.305 Logic Levels: 0
+ Logic: 0.222ns(36.156%), Route: 0.392ns(63.844%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -4700,29 +5123,29 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMS_62_145/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WCLK
- clock pessimism -0.693 10.701
- clock uncertainty 0.000 10.701
+ net (fanout=5464) 1.637 11.446 ntclkbufg_0
+ CLMS_42_81/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK
+ clock pessimism -0.693 10.753
+ clock uncertainty 0.000 10.753
- Hold time 0.380 11.081
+ Hold time 0.380 11.133
- Data required time 11.081
+ Data required time 11.133
----------------------------------------------------------------------------------------------------
- Data required time 11.081
- Data arrival time 11.243
+ Data required time 11.133
+ Data arrival time 11.305
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.162
+ Slack (MET) 0.172
====================================================================================================
====================================================================================================
@@ -4748,9 +5171,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -4773,9 +5196,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 5.188 _N69
PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 6.343 zoom_clk
+ net (fanout=2) 1.059 6.343 ddr_clk
USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 9.233 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -4817,9 +5240,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -4842,9 +5265,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 5.188 _N69
PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 6.343 zoom_clk
+ net (fanout=2) 1.059 6.343 ddr_clk
USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 9.233 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -4886,9 +5309,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -4911,9 +5334,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 5.188 _N69
PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 6.343 zoom_clk
+ net (fanout=2) 1.059 6.343 ddr_clk
USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 9.233 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -4955,9 +5378,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -4980,9 +5403,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -5024,9 +5447,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -5049,9 +5472,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -5093,9 +5516,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -5118,9 +5541,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -5162,9 +5585,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5187,9 +5610,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 5.188 _N69
PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 6.343 zoom_clk
+ net (fanout=2) 1.059 6.343 ddr_clk
USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 9.233 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5231,9 +5654,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5256,9 +5679,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 5.188 _N69
PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 6.343 zoom_clk
+ net (fanout=2) 1.059 6.343 ddr_clk
USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 9.233 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5300,9 +5723,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5325,9 +5748,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 5.188 _N69
PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 6.343 zoom_clk
+ net (fanout=2) 1.059 6.343 ddr_clk
USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 9.233 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5369,9 +5792,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5394,9 +5817,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5438,9 +5861,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5463,9 +5886,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5507,9 +5930,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5532,9 +5955,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -5556,12 +5979,12 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
====================================================================================================
Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS
Path Group : clk_50m
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.378
+Clock Skew : -0.040 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.392
Launch Clock Delay : 5.873
Clock Pessimism Removal : 0.441
@@ -5578,29 +6001,15 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.585 5.873 ntclkbufg_1
- CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-
- CLMS_94_177/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=573) 2.441 8.601 rd3_rst
- CLMS_146_37/RSCO td 0.147 8.748 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT
- net (fanout=4) 0.000 8.748 ntR414
- CLMS_146_41/RSCO td 0.147 8.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.895 ntR413
- CLMS_146_45/RSCO td 0.147 9.042 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=3) 0.000 9.042 ntR412
- CLMS_146_49/RSCO td 0.147 9.189 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT
- net (fanout=2) 0.000 9.189 ntR411
- CLMS_146_53/RSCO td 0.147 9.336 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
- net (fanout=4) 0.000 9.336 ntR410
- CLMS_146_57/RSCO td 0.147 9.483 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT
- net (fanout=6) 0.000 9.483 ntR409
- CLMS_146_61/RSCO td 0.147 9.630 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT
- net (fanout=5) 0.000 9.630 ntR408
- CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS
-
- Data arrival time 9.630 Logic Levels: 7
- Logic: 1.316ns(35.028%), Route: 2.441ns(64.972%)
+ net (fanout=2516) 1.585 5.873 ntclkbufg_1
+ CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
+
+ CLMS_158_237/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=589) 3.130 9.290 rd3_rst
+ CLMA_58_40/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS
+
+ Data arrival time 9.290 Logic Levels: 0
+ Logic: 0.287ns(8.399%), Route: 3.130ns(91.601%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 20.000 20.000 r
@@ -5613,30 +6022,30 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 23.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.531 25.378 ntclkbufg_1
- CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK
- clock pessimism 0.441 25.819
- clock uncertainty -0.150 25.669
+ net (fanout=2516) 1.545 25.392 ntclkbufg_1
+ CLMA_58_40/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK
+ clock pessimism 0.441 25.833
+ clock uncertainty -0.150 25.683
- Recovery time 0.000 25.669
+ Recovery time -0.617 25.066
- Data required time 25.669
+ Data required time 25.066
----------------------------------------------------------------------------------------------------
- Data required time 25.669
- Data arrival time 9.630
+ Data required time 25.066
+ Data arrival time 9.290
----------------------------------------------------------------------------------------------------
- Slack (MET) 16.039
+ Slack (MET) 15.776
====================================================================================================
====================================================================================================
Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS
Path Group : clk_50m
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.378
+Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.403
Launch Clock Delay : 5.873
Clock Pessimism Removal : 0.441
@@ -5653,29 +6062,15 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.585 5.873 ntclkbufg_1
- CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-
- CLMS_94_177/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=573) 2.441 8.601 rd3_rst
- CLMS_146_37/RSCO td 0.147 8.748 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT
- net (fanout=4) 0.000 8.748 ntR414
- CLMS_146_41/RSCO td 0.147 8.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.895 ntR413
- CLMS_146_45/RSCO td 0.147 9.042 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=3) 0.000 9.042 ntR412
- CLMS_146_49/RSCO td 0.147 9.189 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT
- net (fanout=2) 0.000 9.189 ntR411
- CLMS_146_53/RSCO td 0.147 9.336 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
- net (fanout=4) 0.000 9.336 ntR410
- CLMS_146_57/RSCO td 0.147 9.483 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT
- net (fanout=6) 0.000 9.483 ntR409
- CLMS_146_61/RSCO td 0.147 9.630 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT
- net (fanout=5) 0.000 9.630 ntR408
- CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS
-
- Data arrival time 9.630 Logic Levels: 7
- Logic: 1.316ns(35.028%), Route: 2.441ns(64.972%)
+ net (fanout=2516) 1.585 5.873 ntclkbufg_1
+ CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
+
+ CLMS_158_237/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=589) 2.965 9.125 rd3_rst
+ CLMA_58_33/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS
+
+ Data arrival time 9.125 Logic Levels: 0
+ Logic: 0.287ns(8.825%), Route: 2.965ns(91.175%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 20.000 20.000 r
@@ -5688,30 +6083,30 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 23.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.531 25.378 ntclkbufg_1
- CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK
- clock pessimism 0.441 25.819
- clock uncertainty -0.150 25.669
+ net (fanout=2516) 1.556 25.403 ntclkbufg_1
+ CLMA_58_33/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK
+ clock pessimism 0.441 25.844
+ clock uncertainty -0.150 25.694
- Recovery time 0.000 25.669
+ Recovery time -0.617 25.077
- Data required time 25.669
+ Data required time 25.077
----------------------------------------------------------------------------------------------------
- Data required time 25.669
- Data arrival time 9.630
+ Data required time 25.077
+ Data arrival time 9.125
----------------------------------------------------------------------------------------------------
- Slack (MET) 16.039
+ Slack (MET) 15.952
====================================================================================================
====================================================================================================
Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS
Path Group : clk_50m
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.378
+Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.403
Launch Clock Delay : 5.873
Clock Pessimism Removal : 0.441
@@ -5728,29 +6123,15 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.585 5.873 ntclkbufg_1
- CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-
- CLMS_94_177/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=573) 2.441 8.601 rd3_rst
- CLMS_146_37/RSCO td 0.147 8.748 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT
- net (fanout=4) 0.000 8.748 ntR414
- CLMS_146_41/RSCO td 0.147 8.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.895 ntR413
- CLMS_146_45/RSCO td 0.147 9.042 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=3) 0.000 9.042 ntR412
- CLMS_146_49/RSCO td 0.147 9.189 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT
- net (fanout=2) 0.000 9.189 ntR411
- CLMS_146_53/RSCO td 0.147 9.336 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
- net (fanout=4) 0.000 9.336 ntR410
- CLMS_146_57/RSCO td 0.147 9.483 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT
- net (fanout=6) 0.000 9.483 ntR409
- CLMS_146_61/RSCO td 0.147 9.630 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT
- net (fanout=5) 0.000 9.630 ntR408
- CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS
-
- Data arrival time 9.630 Logic Levels: 7
- Logic: 1.316ns(35.028%), Route: 2.441ns(64.972%)
+ net (fanout=2516) 1.585 5.873 ntclkbufg_1
+ CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
+
+ CLMS_158_237/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=589) 2.965 9.125 rd3_rst
+ CLMA_58_33/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS
+
+ Data arrival time 9.125 Logic Levels: 0
+ Logic: 0.287ns(8.825%), Route: 2.965ns(91.175%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 20.000 20.000 r
@@ -5763,32 +6144,32 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 23.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.531 25.378 ntclkbufg_1
- CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK
- clock pessimism 0.441 25.819
- clock uncertainty -0.150 25.669
+ net (fanout=2516) 1.556 25.403 ntclkbufg_1
+ CLMA_58_33/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK
+ clock pessimism 0.441 25.844
+ clock uncertainty -0.150 25.694
- Recovery time 0.000 25.669
+ Recovery time -0.617 25.077
- Data required time 25.669
+ Data required time 25.077
----------------------------------------------------------------------------------------------------
- Data required time 25.669
- Data arrival time 9.630
+ Data required time 25.077
+ Data arrival time 9.125
----------------------------------------------------------------------------------------------------
- Slack (MET) 16.039
+ Slack (MET) 15.952
====================================================================================================
====================================================================================================
Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
-Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+Endpoint : image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
Path Group : clk_50m
Path Type : min (slow corner)
Path Class : async timing path
Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.873
- Launch Clock Delay : 5.378
- Clock Pessimism Removal : -0.459
+ Capture Clock Delay : 5.996
+ Launch Clock Delay : 5.499
+ Clock Pessimism Removal : -0.461
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -5803,15 +6184,15 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.531 5.378 ntclkbufg_1
- CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+ net (fanout=2516) 1.652 5.499 ntclkbufg_1
+ CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
- CLMS_134_93/Q0 tco 0.222 5.600 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
- net (fanout=37) 0.347 5.947 image_filiter_inst/multiline_buffer_inst/srst
- DRM_142_88/RSTB[0] f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+ CLMS_98_321/Q0 tco 0.222 5.721 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
+ net (fanout=40) 0.402 6.123 image_filiter_inst/multiline_buffer_inst/srst
+ DRM_82_316/RSTB[0] f image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
- Data arrival time 5.947 Logic Levels: 0
- Logic: 0.222ns(39.016%), Route: 0.347ns(60.984%)
+ Data arrival time 6.123 Logic Levels: 0
+ Logic: 0.222ns(35.577%), Route: 0.402ns(64.423%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 0.000 0.000 r
@@ -5824,32 +6205,32 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.585 5.873 ntclkbufg_1
- DRM_142_88/CLKB[0] r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0]
- clock pessimism -0.459 5.414
- clock uncertainty 0.000 5.414
+ net (fanout=2516) 1.708 5.996 ntclkbufg_1
+ DRM_82_316/CLKB[0] r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0]
+ clock pessimism -0.461 5.535
+ clock uncertainty 0.000 5.535
- Removal time -0.022 5.392
+ Removal time -0.022 5.513
- Data required time 5.392
+ Data required time 5.513
----------------------------------------------------------------------------------------------------
- Data required time 5.392
- Data arrival time 5.947
+ Data required time 5.513
+ Data arrival time 6.123
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.555
+ Slack (MET) 0.610
====================================================================================================
====================================================================================================
Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
-Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS
Path Group : clk_50m
Path Type : min (slow corner)
Path Class : async timing path
Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.873
- Launch Clock Delay : 5.378
- Clock Pessimism Removal : -0.459
+ Capture Clock Delay : 5.996
+ Launch Clock Delay : 5.499
+ Clock Pessimism Removal : -0.461
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -5864,15 +6245,17 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.531 5.378 ntclkbufg_1
- CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+ net (fanout=2516) 1.652 5.499 ntclkbufg_1
+ CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
- CLMS_134_93/Q0 tco 0.222 5.600 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
- net (fanout=37) 0.347 5.947 image_filiter_inst/multiline_buffer_inst/srst
- DRM_142_88/RSTA[0] f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0]
+ CLMS_98_321/Q0 tco 0.222 5.721 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
+ net (fanout=40) 0.318 6.039 image_filiter_inst/multiline_buffer_inst/srst
+ CLMS_102_325/RSCO td 0.115 6.154 f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 6.154 ntR19
+ CLMS_102_329/RSCI f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS
- Data arrival time 5.947 Logic Levels: 0
- Logic: 0.222ns(39.016%), Route: 0.347ns(60.984%)
+ Data arrival time 6.154 Logic Levels: 1
+ Logic: 0.337ns(51.450%), Route: 0.318ns(48.550%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 0.000 0.000 r
@@ -5885,32 +6268,32 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.585 5.873 ntclkbufg_1
- DRM_142_88/CLKA[0] r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- clock pessimism -0.459 5.414
- clock uncertainty 0.000 5.414
+ net (fanout=2516) 1.708 5.996 ntclkbufg_1
+ CLMS_102_329/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK
+ clock pessimism -0.461 5.535
+ clock uncertainty 0.000 5.535
- Removal time -0.046 5.368
+ Removal time 0.000 5.535
- Data required time 5.368
+ Data required time 5.535
----------------------------------------------------------------------------------------------------
- Data required time 5.368
- Data arrival time 5.947
+ Data required time 5.535
+ Data arrival time 6.154
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.579
+ Slack (MET) 0.619
====================================================================================================
====================================================================================================
Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
-Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS
+Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS
Path Group : clk_50m
Path Type : min (slow corner)
Path Class : async timing path
Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.873
- Launch Clock Delay : 5.378
- Clock Pessimism Removal : -0.459
+ Capture Clock Delay : 5.996
+ Launch Clock Delay : 5.499
+ Clock Pessimism Removal : -0.461
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -5925,17 +6308,17 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.531 5.378 ntclkbufg_1
- CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+ net (fanout=2516) 1.652 5.499 ntclkbufg_1
+ CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
- CLMS_134_93/Q0 tco 0.226 5.604 r image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
- net (fanout=37) 0.465 6.069 image_filiter_inst/multiline_buffer_inst/srst
- CLMA_138_81/RSCO td 0.105 6.174 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT
- net (fanout=2) 0.000 6.174 ntR38
- CLMA_138_85/RSCI r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS
+ CLMS_98_321/Q0 tco 0.222 5.721 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
+ net (fanout=40) 0.318 6.039 image_filiter_inst/multiline_buffer_inst/srst
+ CLMS_102_325/RSCO td 0.115 6.154 f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 6.154 ntR19
+ CLMS_102_329/RSCI f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS
- Data arrival time 6.174 Logic Levels: 1
- Logic: 0.331ns(41.583%), Route: 0.465ns(58.417%)
+ Data arrival time 6.154 Logic Levels: 1
+ Logic: 0.337ns(51.450%), Route: 0.318ns(48.550%)
----------------------------------------------------------------------------------------------------
Clock clk_50m (rising edge) 0.000 0.000 r
@@ -5948,31 +6331,31 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 1.585 5.873 ntclkbufg_1
- CLMA_138_85/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK
- clock pessimism -0.459 5.414
- clock uncertainty 0.000 5.414
+ net (fanout=2516) 1.708 5.996 ntclkbufg_1
+ CLMS_102_329/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK
+ clock pessimism -0.461 5.535
+ clock uncertainty 0.000 5.535
- Removal time 0.000 5.414
+ Removal time 0.000 5.535
- Data required time 5.414
+ Data required time 5.535
----------------------------------------------------------------------------------------------------
- Data required time 5.414
- Data arrival time 6.174
+ Data required time 5.535
+ Data arrival time 6.154
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.760
+ Slack (MET) 0.619
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS
Path Group : clk_200m
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 5.374
- Launch Clock Delay : 5.867
+ Launch Clock Delay : 5.990
Clock Pessimism Removal : 0.439
Location Delay Type Incr Path Logical Resource
@@ -5986,17 +6369,17 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+ net (fanout=71) 1.708 5.990 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
- CLMA_202_148/Q1 tco 0.289 6.156 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q
- net (fanout=686) 2.787 8.943 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn
- CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS
+ CLMA_174_252/Q1 tco 0.289 6.279 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q
+ net (fanout=687) 2.618 8.897 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn
+ CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS
- Data arrival time 8.943 Logic Levels: 0
- Logic: 0.289ns(9.395%), Route: 2.787ns(90.605%)
+ Data arrival time 8.897 Logic Levels: 0
+ Logic: 0.289ns(9.942%), Route: 2.618ns(90.058%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 5.000 5.000 r
@@ -6007,10 +6390,10 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 7.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 8.843 zoom_clk
+ net (fanout=2) 1.059 8.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK
+ net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/CLK
clock pessimism 0.439 10.813
clock uncertainty -0.150 10.663
@@ -6019,21 +6402,21 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
Data required time 10.046
----------------------------------------------------------------------------------------------------
Data required time 10.046
- Data arrival time 8.943
+ Data arrival time 8.897
----------------------------------------------------------------------------------------------------
- Slack (MET) 1.103
+ Slack (MET) 1.149
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS
Path Group : clk_200m
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 5.374
- Launch Clock Delay : 5.867
+ Launch Clock Delay : 5.990
Clock Pessimism Removal : 0.439
Location Delay Type Incr Path Logical Resource
@@ -6047,17 +6430,17 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+ net (fanout=71) 1.708 5.990 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
- CLMA_202_148/Q1 tco 0.289 6.156 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q
- net (fanout=686) 2.787 8.943 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn
- CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS
+ CLMA_174_252/Q1 tco 0.289 6.279 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q
+ net (fanout=687) 2.274 8.553 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn
+ CLMA_30_184/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS
- Data arrival time 8.943 Logic Levels: 0
- Logic: 0.289ns(9.395%), Route: 2.787ns(90.605%)
+ Data arrival time 8.553 Logic Levels: 0
+ Logic: 0.289ns(11.276%), Route: 2.274ns(88.724%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 5.000 5.000 r
@@ -6068,10 +6451,10 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 7.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 8.843 zoom_clk
+ net (fanout=2) 1.059 8.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK
+ net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_30_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK
clock pessimism 0.439 10.813
clock uncertainty -0.150 10.663
@@ -6080,21 +6463,21 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
Data required time 10.046
----------------------------------------------------------------------------------------------------
Data required time 10.046
- Data arrival time 8.943
+ Data arrival time 8.553
----------------------------------------------------------------------------------------------------
- Slack (MET) 1.103
+ Slack (MET) 1.493
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS
Path Group : clk_200m
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.495
- Launch Clock Delay : 5.867
+Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.374
+ Launch Clock Delay : 5.990
Clock Pessimism Removal : 0.439
Location Delay Type Incr Path Logical Resource
@@ -6108,17 +6491,17 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.585 5.867 ntR3909
- CLMS_186_125/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+ net (fanout=2) 1.078 4.282 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.708 5.990 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
- CLMS_186_125/Q0 tco 0.287 6.154 f u_zoom_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=131) 3.324 9.478 zoom_rst
- DRM_278_356/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0]
+ CLMA_174_252/Q1 tco 0.289 6.279 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q
+ net (fanout=687) 2.274 8.553 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn
+ CLMA_30_184/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS
- Data arrival time 9.478 Logic Levels: 0
- Logic: 0.287ns(7.948%), Route: 3.324ns(92.052%)
+ Data arrival time 8.553 Logic Levels: 0
+ Logic: 0.289ns(11.276%), Route: 2.274ns(88.724%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 5.000 5.000 r
@@ -6129,21 +6512,21 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 7.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 8.843 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 8.843 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.652 10.495 ntR3909
- DRM_278_356/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/CLKA[0]
- clock pessimism 0.439 10.934
- clock uncertainty -0.150 10.784
+ net (fanout=2) 1.059 8.843 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_30_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK
+ clock pessimism 0.439 10.813
+ clock uncertainty -0.150 10.663
- Recovery time -0.115 10.669
+ Recovery time -0.617 10.046
- Data required time 10.669
+ Data required time 10.046
----------------------------------------------------------------------------------------------------
- Data required time 10.669
- Data arrival time 9.478
+ Data required time 10.046
+ Data arrival time 8.553
----------------------------------------------------------------------------------------------------
- Slack (MET) 1.191
+ Slack (MET) 1.493
====================================================================================================
====================================================================================================
@@ -6153,9 +6536,9 @@ Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opi
Path Group : clk_200m
Path Type : min (slow corner)
Path Class : async timing path
-Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.867
- Launch Clock Delay : 5.374
+Clock Skew : 0.069 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.990
+ Launch Clock Delay : 5.495
Clock Pessimism Removal : -0.426
Location Delay Type Incr Path Logical Resource
@@ -6169,17 +6552,17 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.531 5.374 ntR3909
- CLMS_202_149/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
+ net (fanout=2) 1.059 3.843 ddr_clk
+ USCM_84_153/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT
+ net (fanout=6) 1.652 5.495 ntR3952
+ CLMS_174_253/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
- CLMS_202_149/Q0 tco 0.222 5.596 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q
- net (fanout=2) 0.179 5.775 ddr_rst
- CLMA_202_148/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS
+ CLMS_174_253/Q0 tco 0.222 5.717 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q
+ net (fanout=2) 0.182 5.899 ddr_rst
+ CLMA_174_252/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS
- Data arrival time 5.775 Logic Levels: 0
- Logic: 0.222ns(55.362%), Route: 0.179ns(44.638%)
+ Data arrival time 5.899 Logic Levels: 0
+ Logic: 0.222ns(54.950%), Route: 0.182ns(45.050%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 0.000 0.000 r
@@ -6190,21 +6573,21 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK
- clock pessimism -0.426 5.441
- clock uncertainty 0.000 5.441
+ net (fanout=71) 1.708 5.990 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK
+ clock pessimism -0.426 5.564
+ clock uncertainty 0.000 5.564
- Removal time -0.220 5.221
+ Removal time -0.220 5.344
- Data required time 5.221
+ Data required time 5.344
----------------------------------------------------------------------------------------------------
- Data required time 5.221
- Data arrival time 5.775
+ Data required time 5.344
+ Data arrival time 5.899
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.554
+ Slack (MET) 0.555
====================================================================================================
====================================================================================================
@@ -6214,9 +6597,9 @@ Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opi
Path Group : clk_200m
Path Type : min (slow corner)
Path Class : async timing path
-Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.867
- Launch Clock Delay : 5.374
+Clock Skew : 0.069 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.990
+ Launch Clock Delay : 5.495
Clock Pessimism Removal : -0.426
Location Delay Type Incr Path Logical Resource
@@ -6230,17 +6613,17 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.531 5.374 ntR3909
- CLMS_202_149/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
+ net (fanout=2) 1.059 3.843 ddr_clk
+ USCM_84_153/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT
+ net (fanout=6) 1.652 5.495 ntR3952
+ CLMS_174_253/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
- CLMS_202_149/Q0 tco 0.222 5.596 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q
- net (fanout=2) 0.179 5.775 ddr_rst
- CLMA_202_148/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS
+ CLMS_174_253/Q0 tco 0.222 5.717 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q
+ net (fanout=2) 0.182 5.899 ddr_rst
+ CLMA_174_252/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS
- Data arrival time 5.775 Logic Levels: 0
- Logic: 0.222ns(55.362%), Route: 0.179ns(44.638%)
+ Data arrival time 5.899 Logic Levels: 0
+ Logic: 0.222ns(54.950%), Route: 0.182ns(45.050%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 0.000 0.000 r
@@ -6251,27 +6634,27 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
- clock pessimism -0.426 5.441
- clock uncertainty 0.000 5.441
+ net (fanout=71) 1.708 5.990 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+ clock pessimism -0.426 5.564
+ clock uncertainty 0.000 5.564
- Removal time -0.220 5.221
+ Removal time -0.220 5.344
- Data required time 5.221
+ Data required time 5.344
----------------------------------------------------------------------------------------------------
- Data required time 5.221
- Data arrival time 5.775
+ Data required time 5.344
+ Data arrival time 5.899
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.554
+ Slack (MET) 0.555
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/RS
Path Group : clk_200m
Path Type : min (slow corner)
Path Class : async timing path
@@ -6291,19 +6674,17 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.531 5.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMS_78_181/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK
+ net (fanout=71) 1.531 5.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_58_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK
- CLMS_78_181/Q0 tco 0.222 5.596 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/Q
- net (fanout=14) 0.443 6.039 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn
- CLMS_62_181/RSCO td 0.105 6.144 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 6.144 ntR1581
- CLMS_62_185/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS
+ CLMA_58_184/Q0 tco 0.222 5.596 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/Q
+ net (fanout=22) 0.485 6.081 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn
+ CLMA_50_196/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/RS
- Data arrival time 6.144 Logic Levels: 1
- Logic: 0.327ns(42.468%), Route: 0.443ns(57.532%)
+ Data arrival time 6.081 Logic Levels: 0
+ Logic: 0.222ns(31.400%), Route: 0.485ns(68.600%)
----------------------------------------------------------------------------------------------------
Clock clk_200m (rising edge) 0.000 0.000 r
@@ -6314,21 +6695,21 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMS_62_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/CLK
+ net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_50_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/CLK
clock pessimism -0.457 5.410
clock uncertainty 0.000 5.410
- Removal time 0.000 5.410
+ Removal time -0.220 5.190
- Data required time 5.410
+ Data required time 5.190
----------------------------------------------------------------------------------------------------
- Data required time 5.410
- Data arrival time 6.144
+ Data required time 5.190
+ Data arrival time 6.081
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.734
+ Slack (MET) 0.891
====================================================================================================
====================================================================================================
@@ -6338,10 +6719,10 @@ Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS
Path Group : clk_10m
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.378
+Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.499
Launch Clock Delay : 5.873
- Clock Pessimism Removal : 0.459
+ Clock Pessimism Removal : 0.441
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -6355,16 +6736,16 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.078 4.288 clk_10m
- USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.585 5.873 ntclkbufg_3
- CLMA_230_69/CLK r rstn_out1/opit_0_inv/CLK
+ USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.585 5.873 ntclkbufg_4
+ CLMS_270_193/CLK r rstn_out1/opit_0_inv/CLK
- CLMA_230_69/Q3 tco 0.286 6.159 f rstn_out1/opit_0_inv/Q
- net (fanout=3) 1.118 7.277 nt_eth_rstn
- CLMA_246_120/RS f ms72xx_ctl/rstn_temp1/opit_0_inv/RS
+ CLMS_270_193/Q3 tco 0.286 6.159 f rstn_out1/opit_0_inv/Q
+ net (fanout=3) 1.217 7.376 nt_eth_rstn
+ CLMA_262_268/RS f ms72xx_ctl/rstn_temp1/opit_0_inv/RS
- Data arrival time 7.277 Logic Levels: 0
- Logic: 0.286ns(20.370%), Route: 1.118ns(79.630%)
+ Data arrival time 7.376 Logic Levels: 0
+ Logic: 0.286ns(19.029%), Route: 1.217ns(80.971%)
----------------------------------------------------------------------------------------------------
Clock clk_10m (rising edge) 100.000 100.000 r
@@ -6376,20 +6757,20 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.758 102.688 _N69
PLL_158_55/CLK_OUT4 td 0.100 102.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.059 103.847 clk_10m
- USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.531 105.378 ntclkbufg_3
- CLMA_246_120/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK
- clock pessimism 0.459 105.837
- clock uncertainty -0.150 105.687
+ USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.652 105.499 ntclkbufg_4
+ CLMA_262_268/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK
+ clock pessimism 0.441 105.940
+ clock uncertainty -0.150 105.790
- Recovery time -0.617 105.070
+ Recovery time -0.617 105.173
- Data required time 105.070
+ Data required time 105.173
----------------------------------------------------------------------------------------------------
- Data required time 105.070
- Data arrival time 7.277
+ Data required time 105.173
+ Data arrival time 7.376
----------------------------------------------------------------------------------------------------
- Slack (MET) 97.793
+ Slack (MET) 97.797
====================================================================================================
====================================================================================================
@@ -6399,10 +6780,10 @@ Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS
Path Group : clk_10m
Path Type : min (slow corner)
Path Class : async timing path
-Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.873
+Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.996
Launch Clock Delay : 5.378
- Clock Pessimism Removal : -0.459
+ Clock Pessimism Removal : -0.441
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -6416,16 +6797,16 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT4 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.059 3.847 clk_10m
- USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.531 5.378 ntclkbufg_3
- CLMA_230_69/CLK r rstn_out1/opit_0_inv/CLK
+ USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.531 5.378 ntclkbufg_4
+ CLMS_270_193/CLK r rstn_out1/opit_0_inv/CLK
- CLMA_230_69/Q3 tco 0.226 5.604 r rstn_out1/opit_0_inv/Q
- net (fanout=3) 0.896 6.500 nt_eth_rstn
- CLMA_246_120/RS r ms72xx_ctl/rstn_temp1/opit_0_inv/RS
+ CLMS_270_193/Q3 tco 0.226 5.604 r rstn_out1/opit_0_inv/Q
+ net (fanout=3) 0.988 6.592 nt_eth_rstn
+ CLMA_262_268/RS r ms72xx_ctl/rstn_temp1/opit_0_inv/RS
- Data arrival time 6.500 Logic Levels: 0
- Logic: 0.226ns(20.143%), Route: 0.896ns(79.857%)
+ Data arrival time 6.592 Logic Levels: 0
+ Logic: 0.226ns(18.616%), Route: 0.988ns(81.384%)
----------------------------------------------------------------------------------------------------
Clock clk_10m (rising edge) 0.000 0.000 r
@@ -6437,38 +6818,38 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
net (fanout=1) 1.078 4.288 clk_10m
- USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 1.585 5.873 ntclkbufg_3
- CLMA_246_120/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK
- clock pessimism -0.459 5.414
- clock uncertainty 0.000 5.414
+ USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.708 5.996 ntclkbufg_4
+ CLMA_262_268/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK
+ clock pessimism -0.441 5.555
+ clock uncertainty 0.000 5.555
- Removal time -0.226 5.188
+ Removal time -0.226 5.329
- Data required time 5.188
+ Data required time 5.329
----------------------------------------------------------------------------------------------------
- Data required time 5.188
- Data arrival time 6.500
+ Data required time 5.329
+ Data arrival time 6.592
----------------------------------------------------------------------------------------------------
- Slack (MET) 1.312
+ Slack (MET) 1.263
====================================================================================================
====================================================================================================
-Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS
-Path Group : clk_720p60Hz
+Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 8.831
- Launch Clock Delay : 9.434
- Clock Pessimism Removal : 0.549
+Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 8.956
+ Launch Clock Delay : 9.440
+ Clock Pessimism Removal : 0.551
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
@@ -6478,86 +6859,66 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
- PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.599 7.849 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.585 9.434 ntclkbufg_2
- CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-
- CLMS_150_245/Q0 tco 0.287 9.721 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
- net (fanout=1066) 2.932 12.653 sync_vg_100m
- CLMA_294_132/RSCO td 0.147 12.800 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 12.800 ntR491
- CLMA_294_136/RSCO td 0.147 12.947 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 12.947 ntR490
- CLMA_294_140/RSCO td 0.147 13.094 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=1) 0.000 13.094 ntR489
- CLMA_294_144/RSCO td 0.147 13.241 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 13.241 ntR488
- CLMA_294_148/RSCO td 0.147 13.388 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 13.388 ntR487
- CLMA_294_152/RSCO td 0.147 13.535 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.535 ntR486
- CLMA_294_156/RSCO td 0.147 13.682 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.682 ntR485
- CLMA_294_160/RSCO td 0.147 13.829 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=2) 0.000 13.829 ntR484
- CLMA_294_164/RSCO td 0.147 13.976 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 13.976 ntR483
- CLMA_294_168/RSCO td 0.147 14.123 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 14.123 ntR482
- CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS
-
- Data arrival time 14.123 Logic Levels: 10
- Logic: 1.757ns(37.471%), Route: 2.932ns(62.529%)
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.585 9.440 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+
+ CLMA_170_124/Q0 tco 0.287 9.727 f u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 2.983 12.710 zoom_rst
+ DRM_306_252/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0]
+
+ Data arrival time 12.710 Logic Levels: 0
+ Logic: 0.287ns(8.777%), Route: 2.983ns(91.223%)
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 13.473 13.473 r
- P20 0.000 13.473 r clk (port)
- net (fanout=1) 0.074 13.547 clk
- IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 15.355 clk_ibuf/ntD
- IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.758 16.161 _N69
- PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 1.059 17.320 rd3_clk
- USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 19.106 ntR3907
- PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.571 20.773 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.531 22.304 ntclkbufg_2
- CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/CLK
- clock pessimism 0.549 22.853
- clock uncertainty -0.150 22.703
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.618 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 9.424 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 10.583 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 12.369 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 14.040 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.652 15.692 ntclkbufg_3
+ DRM_306_252/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism 0.551 16.243
+ clock uncertainty -0.150 16.093
- Recovery time 0.000 22.703
+ Recovery time -0.115 15.978
- Data required time 22.703
+ Data required time 15.978
----------------------------------------------------------------------------------------------------
- Data required time 22.703
- Data arrival time 14.123
+ Data required time 15.978
+ Data arrival time 12.710
----------------------------------------------------------------------------------------------------
- Slack (MET) 8.580
+ Slack (MET) 3.268
====================================================================================================
====================================================================================================
-Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS
-Path Group : clk_720p60Hz
+Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 8.831
- Launch Clock Delay : 9.434
- Clock Pessimism Removal : 0.549
+Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 8.956
+ Launch Clock Delay : 9.440
+ Clock Pessimism Removal : 0.551
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
@@ -6567,86 +6928,66 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
- PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.599 7.849 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.585 9.434 ntclkbufg_2
- CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-
- CLMS_150_245/Q0 tco 0.287 9.721 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
- net (fanout=1066) 2.932 12.653 sync_vg_100m
- CLMA_294_132/RSCO td 0.147 12.800 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 12.800 ntR491
- CLMA_294_136/RSCO td 0.147 12.947 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 12.947 ntR490
- CLMA_294_140/RSCO td 0.147 13.094 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=1) 0.000 13.094 ntR489
- CLMA_294_144/RSCO td 0.147 13.241 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 13.241 ntR488
- CLMA_294_148/RSCO td 0.147 13.388 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 13.388 ntR487
- CLMA_294_152/RSCO td 0.147 13.535 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.535 ntR486
- CLMA_294_156/RSCO td 0.147 13.682 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.682 ntR485
- CLMA_294_160/RSCO td 0.147 13.829 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=2) 0.000 13.829 ntR484
- CLMA_294_164/RSCO td 0.147 13.976 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 13.976 ntR483
- CLMA_294_168/RSCO td 0.147 14.123 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 14.123 ntR482
- CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS
-
- Data arrival time 14.123 Logic Levels: 10
- Logic: 1.757ns(37.471%), Route: 2.932ns(62.529%)
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.585 9.440 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+
+ CLMA_170_124/Q0 tco 0.287 9.727 f u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 2.931 12.658 zoom_rst
+ DRM_306_292/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0]
+
+ Data arrival time 12.658 Logic Levels: 0
+ Logic: 0.287ns(8.919%), Route: 2.931ns(91.081%)
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 13.473 13.473 r
- P20 0.000 13.473 r clk (port)
- net (fanout=1) 0.074 13.547 clk
- IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 15.355 clk_ibuf/ntD
- IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.758 16.161 _N69
- PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 1.059 17.320 rd3_clk
- USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 19.106 ntR3907
- PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.571 20.773 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.531 22.304 ntclkbufg_2
- CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/CLK
- clock pessimism 0.549 22.853
- clock uncertainty -0.150 22.703
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.618 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 9.424 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 10.583 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 12.369 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 14.040 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.652 15.692 ntclkbufg_3
+ DRM_306_292/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism 0.551 16.243
+ clock uncertainty -0.150 16.093
- Recovery time 0.000 22.703
+ Recovery time -0.115 15.978
- Data required time 22.703
+ Data required time 15.978
----------------------------------------------------------------------------------------------------
- Data required time 22.703
- Data arrival time 14.123
+ Data required time 15.978
+ Data arrival time 12.658
----------------------------------------------------------------------------------------------------
- Slack (MET) 8.580
+ Slack (MET) 3.320
====================================================================================================
====================================================================================================
-Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS
-Path Group : clk_720p60Hz
+Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 8.831
- Launch Clock Delay : 9.434
- Clock Pessimism Removal : 0.549
+Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 8.956
+ Launch Clock Delay : 9.440
+ Clock Pessimism Removal : 0.551
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
@@ -6656,86 +6997,66 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
- PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.599 7.849 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.585 9.434 ntclkbufg_2
- CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-
- CLMS_150_245/Q0 tco 0.287 9.721 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
- net (fanout=1066) 2.932 12.653 sync_vg_100m
- CLMA_294_132/RSCO td 0.147 12.800 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 12.800 ntR491
- CLMA_294_136/RSCO td 0.147 12.947 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 12.947 ntR490
- CLMA_294_140/RSCO td 0.147 13.094 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=1) 0.000 13.094 ntR489
- CLMA_294_144/RSCO td 0.147 13.241 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 13.241 ntR488
- CLMA_294_148/RSCO td 0.147 13.388 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 13.388 ntR487
- CLMA_294_152/RSCO td 0.147 13.535 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.535 ntR486
- CLMA_294_156/RSCO td 0.147 13.682 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.682 ntR485
- CLMA_294_160/RSCO td 0.147 13.829 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=2) 0.000 13.829 ntR484
- CLMA_294_164/RSCO td 0.147 13.976 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 13.976 ntR483
- CLMA_294_168/RSCO td 0.147 14.123 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 14.123 ntR482
- CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS
-
- Data arrival time 14.123 Logic Levels: 10
- Logic: 1.757ns(37.471%), Route: 2.932ns(62.529%)
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.585 9.440 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+
+ CLMA_170_124/Q0 tco 0.287 9.727 f u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 2.828 12.555 zoom_rst
+ DRM_306_272/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0]
+
+ Data arrival time 12.555 Logic Levels: 0
+ Logic: 0.287ns(9.213%), Route: 2.828ns(90.787%)
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 13.473 13.473 r
- P20 0.000 13.473 r clk (port)
- net (fanout=1) 0.074 13.547 clk
- IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 15.355 clk_ibuf/ntD
- IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.758 16.161 _N69
- PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 1.059 17.320 rd3_clk
- USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 19.106 ntR3907
- PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.571 20.773 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.531 22.304 ntclkbufg_2
- CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/CLK
- clock pessimism 0.549 22.853
- clock uncertainty -0.150 22.703
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.618 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 9.424 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 10.583 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 12.369 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 14.040 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.652 15.692 ntclkbufg_3
+ DRM_306_272/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism 0.551 16.243
+ clock uncertainty -0.150 16.093
- Recovery time 0.000 22.703
+ Recovery time -0.115 15.978
- Data required time 22.703
+ Data required time 15.978
----------------------------------------------------------------------------------------------------
- Data required time 22.703
- Data arrival time 14.123
+ Data required time 15.978
+ Data arrival time 12.555
----------------------------------------------------------------------------------------------------
- Slack (MET) 8.580
+ Slack (MET) 3.423
====================================================================================================
====================================================================================================
-Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0]
-Path Group : clk_720p60Hz
+Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
Path Type : min (slow corner)
Path Class : async timing path
-Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 9.434
- Launch Clock Delay : 8.831
- Clock Pessimism Removal : -0.567
+Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 9.440
+ Launch Clock Delay : 8.835
+ Clock Pessimism Removal : -0.551
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O
@@ -6745,22 +7066,22 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 5.633 ntR3907
- PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.571 7.300 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.531 8.831 ntclkbufg_2
- CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
+ net (fanout=1) 1.786 5.633 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 7.304 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.531 8.835 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
- CLMA_190_124/Q0 tco 0.226 9.057 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=163) 0.977 10.034 rd2_rst
- DRM_234_88/RSTB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0]
+ CLMA_170_124/Q0 tco 0.226 9.061 r u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 1.004 10.065 zoom_rst
+ DRM_234_128/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0]
- Data arrival time 10.034 Logic Levels: 0
- Logic: 0.226ns(18.786%), Route: 0.977ns(81.214%)
+ Data arrival time 10.065 Logic Levels: 0
+ Logic: 0.226ns(18.374%), Route: 1.004ns(81.626%)
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
@@ -6770,41 +7091,41 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
- PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.599 7.849 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.585 9.434 ntclkbufg_2
- DRM_234_88/CLKB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/CLKB[0]
- clock pessimism -0.567 8.867
- clock uncertainty 0.000 8.867
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.585 9.440 ntclkbufg_3
+ DRM_234_128/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism -0.551 8.889
+ clock uncertainty 0.000 8.889
- Removal time -0.077 8.790
+ Removal time -0.073 8.816
- Data required time 8.790
+ Data required time 8.816
----------------------------------------------------------------------------------------------------
- Data required time 8.790
- Data arrival time 10.034
+ Data required time 8.816
+ Data arrival time 10.065
----------------------------------------------------------------------------------------------------
- Slack (MET) 1.244
+ Slack (MET) 1.249
====================================================================================================
====================================================================================================
-Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
-Path Group : clk_720p60Hz
+Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
Path Type : min (slow corner)
Path Class : async timing path
-Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 9.434
- Launch Clock Delay : 8.831
- Clock Pessimism Removal : -0.549
+Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 9.440
+ Launch Clock Delay : 8.835
+ Clock Pessimism Removal : -0.569
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O
@@ -6814,22 +7135,22 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 5.633 ntR3907
- PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.571 7.300 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.531 8.831 ntclkbufg_2
- CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
+ net (fanout=1) 1.786 5.633 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 7.304 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.531 8.835 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
- CLMA_190_124/Q0 tco 0.226 9.057 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=163) 1.106 10.163 rd2_rst
- DRM_234_148/RSTB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+ CLMA_170_124/Q0 tco 0.226 9.061 r u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 1.040 10.101 zoom_rst
+ DRM_234_88/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0]
- Data arrival time 10.163 Logic Levels: 0
- Logic: 0.226ns(16.967%), Route: 1.106ns(83.033%)
+ Data arrival time 10.101 Logic Levels: 0
+ Logic: 0.226ns(17.852%), Route: 1.040ns(82.148%)
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
@@ -6839,41 +7160,41 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
- PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.599 7.849 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.585 9.434 ntclkbufg_2
- DRM_234_148/CLKB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0]
- clock pessimism -0.549 8.885
- clock uncertainty 0.000 8.885
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.585 9.440 ntclkbufg_3
+ DRM_234_88/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism -0.569 8.871
+ clock uncertainty 0.000 8.871
- Removal time -0.077 8.808
+ Removal time -0.073 8.798
- Data required time 8.808
+ Data required time 8.798
----------------------------------------------------------------------------------------------------
- Data required time 8.808
- Data arrival time 10.163
+ Data required time 8.798
+ Data arrival time 10.101
----------------------------------------------------------------------------------------------------
- Slack (MET) 1.355
+ Slack (MET) 1.303
====================================================================================================
====================================================================================================
-Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[15]/opit_0/RS
-Path Group : clk_720p60Hz
+Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
Path Type : min (slow corner)
Path Class : async timing path
-Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 9.434
- Launch Clock Delay : 8.831
- Clock Pessimism Removal : -0.549
+Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 9.440
+ Launch Clock Delay : 8.835
+ Clock Pessimism Removal : -0.569
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O
@@ -6883,22 +7204,22 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.059 3.847 rd3_clk
USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.786 5.633 ntR3907
- PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.571 7.300 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.531 8.831 ntclkbufg_2
- CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
+ net (fanout=1) 1.786 5.633 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.571 7.304 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.531 8.835 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
- CLMA_190_124/Q0 tco 0.226 9.057 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=163) 0.979 10.036 rd2_rst
- CLMS_226_173/RS r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[15]/opit_0/RS
+ CLMA_170_124/Q0 tco 0.226 9.061 r u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 1.120 10.181 zoom_rst
+ DRM_234_108/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0]
- Data arrival time 10.036 Logic Levels: 0
- Logic: 0.226ns(18.755%), Route: 0.979ns(81.245%)
+ Data arrival time 10.181 Logic Levels: 0
+ Logic: 0.226ns(16.790%), Route: 1.120ns(83.210%)
----------------------------------------------------------------------------------------------------
- Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
@@ -6908,36 +7229,546 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 1.078 4.288 rd3_clk
USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.861 6.149 ntR3907
- PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.599 7.849 nt_pix_clk
- USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 1.585 9.434 ntclkbufg_2
- CLMS_226_173/CLK r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[15]/opit_0/CLK
- clock pessimism -0.549 8.885
- clock uncertainty 0.000 8.885
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 1.599 7.855 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.585 9.440 ntclkbufg_3
+ DRM_234_108/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism -0.569 8.871
+ clock uncertainty 0.000 8.871
- Removal time -0.226 8.659
+ Removal time -0.073 8.798
- Data required time 8.659
+ Data required time 8.798
----------------------------------------------------------------------------------------------------
- Data required time 8.659
- Data arrival time 10.036
+ Data required time 8.798
+ Data arrival time 10.181
----------------------------------------------------------------------------------------------------
- Slack (MET) 1.377
+ Slack (MET) 1.383
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS
-Path Group : ddrphy_clkin
+Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS
+Path Group : clk_720p60Hz
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 10.786
- Launch Clock Delay : 11.394
- Clock Pessimism Removal : 0.675
+Clock Skew : -0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 8.952
+ Launch Clock Delay : 9.557
+ Clock Pessimism Removal : 0.549
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.599 7.849 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.708 9.557 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_150_276/Q0 tco 0.287 9.844 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 1.982 11.826 sync_vg_100m
+ CLMA_190_240/RSCO td 0.147 11.973 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT
+ net (fanout=3) 0.000 11.973 ntR687
+ CLMA_190_244/RSCO td 0.147 12.120 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT
+ net (fanout=4) 0.000 12.120 ntR686
+ CLMA_190_248/RSCO td 0.147 12.267 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 12.267 ntR685
+ CLMA_190_252/RSCO td 0.147 12.414 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT
+ net (fanout=6) 0.000 12.414 ntR684
+ CLMA_190_256/RSCO td 0.147 12.561 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT
+ net (fanout=5) 0.000 12.561 ntR683
+ CLMA_190_260/RSCO td 0.147 12.708 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 12.708 ntR682
+ CLMA_190_264/RSCO td 0.147 12.855 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT
+ net (fanout=4) 0.000 12.855 ntR681
+ CLMA_190_268/RSCO td 0.147 13.002 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.002 ntR680
+ CLMA_190_272/RSCO td 0.147 13.149 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.149 ntR679
+ CLMA_190_276/RSCO td 0.147 13.296 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT
+ net (fanout=4) 0.000 13.296 ntR678
+ CLMA_190_280/RSCO td 0.147 13.443 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT
+ net (fanout=4) 0.000 13.443 ntR677
+ CLMA_190_284/RSCO td 0.147 13.590 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
+ net (fanout=6) 0.000 13.590 ntR676
+ CLMA_190_288/RSCO td 0.147 13.737 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT
+ net (fanout=1) 0.000 13.737 ntR675
+ CLMA_190_292/RSCO td 0.147 13.884 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT
+ net (fanout=6) 0.000 13.884 ntR674
+ CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS
+
+ Data arrival time 13.884 Logic Levels: 14
+ Logic: 2.345ns(54.195%), Route: 1.982ns(45.805%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 13.473 13.473 r
+ P20 0.000 13.473 r clk (port)
+ net (fanout=1) 0.074 13.547 clk
+ IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 15.355 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 16.161 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 17.320 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 19.106 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.571 20.773 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.652 22.425 ntclkbufg_2
+ CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK
+ clock pessimism 0.549 22.974
+ clock uncertainty -0.150 22.824
+
+ Recovery time 0.000 22.824
+
+ Data required time 22.824
+----------------------------------------------------------------------------------------------------
+ Data required time 22.824
+ Data arrival time 13.884
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 8.940
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS
+Path Group : clk_720p60Hz
+Path Type : max (slow corner)
+Path Class : async timing path
+Clock Skew : -0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 8.952
+ Launch Clock Delay : 9.557
+ Clock Pessimism Removal : 0.549
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.599 7.849 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.708 9.557 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_150_276/Q0 tco 0.287 9.844 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 1.982 11.826 sync_vg_100m
+ CLMA_190_240/RSCO td 0.147 11.973 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT
+ net (fanout=3) 0.000 11.973 ntR687
+ CLMA_190_244/RSCO td 0.147 12.120 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT
+ net (fanout=4) 0.000 12.120 ntR686
+ CLMA_190_248/RSCO td 0.147 12.267 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 12.267 ntR685
+ CLMA_190_252/RSCO td 0.147 12.414 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT
+ net (fanout=6) 0.000 12.414 ntR684
+ CLMA_190_256/RSCO td 0.147 12.561 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT
+ net (fanout=5) 0.000 12.561 ntR683
+ CLMA_190_260/RSCO td 0.147 12.708 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 12.708 ntR682
+ CLMA_190_264/RSCO td 0.147 12.855 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT
+ net (fanout=4) 0.000 12.855 ntR681
+ CLMA_190_268/RSCO td 0.147 13.002 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.002 ntR680
+ CLMA_190_272/RSCO td 0.147 13.149 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.149 ntR679
+ CLMA_190_276/RSCO td 0.147 13.296 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT
+ net (fanout=4) 0.000 13.296 ntR678
+ CLMA_190_280/RSCO td 0.147 13.443 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT
+ net (fanout=4) 0.000 13.443 ntR677
+ CLMA_190_284/RSCO td 0.147 13.590 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
+ net (fanout=6) 0.000 13.590 ntR676
+ CLMA_190_288/RSCO td 0.147 13.737 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT
+ net (fanout=1) 0.000 13.737 ntR675
+ CLMA_190_292/RSCO td 0.147 13.884 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT
+ net (fanout=6) 0.000 13.884 ntR674
+ CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS
+
+ Data arrival time 13.884 Logic Levels: 14
+ Logic: 2.345ns(54.195%), Route: 1.982ns(45.805%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 13.473 13.473 r
+ P20 0.000 13.473 r clk (port)
+ net (fanout=1) 0.074 13.547 clk
+ IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 15.355 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 16.161 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 17.320 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 19.106 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.571 20.773 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.652 22.425 ntclkbufg_2
+ CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK
+ clock pessimism 0.549 22.974
+ clock uncertainty -0.150 22.824
+
+ Recovery time 0.000 22.824
+
+ Data required time 22.824
+----------------------------------------------------------------------------------------------------
+ Data required time 22.824
+ Data arrival time 13.884
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 8.940
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS
+Path Group : clk_720p60Hz
+Path Type : max (slow corner)
+Path Class : async timing path
+Clock Skew : -0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 8.952
+ Launch Clock Delay : 9.557
+ Clock Pessimism Removal : 0.549
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.599 7.849 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.708 9.557 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_150_276/Q0 tco 0.287 9.844 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 1.982 11.826 sync_vg_100m
+ CLMA_190_240/RSCO td 0.147 11.973 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT
+ net (fanout=3) 0.000 11.973 ntR687
+ CLMA_190_244/RSCO td 0.147 12.120 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT
+ net (fanout=4) 0.000 12.120 ntR686
+ CLMA_190_248/RSCO td 0.147 12.267 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 12.267 ntR685
+ CLMA_190_252/RSCO td 0.147 12.414 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT
+ net (fanout=6) 0.000 12.414 ntR684
+ CLMA_190_256/RSCO td 0.147 12.561 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT
+ net (fanout=5) 0.000 12.561 ntR683
+ CLMA_190_260/RSCO td 0.147 12.708 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 12.708 ntR682
+ CLMA_190_264/RSCO td 0.147 12.855 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT
+ net (fanout=4) 0.000 12.855 ntR681
+ CLMA_190_268/RSCO td 0.147 13.002 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.002 ntR680
+ CLMA_190_272/RSCO td 0.147 13.149 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.149 ntR679
+ CLMA_190_276/RSCO td 0.147 13.296 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT
+ net (fanout=4) 0.000 13.296 ntR678
+ CLMA_190_280/RSCO td 0.147 13.443 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT
+ net (fanout=4) 0.000 13.443 ntR677
+ CLMA_190_284/RSCO td 0.147 13.590 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
+ net (fanout=6) 0.000 13.590 ntR676
+ CLMA_190_288/RSCO td 0.147 13.737 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT
+ net (fanout=1) 0.000 13.737 ntR675
+ CLMA_190_292/RSCO td 0.147 13.884 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT
+ net (fanout=6) 0.000 13.884 ntR674
+ CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS
+
+ Data arrival time 13.884 Logic Levels: 14
+ Logic: 2.345ns(54.195%), Route: 1.982ns(45.805%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 13.473 13.473 r
+ P20 0.000 13.473 r clk (port)
+ net (fanout=1) 0.074 13.547 clk
+ IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 15.355 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 16.161 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 17.320 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 19.106 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.571 20.773 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.652 22.425 ntclkbufg_2
+ CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK
+ clock pessimism 0.549 22.974
+ clock uncertainty -0.150 22.824
+
+ Recovery time 0.000 22.824
+
+ Data required time 22.824
+----------------------------------------------------------------------------------------------------
+ Data required time 22.824
+ Data arrival time 13.884
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 8.940
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+Path Group : clk_720p60Hz
+Path Type : min (slow corner)
+Path Class : async timing path
+Clock Skew : 0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 9.557
+ Launch Clock Delay : 8.952
+ Clock Pessimism Removal : -0.549
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.882 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 2.688 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 3.847 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 5.633 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.571 7.300 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.652 8.952 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_150_276/Q0 tco 0.222 9.174 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 0.796 9.970 sync_vg_100m
+ DRM_178_272/RSTB[0] f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+
+ Data arrival time 9.970 Logic Levels: 0
+ Logic: 0.222ns(21.807%), Route: 0.796ns(78.193%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.599 7.849 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.708 9.557 ntclkbufg_2
+ DRM_178_272/CLKB[0] r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0]
+ clock pessimism -0.549 9.008
+ clock uncertainty 0.000 9.008
+
+ Removal time -0.022 8.986
+
+ Data required time 8.986
+----------------------------------------------------------------------------------------------------
+ Data required time 8.986
+ Data arrival time 9.970
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 0.984
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS
+Path Group : clk_720p60Hz
+Path Type : min (slow corner)
+Path Class : async timing path
+Clock Skew : 0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 9.557
+ Launch Clock Delay : 8.952
+ Clock Pessimism Removal : -0.549
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.882 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 2.688 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 3.847 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 5.633 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.571 7.300 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.652 8.952 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_150_276/Q0 tco 0.226 9.178 r sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 0.801 9.979 sync_vg_100m
+ CLMA_182_281/RSCO td 0.105 10.084 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=3) 0.000 10.084 ntR691
+ CLMA_182_285/RSCO td 0.105 10.189 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 10.189 ntR690
+ CLMA_182_289/RSCO td 0.105 10.294 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT
+ net (fanout=5) 0.000 10.294 ntR689
+ CLMA_182_293/RSCI r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS
+
+ Data arrival time 10.294 Logic Levels: 3
+ Logic: 0.541ns(40.313%), Route: 0.801ns(59.687%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.599 7.849 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.708 9.557 ntclkbufg_2
+ CLMA_182_293/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK
+ clock pessimism -0.549 9.008
+ clock uncertainty 0.000 9.008
+
+ Removal time 0.000 9.008
+
+ Data required time 9.008
+----------------------------------------------------------------------------------------------------
+ Data required time 9.008
+ Data arrival time 10.294
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 1.286
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS
+Path Group : clk_720p60Hz
+Path Type : min (slow corner)
+Path Class : async timing path
+Clock Skew : 0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 9.557
+ Launch Clock Delay : 8.952
+ Clock Pessimism Removal : -0.549
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.882 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.758 2.688 _N69
+ PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.059 3.847 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.786 5.633 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.571 7.300 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.652 8.952 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_150_276/Q0 tco 0.226 9.178 r sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 0.801 9.979 sync_vg_100m
+ CLMA_182_281/RSCO td 0.105 10.084 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=3) 0.000 10.084 ntR691
+ CLMA_182_285/RSCO td 0.105 10.189 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 10.189 ntR690
+ CLMA_182_289/RSCO td 0.105 10.294 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT
+ net (fanout=5) 0.000 10.294 ntR689
+ CLMA_182_293/RSCI r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS
+
+ Data arrival time 10.294 Logic Levels: 3
+ Logic: 0.541ns(40.313%), Route: 0.801ns(59.687%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_720p60Hz (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.240 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.787 3.103 _N69
+ PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 1.078 4.288 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.861 6.149 ntR3950
+ PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 1.599 7.849 nt_pix_clk
+ USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT
+ net (fanout=1635) 1.708 9.557 ntclkbufg_2
+ CLMA_182_293/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK
+ clock pessimism -0.549 9.008
+ clock uncertainty 0.000 9.008
+
+ Removal time 0.000 9.008
+
+ Data required time 9.008
+----------------------------------------------------------------------------------------------------
+ Data required time 9.008
+ Data arrival time 10.294
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 1.286
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS
+Path Group : ddrphy_clkin
+Path Type : max (slow corner)
+Path Class : async timing path
+Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 10.665
+ Launch Clock Delay : 11.394
+ Clock Pessimism Removal : 0.693
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -6950,59 +7781,57 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-
- CLMA_70_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 1.655 13.338 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_10_224/RSCO td 0.147 13.485 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.485 ntR1395
- CLMA_10_228/RSCO td 0.147 13.632 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.632 ntR1394
- CLMA_10_232/RSCO td 0.147 13.779 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.779 ntR1393
- CLMA_10_236/RSCO td 0.147 13.926 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 13.926 ntR1392
- CLMA_10_240/RSCO td 0.147 14.073 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 14.073 ntR1391
- CLMA_10_244/RSCO td 0.147 14.220 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 14.220 ntR1390
- CLMA_10_248/RSCO td 0.147 14.367 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 14.367 ntR1389
- CLMA_10_252/RSCO td 0.147 14.514 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT
- net (fanout=4) 0.000 14.514 ntR1388
- CLMA_10_256/RSCO td 0.147 14.661 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 14.661 ntR1387
- CLMA_10_260/RSCO td 0.147 14.808 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 14.808 ntR1386
- CLMA_10_264/RSCO td 0.147 14.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 14.955 ntR1385
- CLMA_10_268/RSCO td 0.147 15.102 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT
- net (fanout=3) 0.000 15.102 ntR1384
- CLMA_10_272/RSCO td 0.147 15.249 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT
- net (fanout=2) 0.000 15.249 ntR1383
- CLMA_10_276/RSCO td 0.147 15.396 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT
- net (fanout=2) 0.000 15.396 ntR1382
- CLMA_10_280/RSCO td 0.147 15.543 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT
- net (fanout=4) 0.000 15.543 ntR1381
- CLMA_10_284/RSCO td 0.147 15.690 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 15.690 ntR1380
- CLMA_10_288/RSCO td 0.147 15.837 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 15.837 ntR1379
- CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS
-
- Data arrival time 15.837 Logic Levels: 17
- Logic: 2.788ns(62.750%), Route: 1.655ns(37.250%)
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+
+ CLMA_46_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 1.497 13.180 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_34_148/RSCO td 0.147 13.327 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.327 ntR882
+ CLMA_34_152/RSCO td 0.147 13.474 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.474 ntR881
+ CLMA_34_156/RSCO td 0.147 13.621 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.621 ntR880
+ CLMA_34_160/RSCO td 0.147 13.768 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 13.768 ntR879
+ CLMA_34_164/RSCO td 0.147 13.915 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=3) 0.000 13.915 ntR878
+ CLMA_34_168/RSCO td 0.147 14.062 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 14.062 ntR877
+ CLMA_34_172/RSCO td 0.147 14.209 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 14.209 ntR876
+ CLMA_34_176/RSCO td 0.147 14.356 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 14.356 ntR875
+ CLMA_34_180/RSCO td 0.147 14.503 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 14.503 ntR874
+ CLMA_34_184/RSCO td 0.147 14.650 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 14.650 ntR873
+ CLMA_34_192/RSCO td 0.147 14.797 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 14.797 ntR872
+ CLMA_34_196/RSCO td 0.147 14.944 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=1) 0.000 14.944 ntR871
+ CLMA_34_200/RSCO td 0.147 15.091 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT
+ net (fanout=6) 0.000 15.091 ntR870
+ CLMA_34_204/RSCO td 0.147 15.238 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 15.238 ntR869
+ CLMA_34_208/RSCO td 0.147 15.385 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 15.385 ntR868
+ CLMA_34_212/RSCO td 0.147 15.532 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 15.532 ntR867
+ CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS
+
+ Data arrival time 15.532 Logic Levels: 16
+ Logic: 2.641ns(63.823%), Route: 1.497ns(36.177%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -7013,42 +7842,42 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 12.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 13.843 zoom_clk
+ net (fanout=2) 1.059 13.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 16.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 16.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.652 20.786 ntclkbufg_0
- CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/CLK
- clock pessimism 0.675 21.461
- clock uncertainty -0.150 21.311
+ net (fanout=5464) 1.531 20.665 ntclkbufg_0
+ CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.693 21.358
+ clock uncertainty -0.150 21.208
- Recovery time 0.000 21.311
+ Recovery time 0.000 21.208
- Data required time 21.311
+ Data required time 21.208
----------------------------------------------------------------------------------------------------
- Data required time 21.311
- Data arrival time 15.837
+ Data required time 21.208
+ Data arrival time 15.532
----------------------------------------------------------------------------------------------------
- Slack (MET) 5.474
+ Slack (MET) 5.676
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS
Path Group : ddrphy_clkin
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 10.786
+Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 10.665
Launch Clock Delay : 11.394
- Clock Pessimism Removal : 0.675
+ Clock Pessimism Removal : 0.693
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -7061,59 +7890,57 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-
- CLMA_70_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 1.655 13.338 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_10_224/RSCO td 0.147 13.485 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.485 ntR1395
- CLMA_10_228/RSCO td 0.147 13.632 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.632 ntR1394
- CLMA_10_232/RSCO td 0.147 13.779 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.779 ntR1393
- CLMA_10_236/RSCO td 0.147 13.926 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 13.926 ntR1392
- CLMA_10_240/RSCO td 0.147 14.073 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 14.073 ntR1391
- CLMA_10_244/RSCO td 0.147 14.220 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 14.220 ntR1390
- CLMA_10_248/RSCO td 0.147 14.367 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 14.367 ntR1389
- CLMA_10_252/RSCO td 0.147 14.514 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT
- net (fanout=4) 0.000 14.514 ntR1388
- CLMA_10_256/RSCO td 0.147 14.661 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 14.661 ntR1387
- CLMA_10_260/RSCO td 0.147 14.808 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 14.808 ntR1386
- CLMA_10_264/RSCO td 0.147 14.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 14.955 ntR1385
- CLMA_10_268/RSCO td 0.147 15.102 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT
- net (fanout=3) 0.000 15.102 ntR1384
- CLMA_10_272/RSCO td 0.147 15.249 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT
- net (fanout=2) 0.000 15.249 ntR1383
- CLMA_10_276/RSCO td 0.147 15.396 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT
- net (fanout=2) 0.000 15.396 ntR1382
- CLMA_10_280/RSCO td 0.147 15.543 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT
- net (fanout=4) 0.000 15.543 ntR1381
- CLMA_10_284/RSCO td 0.147 15.690 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 15.690 ntR1380
- CLMA_10_288/RSCO td 0.147 15.837 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 15.837 ntR1379
- CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS
-
- Data arrival time 15.837 Logic Levels: 17
- Logic: 2.788ns(62.750%), Route: 1.655ns(37.250%)
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+
+ CLMA_46_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 1.497 13.180 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_34_148/RSCO td 0.147 13.327 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.327 ntR882
+ CLMA_34_152/RSCO td 0.147 13.474 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.474 ntR881
+ CLMA_34_156/RSCO td 0.147 13.621 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.621 ntR880
+ CLMA_34_160/RSCO td 0.147 13.768 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 13.768 ntR879
+ CLMA_34_164/RSCO td 0.147 13.915 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=3) 0.000 13.915 ntR878
+ CLMA_34_168/RSCO td 0.147 14.062 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 14.062 ntR877
+ CLMA_34_172/RSCO td 0.147 14.209 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 14.209 ntR876
+ CLMA_34_176/RSCO td 0.147 14.356 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 14.356 ntR875
+ CLMA_34_180/RSCO td 0.147 14.503 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 14.503 ntR874
+ CLMA_34_184/RSCO td 0.147 14.650 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 14.650 ntR873
+ CLMA_34_192/RSCO td 0.147 14.797 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 14.797 ntR872
+ CLMA_34_196/RSCO td 0.147 14.944 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=1) 0.000 14.944 ntR871
+ CLMA_34_200/RSCO td 0.147 15.091 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT
+ net (fanout=6) 0.000 15.091 ntR870
+ CLMA_34_204/RSCO td 0.147 15.238 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 15.238 ntR869
+ CLMA_34_208/RSCO td 0.147 15.385 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 15.385 ntR868
+ CLMA_34_212/RSCO td 0.147 15.532 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 15.532 ntR867
+ CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS
+
+ Data arrival time 15.532 Logic Levels: 16
+ Logic: 2.641ns(63.823%), Route: 1.497ns(36.177%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -7124,42 +7951,42 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 12.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 13.843 zoom_clk
+ net (fanout=2) 1.059 13.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 16.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 16.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.652 20.786 ntclkbufg_0
- CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/CLK
- clock pessimism 0.675 21.461
- clock uncertainty -0.150 21.311
+ net (fanout=5464) 1.531 20.665 ntclkbufg_0
+ CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/CLK
+ clock pessimism 0.693 21.358
+ clock uncertainty -0.150 21.208
- Recovery time 0.000 21.311
+ Recovery time 0.000 21.208
- Data required time 21.311
+ Data required time 21.208
----------------------------------------------------------------------------------------------------
- Data required time 21.311
- Data arrival time 15.837
+ Data required time 21.208
+ Data arrival time 15.532
----------------------------------------------------------------------------------------------------
- Slack (MET) 5.474
+ Slack (MET) 5.676
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS
Path Group : ddrphy_clkin
Path Type : max (slow corner)
Path Class : async timing path
-Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 10.786
+Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 10.665
Launch Clock Delay : 11.394
- Clock Pessimism Removal : 0.675
+ Clock Pessimism Removal : 0.693
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -7172,59 +7999,57 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-
- CLMA_70_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 1.655 13.338 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_10_224/RSCO td 0.147 13.485 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.485 ntR1395
- CLMA_10_228/RSCO td 0.147 13.632 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.632 ntR1394
- CLMA_10_232/RSCO td 0.147 13.779 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 13.779 ntR1393
- CLMA_10_236/RSCO td 0.147 13.926 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 13.926 ntR1392
- CLMA_10_240/RSCO td 0.147 14.073 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 14.073 ntR1391
- CLMA_10_244/RSCO td 0.147 14.220 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 14.220 ntR1390
- CLMA_10_248/RSCO td 0.147 14.367 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 14.367 ntR1389
- CLMA_10_252/RSCO td 0.147 14.514 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT
- net (fanout=4) 0.000 14.514 ntR1388
- CLMA_10_256/RSCO td 0.147 14.661 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 14.661 ntR1387
- CLMA_10_260/RSCO td 0.147 14.808 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 14.808 ntR1386
- CLMA_10_264/RSCO td 0.147 14.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 14.955 ntR1385
- CLMA_10_268/RSCO td 0.147 15.102 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT
- net (fanout=3) 0.000 15.102 ntR1384
- CLMA_10_272/RSCO td 0.147 15.249 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT
- net (fanout=2) 0.000 15.249 ntR1383
- CLMA_10_276/RSCO td 0.147 15.396 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT
- net (fanout=2) 0.000 15.396 ntR1382
- CLMA_10_280/RSCO td 0.147 15.543 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT
- net (fanout=4) 0.000 15.543 ntR1381
- CLMA_10_284/RSCO td 0.147 15.690 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 15.690 ntR1380
- CLMA_10_288/RSCO td 0.147 15.837 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 15.837 ntR1379
- CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS
-
- Data arrival time 15.837 Logic Levels: 17
- Logic: 2.788ns(62.750%), Route: 1.655ns(37.250%)
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+
+ CLMA_46_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 1.497 13.180 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_34_148/RSCO td 0.147 13.327 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.327 ntR882
+ CLMA_34_152/RSCO td 0.147 13.474 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.474 ntR881
+ CLMA_34_156/RSCO td 0.147 13.621 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 13.621 ntR880
+ CLMA_34_160/RSCO td 0.147 13.768 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 13.768 ntR879
+ CLMA_34_164/RSCO td 0.147 13.915 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=3) 0.000 13.915 ntR878
+ CLMA_34_168/RSCO td 0.147 14.062 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 14.062 ntR877
+ CLMA_34_172/RSCO td 0.147 14.209 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 14.209 ntR876
+ CLMA_34_176/RSCO td 0.147 14.356 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 14.356 ntR875
+ CLMA_34_180/RSCO td 0.147 14.503 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 14.503 ntR874
+ CLMA_34_184/RSCO td 0.147 14.650 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 14.650 ntR873
+ CLMA_34_192/RSCO td 0.147 14.797 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 14.797 ntR872
+ CLMA_34_196/RSCO td 0.147 14.944 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=1) 0.000 14.944 ntR871
+ CLMA_34_200/RSCO td 0.147 15.091 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT
+ net (fanout=6) 0.000 15.091 ntR870
+ CLMA_34_204/RSCO td 0.147 15.238 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 15.238 ntR869
+ CLMA_34_208/RSCO td 0.147 15.385 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 15.385 ntR868
+ CLMA_34_212/RSCO td 0.147 15.532 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 15.532 ntR867
+ CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS
+
+ Data arrival time 15.532 Logic Levels: 16
+ Logic: 2.641ns(63.823%), Route: 1.497ns(36.177%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -7235,35 +8060,35 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 12.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 13.843 zoom_clk
+ net (fanout=2) 1.059 13.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 16.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 16.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.652 20.786 ntclkbufg_0
- CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/CLK
- clock pessimism 0.675 21.461
- clock uncertainty -0.150 21.311
+ net (fanout=5464) 1.531 20.665 ntclkbufg_0
+ CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/CLK
+ clock pessimism 0.693 21.358
+ clock uncertainty -0.150 21.208
- Recovery time 0.000 21.311
+ Recovery time 0.000 21.208
- Data required time 21.311
+ Data required time 21.208
----------------------------------------------------------------------------------------------------
- Data required time 21.311
- Data arrival time 15.837
+ Data required time 21.208
+ Data arrival time 15.532
----------------------------------------------------------------------------------------------------
- Slack (MET) 5.474
+ Slack (MET) 5.676
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS
Path Group : ddrphy_clkin
Path Type : min (slow corner)
Path Class : async timing path
@@ -7283,27 +8108,27 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 6.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.531 10.665 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- CLMA_70_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 0.488 11.375 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_66_212/RSCO td 0.105 11.480 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 11.480 ntR1484
- CLMA_66_216/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS
+ CLMA_46_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 0.346 11.233 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_38_192/RSCO td 0.105 11.338 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT
+ net (fanout=4) 0.000 11.338 ntR984
+ CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS
- Data arrival time 11.480 Logic Levels: 1
- Logic: 0.327ns(40.123%), Route: 0.488ns(59.877%)
+ Data arrival time 11.338 Logic Levels: 1
+ Logic: 0.327ns(48.588%), Route: 0.346ns(51.412%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -7314,18 +8139,18 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/CLK
+ CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/CLK
clock pessimism -0.693 10.701
clock uncertainty 0.000 10.701
@@ -7334,15 +8159,15 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 10.701
----------------------------------------------------------------------------------------------------
Data required time 10.701
- Data arrival time 11.480
+ Data arrival time 11.338
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.779
+ Slack (MET) 0.637
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS
Path Group : ddrphy_clkin
Path Type : min (slow corner)
Path Class : async timing path
@@ -7362,27 +8187,27 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 6.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.531 10.665 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- CLMA_70_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 0.488 11.375 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_66_212/RSCO td 0.105 11.480 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 11.480 ntR1484
- CLMA_66_216/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS
+ CLMA_46_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 0.346 11.233 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_38_192/RSCO td 0.105 11.338 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT
+ net (fanout=4) 0.000 11.338 ntR984
+ CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS
- Data arrival time 11.480 Logic Levels: 1
- Logic: 0.327ns(40.123%), Route: 0.488ns(59.877%)
+ Data arrival time 11.338 Logic Levels: 1
+ Logic: 0.327ns(48.588%), Route: 0.346ns(51.412%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -7393,18 +8218,18 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/CLK
+ CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/CLK
clock pessimism -0.693 10.701
clock uncertainty 0.000 10.701
@@ -7413,15 +8238,15 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 10.701
----------------------------------------------------------------------------------------------------
Data required time 10.701
- Data arrival time 11.480
+ Data arrival time 11.338
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.779
+ Slack (MET) 0.637
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS
Path Group : ddrphy_clkin
Path Type : min (slow corner)
Path Class : async timing path
@@ -7441,27 +8266,27 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.758 2.688 _N69
PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.059 3.843 zoom_clk
+ net (fanout=2) 1.059 3.843 ddr_clk
USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.102 6.733 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 6.982 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.531 10.665 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- CLMA_70_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 0.488 11.375 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_66_212/RSCO td 0.105 11.480 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 11.480 ntR1484
- CLMA_66_216/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS
+ CLMA_46_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 0.346 11.233 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_38_192/RSCO td 0.105 11.338 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT
+ net (fanout=4) 0.000 11.338 ntR984
+ CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS
- Data arrival time 11.480 Logic Levels: 1
- Logic: 0.327ns(40.123%), Route: 0.488ns(59.877%)
+ Data arrival time 11.338 Logic Levels: 1
+ Logic: 0.327ns(48.588%), Route: 0.346ns(51.412%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -7472,18 +8297,18 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/CLK
+ CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/CLK
clock pessimism -0.693 10.701
clock uncertainty 0.000 10.701
@@ -7492,14 +8317,14 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 10.701
----------------------------------------------------------------------------------------------------
Data required time 10.701
- Data arrival time 11.480
+ Data arrival time 11.338
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.779
+ Slack (MET) 0.637
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/CLK
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK
Endpoint : mem_rst_n (port)
Path Group : **default**
Path Type : max (slow corner)
@@ -7516,37 +8341,37 @@ Path Class : combinational timing path
IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.787 3.103 _N69
PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 1.078 4.282 zoom_clk
+ net (fanout=2) 1.078 4.282 ddr_clk
USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 1.121 7.270 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 7.618 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 1.585 11.394 ntclkbufg_0
- CLMS_46_173/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/CLK
-
- CLMS_46_173/Q1 tco 0.289 11.683 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/Q
- net (fanout=575) 2.425 14.108 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done
- CLMS_18_317/Y0 td 0.196 14.304 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm/Z
- net (fanout=1) 1.113 15.417 nt_mem_rst_n
- IOL_7_369/DO td 0.139 15.556 f mem_rst_n_obuf/opit_1/O
- net (fanout=1) 0.000 15.556 mem_rst_n_obuf/ntO
- IOBS_LR_0_368/PAD td 3.903 19.459 f mem_rst_n_obuf/opit_0/O
- net (fanout=1) 0.096 19.555 mem_rst_n
+ CLMA_46_156/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK
+
+ CLMA_46_156/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/Q
+ net (fanout=1) 0.760 12.443 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_rst
+ CLMS_34_173/Y3 td 0.197 12.640 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm/Z
+ net (fanout=1) 2.439 15.079 nt_mem_rst_n
+ IOL_7_369/DO td 0.139 15.218 f mem_rst_n_obuf/opit_1/O
+ net (fanout=1) 0.000 15.218 mem_rst_n_obuf/ntO
+ IOBS_LR_0_368/PAD td 3.903 19.121 f mem_rst_n_obuf/opit_0/O
+ net (fanout=1) 0.096 19.217 mem_rst_n
C1 f mem_rst_n (port)
- Data arrival time 19.555 Logic Levels: 3
- Logic: 4.527ns(55.471%), Route: 3.634ns(44.529%)
+ Data arrival time 19.217 Logic Levels: 3
+ Logic: 4.528ns(57.881%), Route: 3.295ns(42.119%)
====================================================================================================
====================================================================================================
-Startpoint : param_manager_inst/index[1]/opit_0_L5Q_perm/CLK
-Endpoint : led[2] (port)
+Startpoint : param_manager_inst/index[0]/opit_0_L5Q_perm/CLK
+Endpoint : led[1] (port)
Path Group : **default**
Path Type : max (slow corner)
Path Class : combinational timing path
@@ -7564,25 +8389,25 @@ Path Class : combinational timing path
IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.585 10.030 gmii_clk
- CLMA_194_168/CLK r param_manager_inst/index[1]/opit_0_L5Q_perm/CLK
-
- CLMA_194_168/Q3 tco 0.286 10.316 f param_manager_inst/index[1]/opit_0_L5Q_perm/Q
- net (fanout=19) 3.743 14.059 nt_led[2]
- IOL_19_373/DO td 0.139 14.198 f led_obuf[2]/opit_1/O
- net (fanout=1) 0.000 14.198 led_obuf[2]/ntO
- IOBS_TB_17_376/PAD td 3.853 18.051 f led_obuf[2]/opit_0/O
- net (fanout=1) 0.107 18.158 led[2]
- A2 f led[2] (port)
+ net (fanout=1862) 1.585 10.030 gmii_clk
+ CLMA_210_205/CLK r param_manager_inst/index[0]/opit_0_L5Q_perm/CLK
- Data arrival time 18.158 Logic Levels: 2
- Logic: 4.278ns(52.633%), Route: 3.850ns(47.367%)
+ CLMA_210_205/Q0 tco 0.287 10.317 f param_manager_inst/index[0]/opit_0_L5Q_perm/Q
+ net (fanout=20) 3.794 14.111 nt_led[1]
+ IOL_19_374/DO td 0.139 14.250 f led_obuf[1]/opit_1/O
+ net (fanout=1) 0.000 14.250 led_obuf[1]/ntO
+ IOBD_16_376/PAD td 3.853 18.103 f led_obuf[1]/opit_0/O
+ net (fanout=1) 0.109 18.212 led[1]
+ B2 f led[1] (port)
+
+ Data arrival time 18.212 Logic Levels: 2
+ Logic: 4.279ns(52.298%), Route: 3.903ns(47.702%)
====================================================================================================
====================================================================================================
-Startpoint : param_manager_inst/index[3]/opit_0_L5Q_perm/CLK
-Endpoint : led[4] (port)
+Startpoint : param_manager_inst/index[1]/opit_0_L5Q_perm/CLK
+Endpoint : led[2] (port)
Path Group : **default**
Path Type : max (slow corner)
Path Class : combinational timing path
@@ -7600,19 +8425,19 @@ Path Class : combinational timing path
IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 1.585 10.030 gmii_clk
- CLMA_194_168/CLK r param_manager_inst/index[3]/opit_0_L5Q_perm/CLK
-
- CLMA_194_168/Q1 tco 0.289 10.319 f param_manager_inst/index[3]/opit_0_L5Q_perm/Q
- net (fanout=18) 3.675 13.994 nt_led[4]
- IOL_35_373/DO td 0.139 14.133 f led_obuf[4]/opit_1/O
- net (fanout=1) 0.000 14.133 led_obuf[4]/ntO
- IOBS_TB_33_376/PAD td 3.853 17.986 f led_obuf[4]/opit_0/O
- net (fanout=1) 0.087 18.073 led[4]
- A3 f led[4] (port)
+ net (fanout=1862) 1.585 10.030 gmii_clk
+ CLMA_210_205/CLK r param_manager_inst/index[1]/opit_0_L5Q_perm/CLK
+
+ CLMA_210_205/Q3 tco 0.286 10.316 f param_manager_inst/index[1]/opit_0_L5Q_perm/Q
+ net (fanout=19) 3.663 13.979 nt_led[2]
+ IOL_19_373/DO td 0.139 14.118 f led_obuf[2]/opit_1/O
+ net (fanout=1) 0.000 14.118 led_obuf[2]/ntO
+ IOBS_TB_17_376/PAD td 3.853 17.971 f led_obuf[2]/opit_0/O
+ net (fanout=1) 0.107 18.078 led[2]
+ A2 f led[2] (port)
- Data arrival time 18.073 Logic Levels: 2
- Logic: 4.281ns(53.226%), Route: 3.762ns(46.774%)
+ Data arrival time 18.078 Logic Levels: 2
+ Logic: 4.278ns(53.156%), Route: 3.770ns(46.844%)
====================================================================================================
====================================================================================================
@@ -7685,35 +8510,35 @@ Path Class : combinational timing path
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 5.052 5.950 0.898 Low Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 5.052 5.950 0.898 High Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 5.330 5.950 0.620 High Pulse Width CLMS_146_9/CLK u_ov5640/cmos1_8_16bit/de_in0/opit_0/CLK
+ 5.052 5.950 0.898 Low Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 5.052 5.950 0.898 High Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 5.330 5.950 0.620 Low Pulse Width CLMS_134_25/CLK u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm/CLK
====================================================================================================
{cmos2_pclk} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 5.052 5.950 0.898 Low Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 5.052 5.950 0.898 High Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 5.330 5.950 0.620 Low Pulse Width CLMS_150_41/CLK u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q/CLK
+ 5.052 5.950 0.898 Low Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 5.052 5.950 0.898 High Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 5.330 5.950 0.620 High Pulse Width CLMS_74_17/CLK u_ov5640/cmos2_8_16bit/de_in0/opit_0/CLK
====================================================================================================
{hdmi_in_clk} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 2.435 3.333 0.898 Low Pulse Width DRM_82_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 2.435 3.333 0.898 High Pulse Width DRM_82_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 2.435 3.333 0.898 High Pulse Width DRM_54_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 2.435 3.333 0.898 Low Pulse Width DRM_82_128/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 2.435 3.333 0.898 High Pulse Width DRM_82_128/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 2.435 3.333 0.898 Low Pulse Width DRM_82_88/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0]
====================================================================================================
{eth_rxc} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 2.483 4.000 1.517 High Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK
2.483 4.000 1.517 Low Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK
+ 2.483 4.000 1.517 High Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK
2.483 4.000 1.517 Low Pulse Width IOL_311_374/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft1/opit_1_IOL/SYSCLK
====================================================================================================
@@ -7721,63 +8546,72 @@ Path Class : combinational timing path
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 8.862 10.000 1.138 High Pulse Width APM_106_116/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK
- 8.862 10.000 1.138 Low Pulse Width APM_106_116/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK
- 8.862 10.000 1.138 High Pulse Width APM_106_104/CLK u_rotate_image/u_rotate_mult1/N2/gopapm/CLK
+ 8.862 10.000 1.138 Low Pulse Width APM_206_228/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK
+ 8.862 10.000 1.138 High Pulse Width APM_206_228/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK
+ 8.862 10.000 1.138 High Pulse Width APM_206_216/CLK u_rotate_image/u_rotate_mult1/N2/gopapm/CLK
====================================================================================================
{clk_200m} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 1.362 2.500 1.138 Low Pulse Width APM_206_228/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK
- 1.362 2.500 1.138 High Pulse Width APM_206_228/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK
- 1.362 2.500 1.138 Low Pulse Width APM_206_140/CLK u_zoom_image/mult_fra0_0/N2/gopapm/CLK
+ 1.880 2.500 0.620 Low Pulse Width CLMS_34_181/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK
+ 1.880 2.500 0.620 High Pulse Width CLMS_34_181/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK
+ 1.880 2.500 0.620 High Pulse Width CLMS_34_193/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm/CLK
====================================================================================================
{clk_25m} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 19.580 20.000 0.420 High Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
- 19.580 20.000 0.420 Low Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
- 19.580 20.000 0.420 High Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
+ 19.380 20.000 0.620 High Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+ 19.380 20.000 0.620 Low Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+ 19.380 20.000 0.620 High Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
====================================================================================================
{clk_10m} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 49.102 50.000 0.898 Low Pulse Width DRM_234_108/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
- 49.102 50.000 0.898 High Pulse Width DRM_234_108/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
- 49.102 50.000 0.898 Low Pulse Width DRM_234_108/CLKB[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0]
+ 49.102 50.000 0.898 Low Pulse Width DRM_234_316/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
+ 49.102 50.000 0.898 High Pulse Width DRM_234_316/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
+ 49.102 50.000 0.898 Low Pulse Width DRM_234_316/CLKB[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0]
+====================================================================================================
+
+{clk_1080p60Hz} Minimum Pulse Width :
+****************************************************************************************************
+ Slack Actual Width Require Width Type Location Pin
+----------------------------------------------------------------------------------------------------
+ 2.230 3.368 1.138 High Pulse Width APM_206_28/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK
+ 2.230 3.368 1.138 Low Pulse Width APM_206_28/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK
+ 2.230 3.368 1.138 High Pulse Width APM_206_264/CLK u_zoom_image/mult_fra0_0/N2/gopapm/CLK
====================================================================================================
{clk_720p60Hz} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 5.598 6.736 1.138 High Pulse Width APM_258_140/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK
- 5.598 6.736 1.138 High Pulse Width APM_258_128/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm/CLK
- 5.599 6.737 1.138 Low Pulse Width APM_258_140/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK
+ 5.598 6.736 1.138 High Pulse Width APM_258_216/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK
+ 5.598 6.736 1.138 High Pulse Width APM_258_204/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm/CLK
+ 5.599 6.737 1.138 Low Pulse Width APM_258_216/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK
====================================================================================================
{clk_20k} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 24999.102 25000.000 0.898 Low Pulse Width DRM_178_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
- 24999.102 25000.000 0.898 High Pulse Width DRM_178_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
- 24999.102 25000.000 0.898 Low Pulse Width DRM_178_4/CLKB[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
+ 24999.102 25000.000 0.898 Low Pulse Width DRM_142_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
+ 24999.102 25000.000 0.898 High Pulse Width DRM_142_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
+ 24999.102 25000.000 0.898 Low Pulse Width DRM_142_4/CLKB[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
====================================================================================================
{ddrphy_clkin} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 3.100 5.000 1.900 High Pulse Width CLMS_38_109/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK
- 3.100 5.000 1.900 Low Pulse Width CLMS_38_109/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK
- 3.100 5.000 1.900 High Pulse Width CLMS_34_113/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK
+ 3.100 5.000 1.900 Low Pulse Width CLMS_38_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK
+ 3.100 5.000 1.900 High Pulse Width CLMS_38_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK
+ 3.100 5.000 1.900 Low Pulse Width CLMS_42_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK
====================================================================================================
{ioclk0} Minimum Pulse Width :
@@ -7820,8 +8654,8 @@ Fast Corner
****************************************************************************************************
====================================================================================================
-Startpoint : cmos1_data[4] (port)
-Endpoint : u_ov5640/cmos1_d_d0[4]/opit_0/D
+Startpoint : cmos1_href (port)
+Endpoint : u_ov5640/cmos1_href_d0/opit_0/D
Path Group : cmos1_pclk
Path Type : max (fast corner)
Path Class : sequential timing path
@@ -7836,16 +8670,16 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Clock cmos1_pclk (rising edge) 0.000 0.000 r
Input external delay 1.000 1.000 f
- W11 0.000 1.000 f cmos1_data[4] (port)
- net (fanout=1) 0.041 1.041 cmos1_data[4]
- IOBS_TB_132_0/DIN td 1.049 2.090 f cmos1_data_ibuf[4]/opit_0/O
- net (fanout=1) 0.000 2.090 cmos1_data_ibuf[4]/ntD
- IOL_135_5/RX_DATA_DD td 0.097 2.187 f cmos1_data_ibuf[4]/opit_1/OUT
- net (fanout=1) 5.898 8.085 nt_cmos1_data[4]
- CLMS_134_13/AD f u_ov5640/cmos1_d_d0[4]/opit_0/D
+ AB10 0.000 1.000 f cmos1_href (port)
+ net (fanout=1) 0.063 1.063 cmos1_href
+ IOBR_TB_148_0/DIN td 0.918 1.981 f cmos1_href_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.981 cmos1_href_ibuf/ntD
+ IOL_151_5/RX_DATA_DD td 0.097 2.078 f cmos1_href_ibuf/opit_1/OUT
+ net (fanout=1) 6.241 8.319 nt_cmos1_href
+ CLMA_150_12/M1 f u_ov5640/cmos1_href_d0/opit_0/D
- Data arrival time 8.085 Logic Levels: 2
- Logic: 1.146ns(16.175%), Route: 5.939ns(83.825%)
+ Data arrival time 8.319 Logic Levels: 2
+ Logic: 1.015ns(13.868%), Route: 6.304ns(86.132%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 11.900 11.900 r
@@ -7855,26 +8689,26 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 12.711 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.038 12.749 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 1.428 14.177 _N64
- USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 15.072 ntclkbufg_5
- CLMS_134_13/CLK r u_ov5640/cmos1_d_d0[4]/opit_0/CLK
+ USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 0.895 15.072 ntclkbufg_6
+ CLMA_150_12/CLK r u_ov5640/cmos1_href_d0/opit_0/CLK
clock pessimism 0.000 15.072
clock uncertainty -0.250 14.822
- Setup time 0.024 14.846
+ Setup time -0.068 14.754
- Data required time 14.846
+ Data required time 14.754
----------------------------------------------------------------------------------------------------
- Data required time 14.846
- Data arrival time 8.085
+ Data required time 14.754
+ Data arrival time 8.319
----------------------------------------------------------------------------------------------------
- Slack (MET) 6.761
+ Slack (MET) 6.435
====================================================================================================
====================================================================================================
-Startpoint : cmos1_href (port)
-Endpoint : u_ov5640/cmos1_href_d0/opit_0/D
+Startpoint : cmos1_data[0] (port)
+Endpoint : u_ov5640/cmos1_d_d0[0]/opit_0/D
Path Group : cmos1_pclk
Path Type : max (fast corner)
Path Class : sequential timing path
@@ -7889,16 +8723,16 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Clock cmos1_pclk (rising edge) 0.000 0.000 r
Input external delay 1.000 1.000 f
- AB10 0.000 1.000 f cmos1_href (port)
- net (fanout=1) 0.063 1.063 cmos1_href
- IOBR_TB_148_0/DIN td 0.918 1.981 f cmos1_href_ibuf/opit_0/O
- net (fanout=1) 0.000 1.981 cmos1_href_ibuf/ntD
- IOL_151_5/RX_DATA_DD td 0.097 2.078 f cmos1_href_ibuf/opit_1/OUT
- net (fanout=1) 5.930 8.008 nt_cmos1_href
- CLMS_146_9/AD f u_ov5640/cmos1_href_d0/opit_0/D
+ V11 0.000 1.000 f cmos1_data[0] (port)
+ net (fanout=1) 0.053 1.053 cmos1_data[0]
+ IOBD_133_0/DIN td 1.049 2.102 f cmos1_data_ibuf[0]/opit_0/O
+ net (fanout=1) 0.000 2.102 cmos1_data_ibuf[0]/ntD
+ IOL_135_6/RX_DATA_DD td 0.097 2.199 f cmos1_data_ibuf[0]/opit_1/OUT
+ net (fanout=1) 5.534 7.733 nt_cmos1_data[0]
+ CLMS_134_45/CD f u_ov5640/cmos1_d_d0[0]/opit_0/D
- Data arrival time 8.008 Logic Levels: 2
- Logic: 1.015ns(14.483%), Route: 5.993ns(85.517%)
+ Data arrival time 7.733 Logic Levels: 2
+ Logic: 1.146ns(17.021%), Route: 5.587ns(82.979%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 11.900 11.900 r
@@ -7908,9 +8742,9 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 12.711 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.038 12.749 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 1.428 14.177 _N64
- USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 15.072 ntclkbufg_5
- CLMS_146_9/CLK r u_ov5640/cmos1_href_d0/opit_0/CLK
+ USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 0.895 15.072 ntclkbufg_6
+ CLMS_134_45/CLK r u_ov5640/cmos1_d_d0[0]/opit_0/CLK
clock pessimism 0.000 15.072
clock uncertainty -0.250 14.822
@@ -7919,15 +8753,15 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 14.846
----------------------------------------------------------------------------------------------------
Data required time 14.846
- Data arrival time 8.008
+ Data arrival time 7.733
----------------------------------------------------------------------------------------------------
- Slack (MET) 6.838
+ Slack (MET) 7.113
====================================================================================================
====================================================================================================
-Startpoint : cmos1_data[5] (port)
-Endpoint : u_ov5640/cmos1_d_d0[5]/opit_0/D
+Startpoint : cmos1_data[6] (port)
+Endpoint : u_ov5640/cmos1_d_d0[6]/opit_0/D
Path Group : cmos1_pclk
Path Type : max (fast corner)
Path Class : sequential timing path
@@ -7942,18 +8776,16 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Clock cmos1_pclk (rising edge) 0.000 0.000 r
Input external delay 1.000 1.000 f
- AB11 0.000 1.000 f cmos1_data[5] (port)
- net (fanout=1) 0.077 1.077 cmos1_data[5]
- IOBS_TB_156_0/DIN td 1.049 2.126 f cmos1_data_ibuf[5]/opit_0/O
- net (fanout=1) 0.000 2.126 cmos1_data_ibuf[5]/ntD
- IOL_159_5/RX_DATA_DD td 0.097 2.223 f cmos1_data_ibuf[5]/opit_1/OUT
- net (fanout=1) 1.648 3.871 nt_cmos1_data[5]
- CLMS_322_9/Y6CD td 0.103 3.974 f CLKROUTE_0/Z
- net (fanout=1) 3.866 7.840 ntR3901
- CLMS_146_9/M0 f u_ov5640/cmos1_d_d0[5]/opit_0/D
+ AA10 0.000 1.000 f cmos1_data[6] (port)
+ net (fanout=1) 0.080 1.080 cmos1_data[6]
+ IOBD_149_0/DIN td 1.049 2.129 f cmos1_data_ibuf[6]/opit_0/O
+ net (fanout=1) 0.000 2.129 cmos1_data_ibuf[6]/ntD
+ IOL_151_6/RX_DATA_DD td 0.097 2.226 f cmos1_data_ibuf[6]/opit_1/OUT
+ net (fanout=1) 5.291 7.517 nt_cmos1_data[6]
+ CLMS_150_41/M1 f u_ov5640/cmos1_d_d0[6]/opit_0/D
- Data arrival time 7.840 Logic Levels: 3
- Logic: 1.249ns(18.260%), Route: 5.591ns(81.740%)
+ Data arrival time 7.517 Logic Levels: 2
+ Logic: 1.146ns(17.585%), Route: 5.371ns(82.415%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 11.900 11.900 r
@@ -7963,9 +8795,9 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 12.711 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.038 12.749 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 1.428 14.177 _N64
- USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 15.072 ntclkbufg_5
- CLMS_146_9/CLK r u_ov5640/cmos1_d_d0[5]/opit_0/CLK
+ USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 0.895 15.072 ntclkbufg_6
+ CLMS_150_41/CLK r u_ov5640/cmos1_d_d0[6]/opit_0/CLK
clock pessimism 0.000 15.072
clock uncertainty -0.250 14.822
@@ -7974,22 +8806,22 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 14.754
----------------------------------------------------------------------------------------------------
Data required time 14.754
- Data arrival time 7.840
+ Data arrival time 7.517
----------------------------------------------------------------------------------------------------
- Slack (MET) 6.914
+ Slack (MET) 7.237
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/cmos1_8_16bit/image_data0[5]/opit_0/CLK
-Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[5]
+Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK
+Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0
Path Group : cmos1_pclk
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 3.375
Launch Clock Delay : 3.172
- Clock Pessimism Removal : -0.184
+ Clock Pessimism Removal : -0.188
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -8001,16 +8833,16 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 0.811 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.038 0.849 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 1.428 2.277 _N64
- USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 3.172 ntclkbufg_5
- CLMS_146_33/CLK r u_ov5640/cmos1_8_16bit/image_data0[5]/opit_0/CLK
+ USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 0.895 3.172 ntclkbufg_6
+ CLMA_138_56/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK
- CLMS_146_33/Q2 tco 0.180 3.352 f u_ov5640/cmos1_8_16bit/image_data0[5]/opit_0/Q
- net (fanout=1) 0.266 3.618 u_ov5640/cmos1_d_16bit [5]
- DRM_142_24/DA0[5] f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[5]
+ CLMA_138_56/Q1 tco 0.180 3.352 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Q1
+ net (fanout=5) 0.062 3.414 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [5]
+ CLMA_138_57/C0 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0
- Data arrival time 3.618 Logic Levels: 0
- Logic: 0.180ns(40.359%), Route: 0.266ns(59.641%)
+ Data arrival time 3.414 Logic Levels: 0
+ Logic: 0.180ns(74.380%), Route: 0.062ns(25.620%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 0.000 0.000 r
@@ -8020,33 +8852,33 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 0.937 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.058 0.995 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 1.455 2.450 _N64
- USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 0.925 3.375 ntclkbufg_5
- DRM_142_24/CLKA[0] r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- clock pessimism -0.184 3.191
- clock uncertainty 0.200 3.391
+ USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 0.925 3.375 ntclkbufg_6
+ CLMA_138_57/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK
+ clock pessimism -0.188 3.187
+ clock uncertainty 0.200 3.387
- Hold time 0.119 3.510
+ Hold time -0.077 3.310
- Data required time 3.510
+ Data required time 3.310
----------------------------------------------------------------------------------------------------
- Data required time 3.510
- Data arrival time 3.618
+ Data required time 3.310
+ Data arrival time 3.414
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.108
+ Slack (MET) 0.104
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK
-Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/D
+Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK
+Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0
Path Group : cmos1_pclk
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 3.375
Launch Clock Delay : 3.172
- Clock Pessimism Removal : -0.184
+ Clock Pessimism Removal : -0.188
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -8058,16 +8890,16 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 0.811 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.038 0.849 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 1.428 2.277 _N64
- USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 3.172 ntclkbufg_5
- CLMA_138_24/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK
+ USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 0.895 3.172 ntclkbufg_6
+ CLMA_138_60/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK
- CLMA_138_24/Q0 tco 0.182 3.354 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/Q
- net (fanout=1) 0.136 3.490 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr1 [1]
- CLMA_134_28/M2 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/D
+ CLMA_138_60/Q0 tco 0.179 3.351 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0
+ net (fanout=5) 0.062 3.413 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [8]
+ CLMA_138_61/A0 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0
- Data arrival time 3.490 Logic Levels: 0
- Logic: 0.182ns(57.233%), Route: 0.136ns(42.767%)
+ Data arrival time 3.413 Logic Levels: 0
+ Logic: 0.179ns(74.274%), Route: 0.062ns(25.726%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 0.000 0.000 r
@@ -8077,26 +8909,26 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 0.937 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.058 0.995 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 1.455 2.450 _N64
- USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 0.925 3.375 ntclkbufg_5
- CLMA_134_28/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK
- clock pessimism -0.184 3.191
- clock uncertainty 0.200 3.391
+ USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 0.925 3.375 ntclkbufg_6
+ CLMA_138_61/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK
+ clock pessimism -0.188 3.187
+ clock uncertainty 0.200 3.387
- Hold time -0.011 3.380
+ Hold time -0.078 3.309
- Data required time 3.380
+ Data required time 3.309
----------------------------------------------------------------------------------------------------
- Data required time 3.380
- Data arrival time 3.490
+ Data required time 3.309
+ Data arrival time 3.413
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.110
+ Slack (MET) 0.104
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/cmos1_8_16bit/pdata_i2[0]/opit_0/CLK
-Endpoint : u_ov5640/cmos1_8_16bit/image_data0[8]/opit_0/D
+Startpoint : u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK
+Endpoint : u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D
Path Group : cmos1_pclk
Path Type : min (fast corner)
Path Class : sequential timing path
@@ -8115,16 +8947,16 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 0.811 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.038 0.849 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 1.428 2.277 _N64
- USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 3.172 ntclkbufg_5
- CLMA_138_25/CLK r u_ov5640/cmos1_8_16bit/pdata_i2[0]/opit_0/CLK
+ USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 0.895 3.172 ntclkbufg_6
+ CLMA_138_44/CLK r u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK
- CLMA_138_25/Q3 tco 0.182 3.354 r u_ov5640/cmos1_8_16bit/pdata_i2[0]/opit_0/Q
- net (fanout=1) 0.133 3.487 u_ov5640/cmos1_8_16bit/pdata_i2 [0]
- CLMA_138_29/M1 r u_ov5640/cmos1_8_16bit/image_data0[8]/opit_0/D
+ CLMA_138_44/Y0 tco 0.228 3.400 f u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/Q
+ net (fanout=1) 0.135 3.535 u_ov5640/cmos1_8_16bit/pdata_i2 [4]
+ CLMA_138_45/AD f u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D
- Data arrival time 3.487 Logic Levels: 0
- Logic: 0.182ns(57.778%), Route: 0.133ns(42.222%)
+ Data arrival time 3.535 Logic Levels: 0
+ Logic: 0.228ns(62.810%), Route: 0.135ns(37.190%)
----------------------------------------------------------------------------------------------------
Clock cmos1_pclk (rising edge) 0.000 0.000 r
@@ -8134,31 +8966,31 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 0.937 cmos1_pclk_ibuf/ntD
IOL_171_6/INCK td 0.058 0.995 r cmos1_pclk_ibuf/opit_1/INCK
net (fanout=1) 1.455 2.450 _N64
- USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_5/gopclkbufg/CLKOUT
- net (fanout=118) 0.925 3.375 ntclkbufg_5
- CLMA_138_29/CLK r u_ov5640/cmos1_8_16bit/image_data0[8]/opit_0/CLK
+ USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_6/gopclkbufg/CLKOUT
+ net (fanout=118) 0.925 3.375 ntclkbufg_6
+ CLMA_138_45/CLK r u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/CLK
clock pessimism -0.188 3.187
clock uncertainty 0.200 3.387
- Hold time -0.011 3.376
+ Hold time 0.040 3.427
- Data required time 3.376
+ Data required time 3.427
----------------------------------------------------------------------------------------------------
- Data required time 3.376
- Data arrival time 3.487
+ Data required time 3.427
+ Data arrival time 3.535
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.111
+ Slack (MET) 0.108
====================================================================================================
====================================================================================================
-Startpoint : cmos2_data[7] (port)
-Endpoint : u_ov5640/cmos2_d_d0[7]/opit_0/D
+Startpoint : cmos2_data[6] (port)
+Endpoint : u_ov5640/cmos2_d_d0[6]/opit_0/D
Path Group : cmos2_pclk
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.512
+Clock Skew : 3.511 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.511
Launch Clock Delay : 0.000
Clock Pessimism Removal : 0.000
@@ -8168,16 +9000,16 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Clock cmos2_pclk (rising edge) 0.000 0.000 r
Input external delay 1.000 1.000 f
- AB9 0.000 1.000 f cmos2_data[7] (port)
- net (fanout=1) 0.080 1.080 cmos2_data[7]
- IOBS_TB_128_0/DIN td 1.049 2.129 f cmos2_data_ibuf[7]/opit_0/O
- net (fanout=1) 0.000 2.129 cmos2_data_ibuf[7]/ntD
- IOL_131_5/RX_DATA_DD td 0.097 2.226 f cmos2_data_ibuf[7]/opit_1/OUT
- net (fanout=1) 6.776 9.002 nt_cmos2_data[7]
- CLMS_130_37/M2 f u_ov5640/cmos2_d_d0[7]/opit_0/D
+ Y9 0.000 1.000 f cmos2_data[6] (port)
+ net (fanout=1) 0.078 1.078 cmos2_data[6]
+ IOBD_129_0/DIN td 1.049 2.127 f cmos2_data_ibuf[6]/opit_0/O
+ net (fanout=1) 0.000 2.127 cmos2_data_ibuf[6]/ntD
+ IOL_131_6/RX_DATA_DD td 0.097 2.224 f cmos2_data_ibuf[6]/opit_1/OUT
+ net (fanout=1) 7.000 9.224 nt_cmos2_data[6]
+ CLMA_138_8/M1 f u_ov5640/cmos2_d_d0[6]/opit_0/D
- Data arrival time 9.002 Logic Levels: 2
- Logic: 1.146ns(14.321%), Route: 6.856ns(85.679%)
+ Data arrival time 9.224 Logic Levels: 2
+ Logic: 1.146ns(13.935%), Route: 7.078ns(86.065%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 11.900 11.900 r
@@ -8186,21 +9018,21 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 0.735 12.706 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 12.706 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.066 12.772 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 1.745 14.517 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 14.517 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 15.412 ntclkbufg_6
- CLMS_130_37/CLK r u_ov5640/cmos2_d_d0[7]/opit_0/CLK
- clock pessimism 0.000 15.412
- clock uncertainty -0.250 15.162
+ net (fanout=1) 1.744 14.516 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 14.516 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 0.895 15.411 ntclkbufg_7
+ CLMA_138_8/CLK r u_ov5640/cmos2_d_d0[6]/opit_0/CLK
+ clock pessimism 0.000 15.411
+ clock uncertainty -0.250 15.161
- Setup time -0.068 15.094
+ Setup time -0.068 15.093
- Data required time 15.094
+ Data required time 15.093
----------------------------------------------------------------------------------------------------
- Data required time 15.094
- Data arrival time 9.002
+ Data required time 15.093
+ Data arrival time 9.224
----------------------------------------------------------------------------------------------------
- Slack (MET) 6.092
+ Slack (MET) 5.869
====================================================================================================
====================================================================================================
@@ -8210,8 +9042,8 @@ Endpoint : u_ov5640/cmos2_d_d0[5]/opit_0/D
Path Group : cmos2_pclk
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.512
+Clock Skew : 3.511 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.511
Launch Clock Delay : 0.000
Clock Pessimism Removal : 0.000
@@ -8226,11 +9058,13 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBS_TB_116_0/DIN td 1.049 2.133 f cmos2_data_ibuf[5]/opit_0/O
net (fanout=1) 0.000 2.133 cmos2_data_ibuf[5]/ntD
IOL_119_5/RX_DATA_DD td 0.097 2.230 f cmos2_data_ibuf[5]/opit_1/OUT
- net (fanout=1) 6.531 8.761 nt_cmos2_data[5]
- CLMA_134_40/M0 f u_ov5640/cmos2_d_d0[5]/opit_0/D
+ net (fanout=1) 1.068 3.298 nt_cmos2_data[5]
+ CLMS_198_49/Y6CD td 0.103 3.401 f CLKROUTE_0/Z
+ net (fanout=1) 5.822 9.223 ntR3940
+ CLMA_138_8/M0 f u_ov5640/cmos2_d_d0[5]/opit_0/D
- Data arrival time 8.761 Logic Levels: 2
- Logic: 1.146ns(14.766%), Route: 6.615ns(85.234%)
+ Data arrival time 9.223 Logic Levels: 3
+ Logic: 1.249ns(15.189%), Route: 6.974ns(84.811%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 11.900 11.900 r
@@ -8239,32 +9073,32 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 0.735 12.706 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 12.706 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.066 12.772 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 1.745 14.517 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 14.517 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 15.412 ntclkbufg_6
- CLMA_134_40/CLK r u_ov5640/cmos2_d_d0[5]/opit_0/CLK
- clock pessimism 0.000 15.412
- clock uncertainty -0.250 15.162
+ net (fanout=1) 1.744 14.516 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 14.516 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 0.895 15.411 ntclkbufg_7
+ CLMA_138_8/CLK r u_ov5640/cmos2_d_d0[5]/opit_0/CLK
+ clock pessimism 0.000 15.411
+ clock uncertainty -0.250 15.161
- Setup time -0.068 15.094
+ Setup time -0.068 15.093
- Data required time 15.094
+ Data required time 15.093
----------------------------------------------------------------------------------------------------
- Data required time 15.094
- Data arrival time 8.761
+ Data required time 15.093
+ Data arrival time 9.223
----------------------------------------------------------------------------------------------------
- Slack (MET) 6.333
+ Slack (MET) 5.870
====================================================================================================
====================================================================================================
-Startpoint : cmos2_data[6] (port)
-Endpoint : u_ov5640/cmos2_d_d0[6]/opit_0/D
+Startpoint : cmos2_href (port)
+Endpoint : u_ov5640/cmos2_href_d0/opit_0/D
Path Group : cmos2_pclk
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.512
+Clock Skew : 3.550 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.550
Launch Clock Delay : 0.000
Clock Pessimism Removal : 0.000
@@ -8274,18 +9108,20 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Clock cmos2_pclk (rising edge) 0.000 0.000 r
Input external delay 1.000 1.000 f
- Y9 0.000 1.000 f cmos2_data[6] (port)
- net (fanout=1) 0.078 1.078 cmos2_data[6]
- IOBD_129_0/DIN td 1.049 2.127 f cmos2_data_ibuf[6]/opit_0/O
- net (fanout=1) 0.000 2.127 cmos2_data_ibuf[6]/ntD
- IOL_131_6/RX_DATA_DD td 0.097 2.224 f cmos2_data_ibuf[6]/opit_1/OUT
- net (fanout=1) 0.831 3.055 nt_cmos2_data[6]
- CLMA_94_8/Y6AB td 0.101 3.156 f CLKROUTE_2/Z
- net (fanout=1) 5.292 8.448 ntR3903
- CLMA_134_40/M1 f u_ov5640/cmos2_d_d0[6]/opit_0/D
+ AB5 0.000 1.000 f cmos2_href (port)
+ net (fanout=1) 0.093 1.093 cmos2_href
+ IOBS_TB_32_0/DIN td 0.918 2.011 f cmos2_href_ibuf/opit_0/O
+ net (fanout=1) 0.000 2.011 cmos2_href_ibuf/ntD
+ IOL_35_5/RX_DATA_DD td 0.097 2.108 f cmos2_href_ibuf/opit_1/OUT
+ net (fanout=1) 0.521 2.629 nt_cmos2_href
+ CLMA_18_12/Y6AB td 0.101 2.730 f CLKROUTE_2/Z
+ net (fanout=1) 3.087 5.817 ntR3942
+ CLMA_18_80/Y6CD td 0.103 5.920 f CLKROUTE_1/Z
+ net (fanout=1) 3.317 9.237 ntR3941
+ CLMS_78_21/CD f u_ov5640/cmos2_href_d0/opit_0/D
- Data arrival time 8.448 Logic Levels: 3
- Logic: 1.247ns(16.743%), Route: 6.201ns(83.257%)
+ Data arrival time 9.237 Logic Levels: 4
+ Logic: 1.219ns(14.799%), Route: 7.018ns(85.201%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 11.900 11.900 r
@@ -8294,33 +9130,33 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 0.735 12.706 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 12.706 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.066 12.772 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 1.745 14.517 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 14.517 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 15.412 ntclkbufg_6
- CLMA_134_40/CLK r u_ov5640/cmos2_d_d0[6]/opit_0/CLK
- clock pessimism 0.000 15.412
- clock uncertainty -0.250 15.162
+ net (fanout=1) 1.744 14.516 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 14.516 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 0.934 15.450 ntclkbufg_7
+ CLMS_78_21/CLK r u_ov5640/cmos2_href_d0/opit_0/CLK
+ clock pessimism 0.000 15.450
+ clock uncertainty -0.250 15.200
- Setup time -0.068 15.094
+ Setup time 0.024 15.224
- Data required time 15.094
+ Data required time 15.224
----------------------------------------------------------------------------------------------------
- Data required time 15.094
- Data arrival time 8.448
+ Data required time 15.224
+ Data arrival time 9.237
----------------------------------------------------------------------------------------------------
- Slack (MET) 6.646
+ Slack (MET) 5.987
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK
-Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/D
+Startpoint : u_ov5640/cmos2_href_d0/opit_0/CLK
+Endpoint : u_ov5640/cmos2_href_d1/opit_0/D
Path Group : cmos2_pclk
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.861
- Launch Clock Delay : 3.512
+Clock Skew : 0.007 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.887
+ Launch Clock Delay : 3.550
Clock Pessimism Removal : -0.330
Location Delay Type Incr Path Logical Resource
@@ -8332,17 +9168,17 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 0.735 0.806 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 0.806 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.066 0.872 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 1.745 2.617 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 2.617 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 3.512 ntclkbufg_6
- CLMS_150_53/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK
+ net (fanout=1) 1.744 2.616 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 2.616 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 0.934 3.550 ntclkbufg_7
+ CLMS_78_21/CLK r u_ov5640/cmos2_href_d0/opit_0/CLK
- CLMS_150_53/Q3 tco 0.182 3.694 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/Q
- net (fanout=1) 0.280 3.974 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr1 [4]
- CLMA_154_53/M1 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/D
+ CLMS_78_21/Y2 tco 0.236 3.786 r u_ov5640/cmos2_href_d0/opit_0/Q
+ net (fanout=1) 0.210 3.996 u_ov5640/cmos2_href_d0
+ CLMS_74_17/M2 r u_ov5640/cmos2_href_d1/opit_0/D
- Data arrival time 3.974 Logic Levels: 0
- Logic: 0.182ns(39.394%), Route: 0.280ns(60.606%)
+ Data arrival time 3.996 Logic Levels: 0
+ Logic: 0.236ns(52.915%), Route: 0.210ns(47.085%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 0.000 0.000 r
@@ -8351,34 +9187,34 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 0.861 0.932 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 0.932 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.096 1.028 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 1.908 2.936 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 2.936 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 0.925 3.861 ntclkbufg_6
- CLMA_154_53/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK
- clock pessimism -0.330 3.531
- clock uncertainty 0.200 3.731
+ net (fanout=1) 1.907 2.935 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 2.935 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 0.952 3.887 ntclkbufg_7
+ CLMS_74_17/CLK r u_ov5640/cmos2_href_d1/opit_0/CLK
+ clock pessimism -0.330 3.557
+ clock uncertainty 0.200 3.757
- Hold time -0.011 3.720
+ Hold time -0.011 3.746
- Data required time 3.720
+ Data required time 3.746
----------------------------------------------------------------------------------------------------
- Data required time 3.720
- Data arrival time 3.974
+ Data required time 3.746
+ Data arrival time 3.996
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.254
+ Slack (MET) 0.250
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/CLK
-Endpoint : u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/D
+Startpoint : u_ov5640/cmos2_d_d0[4]/opit_0/CLK
+Endpoint : u_ov5640/cmos2_d_d1[4]/opit_0/D
Path Group : cmos2_pclk
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.861
- Launch Clock Delay : 3.512
- Clock Pessimism Removal : -0.330
+Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.860
+ Launch Clock Delay : 3.511
+ Clock Pessimism Removal : -0.348
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -8389,17 +9225,17 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 0.735 0.806 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 0.806 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.066 0.872 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 1.745 2.617 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 2.617 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 3.512 ntclkbufg_6
- CLMS_130_45/CLK r u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/CLK
+ net (fanout=1) 1.744 2.616 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 2.616 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 0.895 3.511 ntclkbufg_7
+ CLMA_138_20/CLK r u_ov5640/cmos2_d_d0[4]/opit_0/CLK
- CLMS_130_45/Y2 tco 0.236 3.748 r u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/Q
- net (fanout=1) 0.234 3.982 u_ov5640/cmos2_8_16bit/pdata_i0 [1]
- CLMA_134_52/M3 r u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/D
+ CLMA_138_20/Y0 tco 0.236 3.747 r u_ov5640/cmos2_d_d0[4]/opit_0/Q
+ net (fanout=1) 0.211 3.958 u_ov5640/cmos2_d_d0 [4]
+ CLMA_138_20/M2 r u_ov5640/cmos2_d_d1[4]/opit_0/D
- Data arrival time 3.982 Logic Levels: 0
- Logic: 0.236ns(50.213%), Route: 0.234ns(49.787%)
+ Data arrival time 3.958 Logic Levels: 0
+ Logic: 0.236ns(52.796%), Route: 0.211ns(47.204%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 0.000 0.000 r
@@ -8408,33 +9244,33 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 0.861 0.932 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 0.932 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.096 1.028 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 1.908 2.936 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 2.936 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 0.925 3.861 ntclkbufg_6
- CLMA_134_52/CLK r u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/CLK
- clock pessimism -0.330 3.531
- clock uncertainty 0.200 3.731
+ net (fanout=1) 1.907 2.935 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 2.935 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 0.925 3.860 ntclkbufg_7
+ CLMA_138_20/CLK r u_ov5640/cmos2_d_d1[4]/opit_0/CLK
+ clock pessimism -0.348 3.512
+ clock uncertainty 0.200 3.712
- Hold time -0.011 3.720
+ Hold time -0.011 3.701
- Data required time 3.720
+ Data required time 3.701
----------------------------------------------------------------------------------------------------
- Data required time 3.720
- Data arrival time 3.982
+ Data required time 3.701
+ Data arrival time 3.958
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.262
+ Slack (MET) 0.257
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/CLK
-Endpoint : u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/D
+Startpoint : u_ov5640/cmos2_d_d1[3]/opit_0/CLK
+Endpoint : u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/D
Path Group : cmos2_pclk
Path Type : min (fast corner)
Path Class : sequential timing path
Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.861
- Launch Clock Delay : 3.512
+ Capture Clock Delay : 3.860
+ Launch Clock Delay : 3.511
Clock Pessimism Removal : -0.330
Location Delay Type Incr Path Logical Resource
@@ -8446,17 +9282,17 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 0.735 0.806 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 0.806 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.066 0.872 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 1.745 2.617 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 2.617 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 0.895 3.512 ntclkbufg_6
- CLMS_130_53/CLK r u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/CLK
+ net (fanout=1) 1.744 2.616 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 2.616 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 0.895 3.511 ntclkbufg_7
+ CLMA_126_25/CLK r u_ov5640/cmos2_d_d1[3]/opit_0/CLK
- CLMS_130_53/Q3 tco 0.182 3.694 r u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/Q
- net (fanout=1) 0.289 3.983 u_ov5640/cmos2_8_16bit/pdata_i2 [0]
- CLMA_138_56/M2 r u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/D
+ CLMA_126_25/Q1 tco 0.184 3.695 r u_ov5640/cmos2_d_d1[3]/opit_0/Q
+ net (fanout=1) 0.285 3.980 u_ov5640/cmos2_d_d1 [3]
+ CLMA_130_32/M1 r u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/D
- Data arrival time 3.983 Logic Levels: 0
- Logic: 0.182ns(38.641%), Route: 0.289ns(61.359%)
+ Data arrival time 3.980 Logic Levels: 0
+ Logic: 0.184ns(39.232%), Route: 0.285ns(60.768%)
----------------------------------------------------------------------------------------------------
Clock cmos2_pclk (rising edge) 0.000 0.000 r
@@ -8465,21 +9301,21 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOBD_37_0/DIN td 0.861 0.932 r cmos2_pclk_ibuf/opit_0/O
net (fanout=1) 0.000 0.932 cmos2_pclk_ibuf/ntD
IOL_39_6/RX_DATA_DD td 0.096 1.028 r cmos2_pclk_ibuf/opit_1/OUT
- net (fanout=1) 1.908 2.936 nt_cmos2_pclk
- USCM_84_118/CLK_USCM td 0.000 2.936 r clkbufg_6/gopclkbufg/CLKOUT
- net (fanout=118) 0.925 3.861 ntclkbufg_6
- CLMA_138_56/CLK r u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/CLK
- clock pessimism -0.330 3.531
- clock uncertainty 0.200 3.731
+ net (fanout=1) 1.907 2.935 nt_cmos2_pclk
+ USCM_84_119/CLK_USCM td 0.000 2.935 r clkbufg_7/gopclkbufg/CLKOUT
+ net (fanout=118) 0.925 3.860 ntclkbufg_7
+ CLMA_130_32/CLK r u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/CLK
+ clock pessimism -0.330 3.530
+ clock uncertainty 0.200 3.730
- Hold time -0.011 3.720
+ Hold time -0.011 3.719
- Data required time 3.720
+ Data required time 3.719
----------------------------------------------------------------------------------------------------
- Data required time 3.720
- Data arrival time 3.983
+ Data required time 3.719
+ Data arrival time 3.980
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.263
+ Slack (MET) 0.261
====================================================================================================
====================================================================================================
@@ -8504,28 +9340,30 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.455 3.095 _N37
- USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.925 4.020 ntclkbufg_4
- CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
-
- CLMA_146_68/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
- net (fanout=4) 1.078 5.319 wr1_data_in_valid
- td 0.222 5.541 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 5.541 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001
- CLMA_70_96/Y3 td 0.387 5.928 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Y1
- net (fanout=3) 0.249 6.177 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [3]
- CLMA_66_88/Y2 td 0.381 6.558 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm/Z
- net (fanout=1) 0.283 6.841 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wwptr [3]
- td 0.365 7.206 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_0/gateop_A2/Cout
- net (fanout=1) 0.000 7.206 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [2]
- CLMA_66_100/COUT td 0.044 7.250 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 7.250 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6]
- CLMA_66_104/Y1 td 0.383 7.633 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1
- net (fanout=1) 0.072 7.705 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158
- CLMA_66_104/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4
-
- Data arrival time 7.705 Logic Levels: 4
- Logic: 2.003ns(54.355%), Route: 1.682ns(45.645%)
+ USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.925 4.020 ntclkbufg_5
+ CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
+
+ CLMA_110_85/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
+ net (fanout=4) 0.537 4.778 wr1_data_in_valid
+ td 0.222 5.000 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 5.000 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959
+ CLMA_90_101/COUT td 0.044 5.044 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 5.044 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961
+ td 0.044 5.088 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 5.088 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963
+ CLMA_90_105/Y3 td 0.365 5.453 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Y1
+ net (fanout=3) 0.355 5.808 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [7]
+ CLMA_94_112/Y3 td 0.151 5.959 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm/Z
+ net (fanout=1) 0.366 6.325 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wwptr [7]
+ CLMA_90_100/COUT td 0.391 6.716 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout
+ net (fanout=1) 0.000 6.716 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6]
+ CLMA_90_104/Y1 td 0.383 7.099 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1
+ net (fanout=1) 0.074 7.173 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158
+ CLMA_90_104/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4
+
+ Data arrival time 7.173 Logic Levels: 5
+ Logic: 1.821ns(57.755%), Route: 1.332ns(42.245%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 6.666 6.666 r
@@ -8535,9 +9373,9 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 8.029 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.038 8.067 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.428 9.495 _N37
- USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.895 10.390 ntclkbufg_4
- CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.895 10.390 ntclkbufg_5
+ CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
clock pessimism 0.277 10.667
clock uncertainty -0.250 10.417
@@ -8546,15 +9384,15 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
Data required time 10.323
----------------------------------------------------------------------------------------------------
Data required time 10.323
- Data arrival time 7.705
+ Data arrival time 7.173
----------------------------------------------------------------------------------------------------
- Slack (MET) 2.618
+ Slack (MET) 3.150
====================================================================================================
====================================================================================================
Startpoint : u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0
+Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2
Path Group : hdmi_in_clk
Path Type : max (fast corner)
Path Class : sequential timing path
@@ -8573,28 +9411,24 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.455 3.095 _N37
- USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.925 4.020 ntclkbufg_4
- CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
-
- CLMA_146_68/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
- net (fanout=4) 1.078 5.319 wr1_data_in_valid
- td 0.222 5.541 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 5.541 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001
- CLMA_70_96/COUT td 0.044 5.585 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 5.585 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003
- td 0.044 5.629 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 5.629 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005
- CLMA_70_100/COUT td 0.044 5.673 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 5.673 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007
- td 0.044 5.717 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 5.717 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009
- CLMA_70_104/Y3 td 0.387 6.104 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1
- net (fanout=3) 0.247 6.351 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11]
- CLMA_66_104/C0 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0
-
- Data arrival time 6.351 Logic Levels: 3
- Logic: 1.006ns(43.157%), Route: 1.325ns(56.843%)
+ USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.925 4.020 ntclkbufg_5
+ CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
+
+ CLMA_110_85/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
+ net (fanout=4) 0.537 4.778 wr1_data_in_valid
+ td 0.222 5.000 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 5.000 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959
+ CLMA_90_101/COUT td 0.044 5.044 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 5.044 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961
+ td 0.044 5.088 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 5.088 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963
+ CLMA_90_105/Y2 td 0.209 5.297 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Y0
+ net (fanout=3) 0.452 5.749 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [6]
+ CLMA_90_104/D2 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2
+
+ Data arrival time 5.749 Logic Levels: 2
+ Logic: 0.740ns(42.799%), Route: 0.989ns(57.201%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 6.666 6.666 r
@@ -8604,26 +9438,26 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 8.029 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.038 8.067 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.428 9.495 _N37
- USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.895 10.390 ntclkbufg_4
- CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.895 10.390 ntclkbufg_5
+ CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK
clock pessimism 0.277 10.667
clock uncertainty -0.250 10.417
- Setup time -0.150 10.267
+ Setup time -0.283 10.134
- Data required time 10.267
+ Data required time 10.134
----------------------------------------------------------------------------------------------------
- Data required time 10.267
- Data arrival time 6.351
+ Data required time 10.134
+ Data arrival time 5.749
----------------------------------------------------------------------------------------------------
- Slack (MET) 3.916
+ Slack (MET) 4.385
====================================================================================================
====================================================================================================
Startpoint : u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4
+Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1
Path Group : hdmi_in_clk
Path Type : max (fast corner)
Path Class : sequential timing path
@@ -8642,28 +9476,28 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.455 3.095 _N37
- USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.925 4.020 ntclkbufg_4
- CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
-
- CLMA_146_68/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
- net (fanout=4) 1.078 5.319 wr1_data_in_valid
- td 0.222 5.541 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 5.541 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001
- CLMA_70_96/COUT td 0.044 5.585 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 5.585 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003
- td 0.044 5.629 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 5.629 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005
- CLMA_70_100/COUT td 0.044 5.673 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 5.673 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007
- td 0.044 5.717 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 5.717 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009
- CLMA_70_104/Y3 td 0.387 6.104 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1
- net (fanout=3) 0.247 6.351 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11]
- CLMS_66_105/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4
-
- Data arrival time 6.351 Logic Levels: 3
- Logic: 1.006ns(43.157%), Route: 1.325ns(56.843%)
+ USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.925 4.020 ntclkbufg_5
+ CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
+
+ CLMA_110_85/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q
+ net (fanout=4) 0.537 4.778 wr1_data_in_valid
+ td 0.222 5.000 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 5.000 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959
+ CLMA_90_101/COUT td 0.044 5.044 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 5.044 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961
+ td 0.044 5.088 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 5.088 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963
+ CLMA_90_105/COUT td 0.044 5.132 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 5.132 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15965
+ td 0.044 5.176 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 5.176 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15967
+ CLMA_90_109/Y3 td 0.365 5.541 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1
+ net (fanout=3) 0.259 5.800 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11]
+ CLMA_90_104/C1 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1
+
+ Data arrival time 5.800 Logic Levels: 3
+ Logic: 0.984ns(55.281%), Route: 0.796ns(44.719%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 6.666 6.666 r
@@ -8673,26 +9507,26 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.000 8.029 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.038 8.067 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.428 9.495 _N37
- USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.895 10.390 ntclkbufg_4
- CLMS_66_105/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.895 10.390 ntclkbufg_5
+ CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
clock pessimism 0.277 10.667
clock uncertainty -0.250 10.417
- Setup time -0.094 10.323
+ Setup time -0.190 10.227
- Data required time 10.323
+ Data required time 10.227
----------------------------------------------------------------------------------------------------
- Data required time 10.323
- Data arrival time 6.351
+ Data required time 10.227
+ Data arrival time 5.800
----------------------------------------------------------------------------------------------------
- Slack (MET) 3.972
+ Slack (MET) 4.427
====================================================================================================
====================================================================================================
-Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK
-Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0
+Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK
+Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0
Path Group : hdmi_in_clk
Path Type : min (fast corner)
Path Class : sequential timing path
@@ -8711,16 +9545,16 @@ Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.363 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.038 1.401 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.428 2.829 _N37
- USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.895 3.724 ntclkbufg_4
- CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.895 3.724 ntclkbufg_5
+ CLMA_122_92/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK
- CLMA_110_85/Q2 tco 0.180 3.904 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/Q
- net (fanout=5) 0.062 3.966 u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [2]
- CLMA_110_85/D0 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0
+ CLMA_122_92/Q2 tco 0.180 3.904 f u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/Q
+ net (fanout=3) 0.059 3.963 u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt [2]
+ CLMA_122_92/D0 f u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0
- Data arrival time 3.966 Logic Levels: 0
- Logic: 0.180ns(74.380%), Route: 0.062ns(25.620%)
+ Data arrival time 3.963 Logic Levels: 0
+ Logic: 0.180ns(75.314%), Route: 0.059ns(24.686%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 0.000 0.000 r
@@ -8730,9 +9564,9 @@ Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.455 3.095 _N37
- USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.925 4.020 ntclkbufg_4
- CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK
+ USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.925 4.020 ntclkbufg_5
+ CLMA_122_92/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK
clock pessimism -0.295 3.725
clock uncertainty 0.200 3.925
@@ -8741,15 +9575,15 @@ Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 3.860
----------------------------------------------------------------------------------------------------
Data required time 3.860
- Data arrival time 3.966
+ Data arrival time 3.963
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.106
+ Slack (MET) 0.103
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK
-Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/D
+Startpoint : u_hdmi_in_top/r_in3[3]/opit_0/CLK
+Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[3]
Path Group : hdmi_in_clk
Path Type : min (fast corner)
Path Class : sequential timing path
@@ -8768,16 +9602,16 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.363 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.038 1.401 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.428 2.829 _N37
- USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.895 3.724 ntclkbufg_4
- CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK
+ USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.895 3.724 ntclkbufg_5
+ CLMS_94_89/CLK r u_hdmi_in_top/r_in3[3]/opit_0/CLK
- CLMA_66_104/Q0 tco 0.182 3.906 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/Q
- net (fanout=1) 0.137 4.043 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [3]
- CLMS_62_101/M2 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/D
+ CLMS_94_89/Q3 tco 0.178 3.902 f u_hdmi_in_top/r_in3[3]/opit_0/Q
+ net (fanout=1) 0.265 4.167 wr1_data_in[11]
+ DRM_82_88/DA0[3] f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[3]
- Data arrival time 4.043 Logic Levels: 0
- Logic: 0.182ns(57.053%), Route: 0.137ns(42.947%)
+ Data arrival time 4.167 Logic Levels: 0
+ Logic: 0.178ns(40.181%), Route: 0.265ns(59.819%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 0.000 0.000 r
@@ -8787,26 +9621,26 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.455 3.095 _N37
- USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.925 4.020 ntclkbufg_4
- CLMS_62_101/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK
+ USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.925 4.020 ntclkbufg_5
+ DRM_82_88/CLKA[0] r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0]
clock pessimism -0.277 3.743
clock uncertainty 0.200 3.943
- Hold time -0.011 3.932
+ Hold time 0.119 4.062
- Data required time 3.932
+ Data required time 4.062
----------------------------------------------------------------------------------------------------
- Data required time 3.932
- Data arrival time 4.043
+ Data required time 4.062
+ Data arrival time 4.167
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.111
+ Slack (MET) 0.105
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK
-Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/D
+Startpoint : u_hdmi_in_top/r_in3[5]/opit_0/CLK
+Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[5]
Path Group : hdmi_in_clk
Path Type : min (fast corner)
Path Class : sequential timing path
@@ -8825,16 +9659,16 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.363 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.038 1.401 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.428 2.829 _N37
- USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.895 3.724 ntclkbufg_4
- CLMA_62_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK
+ USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.895 3.724 ntclkbufg_5
+ CLMA_90_92/CLK r u_hdmi_in_top/r_in3[5]/opit_0/CLK
- CLMA_62_104/Q0 tco 0.182 3.906 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/Q
- net (fanout=1) 0.137 4.043 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [7]
- CLMA_66_100/M0 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/D
+ CLMA_90_92/Q3 tco 0.178 3.902 f u_hdmi_in_top/r_in3[5]/opit_0/Q
+ net (fanout=1) 0.266 4.168 wr1_data_in[13]
+ DRM_82_88/DA0[5] f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[5]
- Data arrival time 4.043 Logic Levels: 0
- Logic: 0.182ns(57.053%), Route: 0.137ns(42.947%)
+ Data arrival time 4.168 Logic Levels: 0
+ Logic: 0.178ns(40.090%), Route: 0.266ns(59.910%)
----------------------------------------------------------------------------------------------------
Clock hdmi_in_clk (rising edge) 0.000 0.000 r
@@ -8844,33 +9678,33 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD
IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK
net (fanout=1) 1.455 3.095 _N37
- USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT
- net (fanout=167) 0.925 4.020 ntclkbufg_4
- CLMA_66_100/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK
+ USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT
+ net (fanout=167) 0.925 4.020 ntclkbufg_5
+ DRM_82_88/CLKA[0] r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0]
clock pessimism -0.277 3.743
clock uncertainty 0.200 3.943
- Hold time -0.011 3.932
+ Hold time 0.119 4.062
- Data required time 3.932
+ Data required time 4.062
----------------------------------------------------------------------------------------------------
- Data required time 3.932
- Data arrival time 4.043
+ Data required time 4.062
+ Data arrival time 4.168
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.111
+ Slack (MET) 0.106
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE
+Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE
Path Group : eth_rxc
Path Type : max (fast corner)
Path Class : sequential timing path
Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.650
- Launch Clock Delay : 6.734
- Clock Pessimism Removal : 1.065
+ Capture Clock Delay : 5.760
+ Launch Clock Delay : 6.846
+ Clock Pessimism Removal : 1.067
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -8885,35 +9719,29 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.925 6.734 gmii_clk
- CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-
- CLMA_202_140/Q2 tco 0.224 6.958 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q
- net (fanout=2) 0.305 7.263 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2]
- td 0.365 7.628 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 7.628 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2]
- CLMA_214_140/COUT td 0.044 7.672 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout
- net (fanout=1) 0.000 7.672 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4]
- td 0.044 7.716 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout
- net (fanout=1) 0.000 7.716 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6]
- CLMA_214_144/COUT td 0.044 7.760 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout
- net (fanout=1) 0.000 7.760 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8]
- td 0.044 7.804 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout
- net (fanout=1) 0.000 7.804 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10]
- CLMA_214_148/COUT td 0.044 7.848 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout
- net (fanout=1) 0.000 7.848 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12]
- CLMA_214_152/Y0 td 0.206 8.054 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0
- net (fanout=1) 0.468 8.522 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13]
- CLMA_210_141/Y3 td 0.431 8.953 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1
- net (fanout=18) 0.529 9.482 _N79
- CLMS_186_153/Y2 td 0.381 9.863 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z
- net (fanout=1) 0.304 10.167 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323
- CLMA_194_160/Y1 td 0.244 10.411 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z
- net (fanout=16) 0.553 10.964 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839
- CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE
-
- Data arrival time 10.964 Logic Levels: 7
- Logic: 2.071ns(48.960%), Route: 2.159ns(51.040%)
+ net (fanout=1862) 1.037 6.846 gmii_clk
+ CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+
+ CLMA_194_261/Q0 tco 0.221 7.067 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q
+ net (fanout=2) 0.560 7.627 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0]
+ CLMA_182_241/Y1 td 0.224 7.851 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z
+ net (fanout=1) 0.458 8.309 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159
+ CLMA_190_252/Y3 td 0.151 8.460 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z
+ net (fanout=1) 0.367 8.827 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179
+ CLMA_190_240/Y2 td 0.150 8.977 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z
+ net (fanout=2) 0.645 9.622 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446
+ CLMA_210_265/Y3 td 0.162 9.784 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z
+ net (fanout=6) 0.302 10.086 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187
+ CLMA_198_264/Y3 td 0.151 10.237 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z
+ net (fanout=187) 0.449 10.686 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319
+ CLMA_202_272/CECO td 0.132 10.818 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT
+ net (fanout=1) 0.000 10.818 ntR2081
+ CLMA_202_276/CECO td 0.132 10.950 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT
+ net (fanout=6) 0.000 10.950 ntR2080
+ CLMA_202_280/CECI f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE
+
+ Data arrival time 10.950 Logic Levels: 7
+ Logic: 1.323ns(32.237%), Route: 2.781ns(67.763%)
----------------------------------------------------------------------------------------------------
Clock eth_rxc (rising edge) 8.000 8.000 r
@@ -8926,32 +9754,32 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 2.069 11.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.493 12.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 12.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.895 13.650 gmii_clk
- CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CLK
- clock pessimism 1.065 14.715
- clock uncertainty -0.250 14.465
+ net (fanout=1862) 1.005 13.760 gmii_clk
+ CLMA_202_280/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CLK
+ clock pessimism 1.067 14.827
+ clock uncertainty -0.250 14.577
- Setup time -0.476 13.989
+ Setup time -0.576 14.001
- Data required time 13.989
+ Data required time 14.001
----------------------------------------------------------------------------------------------------
- Data required time 13.989
- Data arrival time 10.964
+ Data required time 14.001
+ Data arrival time 10.950
----------------------------------------------------------------------------------------------------
- Slack (MET) 3.025
+ Slack (MET) 3.051
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE
+Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE
Path Group : eth_rxc
Path Type : max (fast corner)
Path Class : sequential timing path
Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.650
- Launch Clock Delay : 6.734
- Clock Pessimism Removal : 1.065
+ Capture Clock Delay : 5.760
+ Launch Clock Delay : 6.846
+ Clock Pessimism Removal : 1.067
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -8966,35 +9794,29 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.925 6.734 gmii_clk
- CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-
- CLMA_202_140/Q2 tco 0.224 6.958 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q
- net (fanout=2) 0.305 7.263 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2]
- td 0.365 7.628 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 7.628 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2]
- CLMA_214_140/COUT td 0.044 7.672 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout
- net (fanout=1) 0.000 7.672 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4]
- td 0.044 7.716 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout
- net (fanout=1) 0.000 7.716 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6]
- CLMA_214_144/COUT td 0.044 7.760 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout
- net (fanout=1) 0.000 7.760 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8]
- td 0.044 7.804 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout
- net (fanout=1) 0.000 7.804 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10]
- CLMA_214_148/COUT td 0.044 7.848 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout
- net (fanout=1) 0.000 7.848 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12]
- CLMA_214_152/Y0 td 0.206 8.054 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0
- net (fanout=1) 0.468 8.522 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13]
- CLMA_210_141/Y3 td 0.431 8.953 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1
- net (fanout=18) 0.529 9.482 _N79
- CLMS_186_153/Y2 td 0.381 9.863 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z
- net (fanout=1) 0.304 10.167 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323
- CLMA_194_160/Y1 td 0.244 10.411 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z
- net (fanout=16) 0.553 10.964 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839
- CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE
-
- Data arrival time 10.964 Logic Levels: 7
- Logic: 2.071ns(48.960%), Route: 2.159ns(51.040%)
+ net (fanout=1862) 1.037 6.846 gmii_clk
+ CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+
+ CLMA_194_261/Q0 tco 0.221 7.067 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q
+ net (fanout=2) 0.560 7.627 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0]
+ CLMA_182_241/Y1 td 0.224 7.851 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z
+ net (fanout=1) 0.458 8.309 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159
+ CLMA_190_252/Y3 td 0.151 8.460 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z
+ net (fanout=1) 0.367 8.827 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179
+ CLMA_190_240/Y2 td 0.150 8.977 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z
+ net (fanout=2) 0.645 9.622 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446
+ CLMA_210_265/Y3 td 0.162 9.784 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z
+ net (fanout=6) 0.302 10.086 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187
+ CLMA_198_264/Y3 td 0.151 10.237 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z
+ net (fanout=187) 0.449 10.686 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319
+ CLMA_202_272/CECO td 0.132 10.818 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT
+ net (fanout=1) 0.000 10.818 ntR2081
+ CLMA_202_276/CECO td 0.132 10.950 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT
+ net (fanout=6) 0.000 10.950 ntR2080
+ CLMA_202_280/CECI f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE
+
+ Data arrival time 10.950 Logic Levels: 7
+ Logic: 1.323ns(32.237%), Route: 2.781ns(67.763%)
----------------------------------------------------------------------------------------------------
Clock eth_rxc (rising edge) 8.000 8.000 r
@@ -9007,32 +9829,32 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 2.069 11.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.493 12.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 12.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.895 13.650 gmii_clk
- CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CLK
- clock pessimism 1.065 14.715
- clock uncertainty -0.250 14.465
+ net (fanout=1862) 1.005 13.760 gmii_clk
+ CLMA_202_280/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CLK
+ clock pessimism 1.067 14.827
+ clock uncertainty -0.250 14.577
- Setup time -0.476 13.989
+ Setup time -0.576 14.001
- Data required time 13.989
+ Data required time 14.001
----------------------------------------------------------------------------------------------------
- Data required time 13.989
- Data arrival time 10.964
+ Data required time 14.001
+ Data arrival time 10.950
----------------------------------------------------------------------------------------------------
- Slack (MET) 3.025
+ Slack (MET) 3.051
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE
+Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CE
Path Group : eth_rxc
Path Type : max (fast corner)
Path Class : sequential timing path
Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.650
- Launch Clock Delay : 6.734
- Clock Pessimism Removal : 1.065
+ Capture Clock Delay : 5.760
+ Launch Clock Delay : 6.846
+ Clock Pessimism Removal : 1.067
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -9047,35 +9869,29 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.925 6.734 gmii_clk
- CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
-
- CLMA_202_140/Q2 tco 0.224 6.958 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q
- net (fanout=2) 0.305 7.263 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2]
- td 0.365 7.628 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 7.628 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2]
- CLMA_214_140/COUT td 0.044 7.672 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout
- net (fanout=1) 0.000 7.672 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4]
- td 0.044 7.716 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout
- net (fanout=1) 0.000 7.716 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6]
- CLMA_214_144/COUT td 0.044 7.760 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout
- net (fanout=1) 0.000 7.760 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8]
- td 0.044 7.804 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout
- net (fanout=1) 0.000 7.804 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10]
- CLMA_214_148/COUT td 0.044 7.848 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout
- net (fanout=1) 0.000 7.848 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12]
- CLMA_214_152/Y0 td 0.206 8.054 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0
- net (fanout=1) 0.468 8.522 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13]
- CLMA_210_141/Y3 td 0.431 8.953 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1
- net (fanout=18) 0.529 9.482 _N79
- CLMS_186_153/Y2 td 0.381 9.863 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z
- net (fanout=1) 0.304 10.167 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323
- CLMA_194_160/Y1 td 0.244 10.411 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z
- net (fanout=16) 0.553 10.964 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839
- CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE
-
- Data arrival time 10.964 Logic Levels: 7
- Logic: 2.071ns(48.960%), Route: 2.159ns(51.040%)
+ net (fanout=1862) 1.037 6.846 gmii_clk
+ CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+
+ CLMA_194_261/Q0 tco 0.221 7.067 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q
+ net (fanout=2) 0.560 7.627 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0]
+ CLMA_182_241/Y1 td 0.224 7.851 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z
+ net (fanout=1) 0.458 8.309 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159
+ CLMA_190_252/Y3 td 0.151 8.460 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z
+ net (fanout=1) 0.367 8.827 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179
+ CLMA_190_240/Y2 td 0.150 8.977 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z
+ net (fanout=2) 0.645 9.622 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446
+ CLMA_210_265/Y3 td 0.162 9.784 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z
+ net (fanout=6) 0.302 10.086 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187
+ CLMA_198_264/Y3 td 0.151 10.237 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z
+ net (fanout=187) 0.449 10.686 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319
+ CLMA_202_272/CECO td 0.132 10.818 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT
+ net (fanout=1) 0.000 10.818 ntR2081
+ CLMA_202_276/CECO td 0.132 10.950 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT
+ net (fanout=6) 0.000 10.950 ntR2080
+ CLMA_202_280/CECI f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CE
+
+ Data arrival time 10.950 Logic Levels: 7
+ Logic: 1.323ns(32.237%), Route: 2.781ns(67.763%)
----------------------------------------------------------------------------------------------------
Clock eth_rxc (rising edge) 8.000 8.000 r
@@ -9088,32 +9904,32 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOCKDLY_237_367/CLK_OUT td 2.069 11.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.493 12.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 12.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.895 13.650 gmii_clk
- CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CLK
- clock pessimism 1.065 14.715
- clock uncertainty -0.250 14.465
+ net (fanout=1862) 1.005 13.760 gmii_clk
+ CLMA_202_280/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CLK
+ clock pessimism 1.067 14.827
+ clock uncertainty -0.250 14.577
- Setup time -0.476 13.989
+ Setup time -0.576 14.001
- Data required time 13.989
+ Data required time 14.001
----------------------------------------------------------------------------------------------------
- Data required time 13.989
- Data arrival time 10.964
+ Data required time 14.001
+ Data arrival time 10.950
----------------------------------------------------------------------------------------------------
- Slack (MET) 3.025
+ Slack (MET) 3.051
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/CLK
-Endpoint : udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[4]
+Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D
Path Group : eth_rxc
Path Type : min (fast corner)
Path Class : sequential timing path
Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.734
- Launch Clock Delay : 5.650
- Clock Pessimism Removal : -1.065
+ Capture Clock Delay : 6.846
+ Launch Clock Delay : 5.760
+ Clock Pessimism Removal : -1.067
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -9128,15 +9944,15 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOCKDLY_237_367/CLK_OUT td 2.069 3.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.493 4.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 4.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.895 5.650 gmii_clk
- CLMA_210_200/CLK r udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/CLK
+ net (fanout=1862) 1.005 5.760 gmii_clk
+ CLMA_194_288/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK
- CLMA_210_200/Q2 tco 0.183 5.833 r udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/Q
- net (fanout=1) 0.390 6.223 udp_osd_inst/eth_udp_inst/rec_data [4]
- DRM_234_192/DA0[4] r udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[4]
+ CLMA_194_288/Q0 tco 0.182 5.942 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/Q
+ net (fanout=3) 0.146 6.088 udp_osd_inst/eth_udp_inst/des_ip [30]
+ CLMA_198_288/AD r udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D
- Data arrival time 6.223 Logic Levels: 0
- Logic: 0.183ns(31.937%), Route: 0.390ns(68.063%)
+ Data arrival time 6.088 Logic Levels: 0
+ Logic: 0.182ns(55.488%), Route: 0.146ns(44.512%)
----------------------------------------------------------------------------------------------------
Clock eth_rxc (rising edge) 0.000 0.000 r
@@ -9149,25 +9965,25 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.925 6.734 gmii_clk
- DRM_234_192/CLKA[0] r udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- clock pessimism -1.065 5.669
- clock uncertainty 0.200 5.869
+ net (fanout=1862) 1.037 6.846 gmii_clk
+ CLMA_198_288/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/CLK
+ clock pessimism -1.067 5.779
+ clock uncertainty 0.200 5.979
- Hold time 0.102 5.971
+ Hold time 0.034 6.013
- Data required time 5.971
+ Data required time 6.013
----------------------------------------------------------------------------------------------------
- Data required time 5.971
- Data arrival time 6.223
+ Data required time 6.013
+ Data arrival time 6.088
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.252
+ Slack (MET) 0.075
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/CLK
-Endpoint : udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[3]
+Startpoint : udp_wr_mem_inst/mem[190]/opit_0/CLK
+Endpoint : param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm/L0
Path Group : eth_rxc
Path Type : min (fast corner)
Path Class : sequential timing path
@@ -9189,15 +10005,15 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOCKDLY_237_367/CLK_OUT td 2.069 3.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.493 4.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 4.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.895 5.650 gmii_clk
- CLMA_210_201/CLK r udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/CLK
+ net (fanout=1862) 0.895 5.650 gmii_clk
+ CLMS_222_217/CLK r udp_wr_mem_inst/mem[190]/opit_0/CLK
- CLMA_210_201/Q0 tco 0.182 5.832 r udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/Q
- net (fanout=1) 0.393 6.225 udp_osd_inst/eth_udp_inst/rec_data [3]
- DRM_234_192/DA0[3] r udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[3]
+ CLMS_222_217/Q1 tco 0.184 5.834 r udp_wr_mem_inst/mem[190]/opit_0/Q
+ net (fanout=1) 0.212 6.046 mem[190]
+ CLMA_230_212/C0 r param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm/L0
- Data arrival time 6.225 Logic Levels: 0
- Logic: 0.182ns(31.652%), Route: 0.393ns(68.348%)
+ Data arrival time 6.046 Logic Levels: 0
+ Logic: 0.184ns(46.465%), Route: 0.212ns(53.535%)
----------------------------------------------------------------------------------------------------
Clock eth_rxc (rising edge) 0.000 0.000 r
@@ -9210,32 +10026,32 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.925 6.734 gmii_clk
- DRM_234_192/CLKA[0] r udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ net (fanout=1862) 0.925 6.734 gmii_clk
+ CLMA_230_212/CLK r param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm/CLK
clock pessimism -1.065 5.669
clock uncertainty 0.200 5.869
- Hold time 0.102 5.971
+ Hold time -0.078 5.791
- Data required time 5.971
+ Data required time 5.791
----------------------------------------------------------------------------------------------------
- Data required time 5.971
- Data arrival time 6.225
+ Data required time 5.791
+ Data arrival time 6.046
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.254
+ Slack (MET) 0.255
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/CLK
-Endpoint : udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/I01
+Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/L1
Path Group : eth_rxc
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.734
- Launch Clock Delay : 5.650
- Clock Pessimism Removal : -1.065
+Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 6.846
+ Launch Clock Delay : 5.760
+ Clock Pessimism Removal : -1.071
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -9250,1629 +10066,2069 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOCKDLY_237_367/CLK_OUT td 2.069 3.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.493 4.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 4.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.895 5.650 gmii_clk
- CLMA_182_209/CLK r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/CLK
+ net (fanout=1862) 1.005 5.760 gmii_clk
+ CLMA_186_264/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/CLK
+
+ CLMA_186_264/Q2 tco 0.183 5.943 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/Q
+ net (fanout=2) 0.194 6.137 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t [17]
+ CLMS_186_265/A1 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/L1
+
+ Data arrival time 6.137 Logic Levels: 0
+ Logic: 0.183ns(48.541%), Route: 0.194ns(51.459%)
+----------------------------------------------------------------------------------------------------
+
+ Clock eth_rxc (rising edge) 0.000 0.000 r
+ F14 0.000 0.000 r eth_rxc (port)
+ net (fanout=1) 0.057 0.057 eth_rxc
+ IOBD_240_376/DIN td 0.861 0.918 r eth_rxc_ibuf/opit_0/O
+ net (fanout=1) 0.000 0.918 eth_rxc_ibuf/ntD
+ IOL_243_374/INCK td 0.058 0.976 r eth_rxc_ibuf/opit_1/INCK
+ net (fanout=1) 0.370 1.346 _N66
+ IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
+ net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
+ USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
+ net (fanout=1862) 1.037 6.846 gmii_clk
+ CLMS_186_265/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/CLK
+ clock pessimism -1.071 5.775
+ clock uncertainty 0.200 5.975
+
+ Hold time -0.093 5.882
+
+ Data required time 5.882
+----------------------------------------------------------------------------------------------------
+ Data required time 5.882
+ Data arrival time 6.137
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 0.255
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
+Path Group : clk_50m
+Path Type : max (fast corner)
+Path Class : sequential timing path
+Clock Skew : -0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.448
+ Launch Clock Delay : 3.764
+ Clock Pessimism Removal : 0.281
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.953 3.764 ntclkbufg_1
+ DRM_54_24/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
+
+ DRM_54_24/QB0[0] tco 1.780 5.544 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0]
+ net (fanout=6) 0.982 6.526 u_rotate_image/dout [0]
+ CLMS_74_117/Y1 td 0.359 6.885 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z
+ net (fanout=3) 1.071 7.956 u_rotate_image/addr_fifo_rd_en
+ td 0.222 8.178 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 8.178 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576
+ CLMS_50_33/COUT td 0.044 8.222 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 8.222 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578
+ CLMS_50_37/Y1 td 0.383 8.605 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1
+ net (fanout=1) 0.325 8.930 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5]
+ CLMA_58_29/Y1 td 0.360 9.290 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z
+ net (fanout=3) 0.392 9.682 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5]
+ CLMA_58_36/COUT td 0.394 10.076 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout
+ net (fanout=1) 0.000 10.076 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6]
+ CLMA_58_40/Y1 td 0.383 10.459 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1
+ net (fanout=1) 0.072 10.531 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21
+ CLMA_58_40/C4 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
+
+ Data arrival time 10.531 Logic Levels: 6
+ Logic: 3.925ns(58.002%), Route: 2.842ns(41.998%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 20.000 20.000 r
+ P20 0.000 20.000 r clk (port)
+ net (fanout=1) 0.074 20.074 clk
+ IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 21.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 21.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 22.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.907 23.448 ntclkbufg_1
+ CLMA_58_40/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK
+ clock pessimism 0.281 23.729
+ clock uncertainty -0.150 23.579
+
+ Setup time -0.094 23.485
+
+ Data required time 23.485
+----------------------------------------------------------------------------------------------------
+ Data required time 23.485
+ Data arrival time 10.531
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 12.954
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
+Path Group : clk_50m
+Path Type : max (fast corner)
+Path Class : sequential timing path
+Clock Skew : -0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.444
+ Launch Clock Delay : 3.764
+ Clock Pessimism Removal : 0.281
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.953 3.764 ntclkbufg_1
+ DRM_54_24/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
+
+ DRM_54_24/QB0[0] tco 1.780 5.544 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0]
+ net (fanout=6) 0.982 6.526 u_rotate_image/dout [0]
+ CLMS_74_117/Y1 td 0.359 6.885 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z
+ net (fanout=3) 1.071 7.956 u_rotate_image/addr_fifo_rd_en
+ td 0.222 8.178 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 8.178 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576
+ CLMS_50_33/COUT td 0.044 8.222 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 8.222 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578
+ CLMS_50_37/Y1 td 0.383 8.605 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1
+ net (fanout=1) 0.325 8.930 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5]
+ CLMA_58_29/Y1 td 0.360 9.290 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z
+ net (fanout=3) 0.257 9.547 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5]
+ CLMA_62_32/COUT td 0.394 9.941 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout
+ net (fanout=1) 0.000 9.941 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6]
+ CLMA_62_36/CIN r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
+
+ Data arrival time 9.941 Logic Levels: 5
+ Logic: 3.542ns(57.342%), Route: 2.635ns(42.658%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 20.000 20.000 r
+ P20 0.000 20.000 r clk (port)
+ net (fanout=1) 0.074 20.074 clk
+ IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 21.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 21.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 22.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.903 23.444 ntclkbufg_1
+ CLMA_62_36/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK
+ clock pessimism 0.281 23.725
+ clock uncertainty -0.150 23.575
+
+ Setup time -0.276 23.299
+
+ Data required time 23.299
+----------------------------------------------------------------------------------------------------
+ Data required time 23.299
+ Data arrival time 9.941
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 13.358
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/Cin
+Path Group : clk_50m
+Path Type : max (fast corner)
+Path Class : sequential timing path
+Clock Skew : -0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.448
+ Launch Clock Delay : 3.764
+ Clock Pessimism Removal : 0.281
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.953 3.764 ntclkbufg_1
+ DRM_54_24/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
+
+ DRM_54_24/QB0[0] tco 1.780 5.544 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0]
+ net (fanout=6) 0.982 6.526 u_rotate_image/dout [0]
+ CLMS_74_117/Y1 td 0.359 6.885 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z
+ net (fanout=3) 1.071 7.956 u_rotate_image/addr_fifo_rd_en
+ td 0.222 8.178 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 8.178 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576
+ CLMS_50_33/COUT td 0.044 8.222 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 8.222 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578
+ CLMS_50_37/Y1 td 0.383 8.605 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1
+ net (fanout=1) 0.325 8.930 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5]
+ CLMA_58_29/Y1 td 0.360 9.290 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z
+ net (fanout=3) 0.364 9.654 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5]
+ td 0.250 9.904 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/Cout
+ net (fanout=1) 0.000 9.904 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N138_5.co [6]
+ CLMA_58_37/COUT td 0.044 9.948 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/Cout
+ net (fanout=1) 0.000 9.948 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N138_5.co [8]
+ td 0.044 9.992 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/Cout
+ net (fanout=1) 0.000 9.992 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N138_5.co [10]
+ r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/Cin
+
+ Data arrival time 9.992 Logic Levels: 5
+ Logic: 3.486ns(55.973%), Route: 2.742ns(44.027%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 20.000 20.000 r
+ P20 0.000 20.000 r clk (port)
+ net (fanout=1) 0.074 20.074 clk
+ IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 21.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 21.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 22.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.907 23.448 ntclkbufg_1
+ CLMA_58_41/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/CLK
+ clock pessimism 0.281 23.729
+ clock uncertainty -0.150 23.579
+
+ Setup time -0.128 23.451
+
+ Data required time 23.451
+----------------------------------------------------------------------------------------------------
+ Data required time 23.451
+ Data arrival time 9.992
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 13.459
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK
+Endpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10]
+Path Group : clk_50m
+Path Type : min (fast corner)
+Path Class : sequential timing path
+Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.736
+ Launch Clock Delay : 3.436
+ Clock Pessimism Removal : -0.281
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 1.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.895 3.436 ntclkbufg_1
+ CLMS_50_117/CLK r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK
+
+ CLMS_50_117/Q0 tco 0.182 3.618 r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0
+ net (fanout=5) 0.146 3.764 u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/wr_addr [8]
+ DRM_54_108/ADA0[10] r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10]
+
+ Data arrival time 3.764 Logic Levels: 0
+ Logic: 0.182ns(55.488%), Route: 0.146ns(44.512%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.925 3.736 ntclkbufg_1
+ DRM_54_108/CLKA[0] r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA
+ clock pessimism -0.281 3.455
+ clock uncertainty 0.000 3.455
+
+ Hold time 0.166 3.621
+
+ Data required time 3.621
+----------------------------------------------------------------------------------------------------
+ Data required time 3.621
+ Data arrival time 3.764
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 0.143
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2]
+Path Group : clk_50m
+Path Type : min (fast corner)
+Path Class : sequential timing path
+Clock Skew : 0.008 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.760
+ Launch Clock Delay : 3.471
+ Clock Pessimism Removal : -0.281
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 1.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.930 3.471 ntclkbufg_1
+ CLMA_50_32/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK
+
+ CLMA_50_32/Q0 tco 0.182 3.653 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q0
+ net (fanout=4) 0.143 3.796 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [0]
+ DRM_54_24/ADA0[2] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2]
+
+ Data arrival time 3.796 Logic Levels: 0
+ Logic: 0.182ns(56.000%), Route: 0.143ns(44.000%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.949 3.760 ntclkbufg_1
+ DRM_54_24/CLKA[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA
+ clock pessimism -0.281 3.479
+ clock uncertainty 0.000 3.479
+
+ Hold time 0.144 3.623
+
+ Data required time 3.623
+----------------------------------------------------------------------------------------------------
+ Data required time 3.623
+ Data arrival time 3.796
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 0.173
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK
+Endpoint : image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[4]
+Path Group : clk_50m
+Path Type : min (fast corner)
+Path Class : sequential timing path
+Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.848
+ Launch Clock Delay : 3.546
+ Clock Pessimism Removal : -0.283
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 1.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 1.005 3.546 ntclkbufg_1
+ CLMS_78_305/CLK r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK
- CLMA_182_209/Q3 tco 0.182 5.832 r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/Q
- net (fanout=2) 0.199 6.031 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length [7]
- CLMA_186_208/A1 r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/I01
+ CLMS_78_305/Q1 tco 0.184 3.730 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q1
+ net (fanout=4) 0.142 3.872 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/wr_addr [1]
+ DRM_82_292/ADA0[4] r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[4]
- Data arrival time 6.031 Logic Levels: 0
- Logic: 0.182ns(47.769%), Route: 0.199ns(52.231%)
+ Data arrival time 3.872 Logic Levels: 0
+ Logic: 0.184ns(56.442%), Route: 0.142ns(43.558%)
----------------------------------------------------------------------------------------------------
- Clock eth_rxc (rising edge) 0.000 0.000 r
- F14 0.000 0.000 r eth_rxc (port)
- net (fanout=1) 0.057 0.057 eth_rxc
- IOBD_240_376/DIN td 0.861 0.918 r eth_rxc_ibuf/opit_0/O
- net (fanout=1) 0.000 0.918 eth_rxc_ibuf/ntD
- IOL_243_374/INCK td 0.058 0.976 r eth_rxc_ibuf/opit_1/INCK
- net (fanout=1) 0.370 1.346 _N66
- IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
- net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
- USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.925 6.734 gmii_clk
- CLMA_186_208/CLK r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/CLK
- clock pessimism -1.065 5.669
- clock uncertainty 0.200 5.869
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 1.037 3.848 ntclkbufg_1
+ DRM_82_292/CLKA[0] r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism -0.283 3.565
+ clock uncertainty 0.000 3.565
- Hold time -0.093 5.776
+ Hold time 0.127 3.692
- Data required time 5.776
+ Data required time 3.692
----------------------------------------------------------------------------------------------------
- Data required time 5.776
- Data arrival time 6.031
+ Data required time 3.692
+ Data arrival time 3.872
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.255
+ Slack (MET) 0.180
====================================================================================================
====================================================================================================
-Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
-Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
-Path Group : clk_50m
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE
+Path Group : clk_200m
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.066 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.436
- Launch Clock Delay : 3.783
- Clock Pessimism Removal : 0.281
+Clock Skew : -0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.432
+ Launch Clock Delay : 3.732
+ Clock Pessimism Removal : 0.299
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.614 2.811 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.972 3.783 ntclkbufg_1
- DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
-
- DRM_82_4/QB0[0] tco 1.780 5.563 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0]
- net (fanout=6) 0.946 6.509 u_rotate_image/dout [0]
- CLMS_74_73/Y1 td 0.151 6.660 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z
- net (fanout=3) 0.793 7.453 u_rotate_image/addr_fifo_rd_en
- td 0.222 7.675 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 7.675 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637
- CLMS_78_9/Y3 td 0.387 8.062 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1
- net (fanout=1) 0.236 8.298 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [3]
- CLMS_74_13/Y3 td 0.151 8.449 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z
- net (fanout=3) 0.496 8.945 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [3]
- td 0.368 9.313 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2/Cout
- net (fanout=1) 0.000 9.313 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [2]
- CLMA_90_20/COUT td 0.044 9.357 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 9.357 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6]
- CLMA_90_24/Y1 td 0.366 9.723 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1
- net (fanout=1) 0.353 10.076 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21
- CLMA_94_16/C4 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
-
- Data arrival time 10.076 Logic Levels: 5
- Logic: 3.469ns(55.125%), Route: 2.824ns(44.875%)
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_90_197/Q1 tco 0.223 3.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q
+ net (fanout=2) 0.259 4.214 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15]
+ CLMS_94_197/Y0 td 0.376 4.590 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z
+ net (fanout=2) 0.075 4.665 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154
+ CLMA_94_196/Y2 td 0.379 5.044 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z
+ net (fanout=1) 0.067 5.111 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157
+ CLMA_94_196/Y3 td 0.222 5.333 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z
+ net (fanout=11) 0.279 5.612 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43
+ CLMA_90_185/CECO td 0.132 5.744 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 5.744 ntR1851
+ CLMA_90_193/CECO td 0.132 5.876 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 5.876 ntR1850
+ CLMA_90_197/CECI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 5.876 Logic Levels: 5
+ Logic: 1.464ns(68.284%), Route: 0.680ns(31.716%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 20.000 20.000 r
- P20 0.000 20.000 r clk (port)
- net (fanout=1) 0.074 20.074 clk
- IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 21.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 21.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 22.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.895 23.436 ntclkbufg_1
- CLMA_94_16/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK
- clock pessimism 0.281 23.717
- clock uncertainty -0.150 23.567
+ Clock clk_200m (rising edge) 5.000 5.000 r
+ P20 0.000 5.000 r clk (port)
+ net (fanout=1) 0.074 5.074 clk
+ IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 6.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 6.860 _N69
+ PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 7.537 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.299 8.731
+ clock uncertainty -0.150 8.581
- Setup time -0.078 23.489
+ Setup time -0.576 8.005
- Data required time 23.489
+ Data required time 8.005
----------------------------------------------------------------------------------------------------
- Data required time 23.489
- Data arrival time 10.076
+ Data required time 8.005
+ Data arrival time 5.876
----------------------------------------------------------------------------------------------------
- Slack (MET) 13.413
+ Slack (MET) 2.129
====================================================================================================
====================================================================================================
-Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
-Endpoint : u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
-Path Group : clk_50m
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE
+Path Group : clk_200m
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.066 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.436
- Launch Clock Delay : 3.783
- Clock Pessimism Removal : 0.281
+Clock Skew : -0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.432
+ Launch Clock Delay : 3.732
+ Clock Pessimism Removal : 0.299
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.614 2.811 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.972 3.783 ntclkbufg_1
- DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
-
- DRM_82_4/QB0[0] tco 1.780 5.563 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0]
- net (fanout=6) 0.772 6.335 u_rotate_image/dout [0]
- CLMS_74_73/Y3 td 0.358 6.693 f u_rotate_image/fifo_data_valid/opit_0_L5Q_perm/Z
- net (fanout=3) 0.535 7.228 u_rotate_image/N170
- td 0.222 7.450 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 7.450 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16662
- CLMA_58_92/Y3 td 0.387 7.837 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1
- net (fanout=1) 0.162 7.999 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11 [3]
- CLMA_58_89/Y3 td 0.358 8.357 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z
- net (fanout=1) 0.478 8.835 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/rrptr [3]
- td 0.368 9.203 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2/Cout
- net (fanout=1) 0.000 9.203 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [2]
- CLMS_50_93/COUT td 0.044 9.247 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 9.247 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [6]
- CLMS_50_97/Y0 td 0.123 9.370 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Y0
- net (fanout=1) 0.151 9.521 _N70
- CLMS_50_97/C4 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
-
- Data arrival time 9.521 Logic Levels: 5
- Logic: 3.640ns(63.437%), Route: 2.098ns(36.563%)
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_90_197/Q1 tco 0.223 3.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q
+ net (fanout=2) 0.259 4.214 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15]
+ CLMS_94_197/Y0 td 0.376 4.590 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z
+ net (fanout=2) 0.075 4.665 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154
+ CLMA_94_196/Y2 td 0.379 5.044 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z
+ net (fanout=1) 0.067 5.111 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157
+ CLMA_94_196/Y3 td 0.222 5.333 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z
+ net (fanout=11) 0.279 5.612 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43
+ CLMA_90_185/CECO td 0.132 5.744 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 5.744 ntR1851
+ CLMA_90_193/CECO td 0.132 5.876 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 5.876 ntR1850
+ CLMA_90_197/CECI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 5.876 Logic Levels: 5
+ Logic: 1.464ns(68.284%), Route: 0.680ns(31.716%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 20.000 20.000 r
- P20 0.000 20.000 r clk (port)
- net (fanout=1) 0.074 20.074 clk
- IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 21.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 21.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 22.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.895 23.436 ntclkbufg_1
- CLMS_50_97/CLK r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK
- clock pessimism 0.281 23.717
- clock uncertainty -0.150 23.567
+ Clock clk_200m (rising edge) 5.000 5.000 r
+ P20 0.000 5.000 r clk (port)
+ net (fanout=1) 0.074 5.074 clk
+ IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 6.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 6.860 _N69
+ PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 7.537 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.299 8.731
+ clock uncertainty -0.150 8.581
- Setup time -0.094 23.473
+ Setup time -0.576 8.005
- Data required time 23.473
+ Data required time 8.005
----------------------------------------------------------------------------------------------------
- Data required time 23.473
- Data arrival time 9.521
+ Data required time 8.005
+ Data arrival time 5.876
----------------------------------------------------------------------------------------------------
- Slack (MET) 13.952
+ Slack (MET) 2.129
====================================================================================================
====================================================================================================
-Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
-Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
-Path Group : clk_50m
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CE
+Path Group : clk_200m
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.066 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.436
- Launch Clock Delay : 3.783
- Clock Pessimism Removal : 0.281
+Clock Skew : -0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.432
+ Launch Clock Delay : 3.732
+ Clock Pessimism Removal : 0.299
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.614 2.811 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.972 3.783 ntclkbufg_1
- DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
-
- DRM_82_4/QB0[0] tco 1.780 5.563 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0]
- net (fanout=6) 0.946 6.509 u_rotate_image/dout [0]
- CLMS_74_73/Y1 td 0.151 6.660 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z
- net (fanout=3) 0.793 7.453 u_rotate_image/addr_fifo_rd_en
- td 0.222 7.675 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 7.675 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637
- CLMS_78_9/COUT td 0.044 7.719 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 7.719 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16639
- td 0.044 7.763 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Cout
- net (fanout=1) 0.000 7.763 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16641
- CLMS_78_13/Y3 td 0.387 8.150 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/Y1
- net (fanout=1) 0.234 8.384 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [7]
- CLMS_74_13/Y1 td 0.151 8.535 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[7]/gateop_perm/Z
- net (fanout=3) 0.323 8.858 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [7]
- CLMA_94_12/COUT td 0.397 9.255 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 9.255 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6]
- CLMA_94_16/CIN r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
-
- Data arrival time 9.255 Logic Levels: 5
- Logic: 3.176ns(58.041%), Route: 2.296ns(41.959%)
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_90_197/Q1 tco 0.223 3.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q
+ net (fanout=2) 0.259 4.214 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15]
+ CLMS_94_197/Y0 td 0.376 4.590 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z
+ net (fanout=2) 0.075 4.665 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154
+ CLMA_94_196/Y2 td 0.379 5.044 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z
+ net (fanout=1) 0.067 5.111 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157
+ CLMA_94_196/Y3 td 0.222 5.333 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z
+ net (fanout=11) 0.279 5.612 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43
+ CLMA_90_185/CECO td 0.132 5.744 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 5.744 ntR1851
+ CLMA_90_193/CECO td 0.132 5.876 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 5.876 ntR1850
+ CLMA_90_197/CECI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 5.876 Logic Levels: 5
+ Logic: 1.464ns(68.284%), Route: 0.680ns(31.716%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 20.000 20.000 r
- P20 0.000 20.000 r clk (port)
- net (fanout=1) 0.074 20.074 clk
- IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 21.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 21.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 22.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.895 23.436 ntclkbufg_1
- CLMA_94_16/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK
- clock pessimism 0.281 23.717
- clock uncertainty -0.150 23.567
+ Clock clk_200m (rising edge) 5.000 5.000 r
+ P20 0.000 5.000 r clk (port)
+ net (fanout=1) 0.074 5.074 clk
+ IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 6.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 6.860 _N69
+ PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 7.537 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.299 8.731
+ clock uncertainty -0.150 8.581
- Setup time -0.276 23.291
+ Setup time -0.576 8.005
- Data required time 23.291
+ Data required time 8.005
----------------------------------------------------------------------------------------------------
- Data required time 23.291
- Data arrival time 9.255
+ Data required time 8.005
+ Data arrival time 5.876
----------------------------------------------------------------------------------------------------
- Slack (MET) 14.036
+ Slack (MET) 2.129
====================================================================================================
====================================================================================================
-Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK
-Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8]
-Path Group : clk_50m
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D
+Path Group : clk_200m
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.062 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.779
- Launch Clock Delay : 3.436
- Clock Pessimism Removal : -0.281
+Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.732
+ Launch Clock Delay : 3.432
+ Clock Pessimism Removal : -0.285
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 2.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.895 3.436 ntclkbufg_1
- CLMA_90_12/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK
+ PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 2.537 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.895 3.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMS_94_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK
- CLMA_90_12/Q2 tco 0.180 3.616 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Q0
- net (fanout=3) 0.183 3.799 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [6]
- DRM_82_4/ADA0[8] f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8]
+ CLMS_94_193/Q0 tco 0.182 3.614 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/Q
+ net (fanout=3) 0.064 3.678 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d [1]
+ CLMA_94_192/M0 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D
- Data arrival time 3.799 Logic Levels: 0
- Logic: 0.180ns(49.587%), Route: 0.183ns(50.413%)
+ Data arrival time 3.678 Logic Levels: 0
+ Logic: 0.182ns(73.984%), Route: 0.064ns(26.016%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.614 2.811 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.968 3.779 ntclkbufg_1
- DRM_82_4/CLKA[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA
- clock pessimism -0.281 3.498
- clock uncertainty 0.000 3.498
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_94_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/CLK
+ clock pessimism -0.285 3.447
+ clock uncertainty 0.000 3.447
- Hold time 0.162 3.660
+ Hold time -0.011 3.436
- Data required time 3.660
+ Data required time 3.436
----------------------------------------------------------------------------------------------------
- Data required time 3.660
- Data arrival time 3.799
+ Data required time 3.436
+ Data arrival time 3.678
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.139
+ Slack (MET) 0.242
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK
-Endpoint : u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D
-Path Group : clk_50m
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4
+Path Group : clk_200m
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.016 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.757
- Launch Clock Delay : 3.456
- Clock Pessimism Removal : -0.285
+Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.732
+ Launch Clock Delay : 3.432
+ Clock Pessimism Removal : -0.300
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 2.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.915 3.456 ntclkbufg_1
- CLMA_58_88/CLK r u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK
+ PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 2.537 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.895 3.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK
- CLMA_58_88/Q3 tco 0.178 3.634 f u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/Q
- net (fanout=1) 0.058 3.692 u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr1 [8]
- CLMA_58_89/AD f u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D
+ CLMS_38_185/Q3 tco 0.178 3.610 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/Q
+ net (fanout=3) 0.061 3.671 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [4]
+ CLMS_38_185/D4 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4
- Data arrival time 3.692 Logic Levels: 0
- Logic: 0.178ns(75.424%), Route: 0.058ns(24.576%)
+ Data arrival time 3.671 Logic Levels: 0
+ Logic: 0.178ns(74.477%), Route: 0.061ns(25.523%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.614 2.811 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.946 3.757 ntclkbufg_1
- CLMA_58_89/CLK r u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK
- clock pessimism -0.285 3.472
- clock uncertainty 0.000 3.472
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism -0.300 3.432
+ clock uncertainty 0.000 3.432
- Hold time 0.040 3.512
+ Hold time -0.028 3.404
- Data required time 3.512
+ Data required time 3.404
----------------------------------------------------------------------------------------------------
- Data required time 3.512
- Data arrival time 3.692
+ Data required time 3.404
+ Data arrival time 3.671
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.180
+ Slack (MET) 0.267
====================================================================================================
====================================================================================================
-Startpoint : image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK
-Endpoint : image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D
-Path Group : clk_50m
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4
+Path Group : clk_200m
Path Type : min (fast corner)
Path Class : sequential timing path
Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.736
- Launch Clock Delay : 3.436
+ Capture Clock Delay : 3.732
+ Launch Clock Delay : 3.432
Clock Pessimism Removal : -0.299
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 2.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.895 3.436 ntclkbufg_1
- CLMA_98_148/CLK r image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK
+ PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 2.537 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.895 3.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_38_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK
- CLMA_98_148/Q3 tco 0.178 3.614 f image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/Q
- net (fanout=1) 0.058 3.672 image_filiter_inst2/hybrid_filter_inst/pixel_ff [27]
- CLMA_98_148/AD f image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D
+ CLMA_38_184/Q1 tco 0.180 3.612 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/Q
+ net (fanout=4) 0.061 3.673 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg [2]
+ CLMA_38_184/C4 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4
- Data arrival time 3.672 Logic Levels: 0
- Logic: 0.178ns(75.424%), Route: 0.058ns(24.576%)
+ Data arrival time 3.673 Logic Levels: 0
+ Logic: 0.180ns(74.689%), Route: 0.061ns(25.311%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.614 2.811 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.925 3.736 ntclkbufg_1
- CLMA_98_148/CLK r image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK
- clock pessimism -0.299 3.437
- clock uncertainty 0.000 3.437
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_38_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism -0.299 3.433
+ clock uncertainty 0.000 3.433
- Hold time 0.040 3.477
+ Hold time -0.028 3.405
- Data required time 3.477
+ Data required time 3.405
----------------------------------------------------------------------------------------------------
- Data required time 3.477
- Data arrival time 3.672
+ Data required time 3.405
+ Data arrival time 3.673
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.195
+ Slack (MET) 0.268
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK
-Endpoint : u_zoom_image/mult_image_r0_0/N2/gopapm/X[0]
-Path Group : clk_200m
+Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK
+Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D
+Path Group : clk_25m
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.542
- Launch Clock Delay : 3.732
- Clock Pessimism Removal : 0.270
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.441
+ Launch Clock Delay : 3.741
+ Clock Pessimism Removal : 0.281
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_25m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT
- net (fanout=759) 0.925 3.732 ntR3909
- APM_206_140/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK
-
- APM_206_140/P[31] tco 0.822 4.554 f u_zoom_image/mult_fra0_0/N2/gopapm/P[7]
- net (fanout=3) 1.670 6.224 u_zoom_image/coe_mult_p0_0 [7]
- APM_206_328/X[0] f u_zoom_image/mult_image_r0_0/N2/gopapm/X[0]
-
- Data arrival time 6.224 Logic Levels: 0
- Logic: 0.822ns(32.986%), Route: 1.670ns(67.014%)
+ PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.614 2.816 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMS_118_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK
+
+ CLMS_118_17/Q1 tco 0.223 3.964 f u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/Q
+ net (fanout=2) 0.262 4.226 u_ov5640/coms2_reg_config/clock_20k_cnt [4]
+ CLMA_122_16/Y3 td 0.358 4.584 f u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z
+ net (fanout=1) 0.365 4.949 u_ov5640/coms2_reg_config/_N9749
+ CLMA_122_16/Y2 td 0.150 5.099 f u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z
+ net (fanout=13) 0.372 5.471 u_ov5640/coms2_reg_config/N8
+ td 0.368 5.839 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout
+ net (fanout=1) 0.000 5.839 u_ov5640/coms2_reg_config/_N16307
+ CLMS_122_17/COUT td 0.044 5.883 r u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout
+ net (fanout=1) 0.000 5.883 u_ov5640/coms2_reg_config/_N16309
+ CLMS_122_21/Y1 td 0.366 6.249 f u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y1
+ net (fanout=1) 0.471 6.720 u_ov5640/coms2_reg_config/N1114 [10]
+ CLMS_122_17/M3 f u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D
+
+ Data arrival time 6.720 Logic Levels: 4
+ Logic: 1.509ns(50.655%), Route: 1.470ns(49.345%)
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 5.000 5.000 r
- P20 0.000 5.000 r clk (port)
- net (fanout=1) 0.074 5.074 clk
- IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 6.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 6.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 7.537 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 7.537 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.005 8.542 ntR3909
- APM_206_328/CLK r u_zoom_image/mult_image_r0_0/N2/gopapm/CLK
- clock pessimism 0.270 8.812
- clock uncertainty -0.150 8.662
+ Clock clk_25m (rising edge) 40.000 40.000 r
+ P20 0.000 40.000 r clk (port)
+ net (fanout=1) 0.074 40.074 clk
+ IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 41.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 41.860 _N69
+ PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.603 42.546 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 43.441 ntclkbufg_8
+ CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK
+ clock pessimism 0.281 43.722
+ clock uncertainty -0.150 43.572
- Setup time -1.731 6.931
+ Setup time -0.068 43.504
- Data required time 6.931
+ Data required time 43.504
----------------------------------------------------------------------------------------------------
- Data required time 6.931
- Data arrival time 6.224
+ Data required time 43.504
+ Data arrival time 6.720
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.707
+ Slack (MET) 36.784
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK
-Endpoint : u_zoom_image/mult_image_r0_0/N2/gopapm/X[3]
-Path Group : clk_200m
+Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK
+Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D
+Path Group : clk_25m
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.542
- Launch Clock Delay : 3.732
- Clock Pessimism Removal : 0.270
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.441
+ Launch Clock Delay : 3.741
+ Clock Pessimism Removal : 0.281
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_25m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT
- net (fanout=759) 0.925 3.732 ntR3909
- APM_206_140/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK
-
- APM_206_140/P[34] tco 0.822 4.554 f u_zoom_image/mult_fra0_0/N2/gopapm/P[10]
- net (fanout=3) 1.618 6.172 u_zoom_image/coe_mult_p0_0 [10]
- APM_206_328/X[3] f u_zoom_image/mult_image_r0_0/N2/gopapm/X[3]
-
- Data arrival time 6.172 Logic Levels: 0
- Logic: 0.822ns(33.689%), Route: 1.618ns(66.311%)
+ PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.614 2.816 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMS_118_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK
+
+ CLMS_118_17/Q1 tco 0.223 3.964 f u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/Q
+ net (fanout=2) 0.262 4.226 u_ov5640/coms2_reg_config/clock_20k_cnt [4]
+ CLMA_122_16/Y3 td 0.358 4.584 f u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z
+ net (fanout=1) 0.365 4.949 u_ov5640/coms2_reg_config/_N9749
+ CLMA_122_16/Y2 td 0.150 5.099 f u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z
+ net (fanout=13) 0.372 5.471 u_ov5640/coms2_reg_config/N8
+ td 0.368 5.839 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout
+ net (fanout=1) 0.000 5.839 u_ov5640/coms2_reg_config/_N16307
+ CLMS_122_17/Y3 td 0.365 6.204 f u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Y1
+ net (fanout=1) 0.488 6.692 u_ov5640/coms2_reg_config/N1114 [8]
+ CLMS_122_17/M2 f u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D
+
+ Data arrival time 6.692 Logic Levels: 3
+ Logic: 1.464ns(49.610%), Route: 1.487ns(50.390%)
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 5.000 5.000 r
- P20 0.000 5.000 r clk (port)
- net (fanout=1) 0.074 5.074 clk
- IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 6.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 6.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 7.537 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 7.537 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.005 8.542 ntR3909
- APM_206_328/CLK r u_zoom_image/mult_image_r0_0/N2/gopapm/CLK
- clock pessimism 0.270 8.812
- clock uncertainty -0.150 8.662
+ Clock clk_25m (rising edge) 40.000 40.000 r
+ P20 0.000 40.000 r clk (port)
+ net (fanout=1) 0.074 40.074 clk
+ IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 41.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 41.860 _N69
+ PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.603 42.546 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 43.441 ntclkbufg_8
+ CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK
+ clock pessimism 0.281 43.722
+ clock uncertainty -0.150 43.572
- Setup time -1.731 6.931
+ Setup time -0.068 43.504
- Data required time 6.931
+ Data required time 43.504
----------------------------------------------------------------------------------------------------
- Data required time 6.931
- Data arrival time 6.172
+ Data required time 43.504
+ Data arrival time 6.692
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.759
+ Slack (MET) 36.812
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK
-Endpoint : u_zoom_image/mult_image_r0_0/N2/gopapm/X[6]
-Path Group : clk_200m
+Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK
+Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D
+Path Group : clk_25m
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.542
- Launch Clock Delay : 3.732
- Clock Pessimism Removal : 0.270
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.441
+ Launch Clock Delay : 3.741
+ Clock Pessimism Removal : 0.281
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_25m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT
- net (fanout=759) 0.925 3.732 ntR3909
- APM_206_140/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK
-
- APM_206_140/P[37] tco 0.822 4.554 f u_zoom_image/mult_fra0_0/N2/gopapm/P[13]
- net (fanout=3) 1.614 6.168 u_zoom_image/coe_mult_p0_0 [13]
- APM_206_328/X[6] f u_zoom_image/mult_image_r0_0/N2/gopapm/X[6]
-
- Data arrival time 6.168 Logic Levels: 0
- Logic: 0.822ns(33.744%), Route: 1.614ns(66.256%)
+ PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.614 2.816 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMS_118_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK
+
+ CLMS_118_17/Q1 tco 0.223 3.964 f u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/Q
+ net (fanout=2) 0.262 4.226 u_ov5640/coms2_reg_config/clock_20k_cnt [4]
+ CLMA_122_16/Y3 td 0.358 4.584 f u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z
+ net (fanout=1) 0.365 4.949 u_ov5640/coms2_reg_config/_N9749
+ CLMA_122_16/Y2 td 0.150 5.099 f u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z
+ net (fanout=13) 0.372 5.471 u_ov5640/coms2_reg_config/N8
+ td 0.368 5.839 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout
+ net (fanout=1) 0.000 5.839 u_ov5640/coms2_reg_config/_N16307
+ CLMS_122_17/COUT td 0.044 5.883 r u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout
+ net (fanout=1) 0.000 5.883 u_ov5640/coms2_reg_config/_N16309
+ CLMS_122_21/Y0 td 0.206 6.089 f u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y0
+ net (fanout=1) 0.471 6.560 u_ov5640/coms2_reg_config/N1114 [9]
+ CLMS_122_17/M1 f u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D
+
+ Data arrival time 6.560 Logic Levels: 4
+ Logic: 1.349ns(47.854%), Route: 1.470ns(52.146%)
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 5.000 5.000 r
- P20 0.000 5.000 r clk (port)
- net (fanout=1) 0.074 5.074 clk
- IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 6.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 6.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 7.537 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 7.537 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.005 8.542 ntR3909
- APM_206_328/CLK r u_zoom_image/mult_image_r0_0/N2/gopapm/CLK
- clock pessimism 0.270 8.812
- clock uncertainty -0.150 8.662
+ Clock clk_25m (rising edge) 40.000 40.000 r
+ P20 0.000 40.000 r clk (port)
+ net (fanout=1) 0.074 40.074 clk
+ IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 41.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 41.860 _N69
+ PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.603 42.546 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 43.441 ntclkbufg_8
+ CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/CLK
+ clock pessimism 0.281 43.722
+ clock uncertainty -0.150 43.572
- Setup time -1.731 6.931
+ Setup time -0.068 43.504
- Data required time 6.931
+ Data required time 43.504
----------------------------------------------------------------------------------------------------
- Data required time 6.931
- Data arrival time 6.168
+ Data required time 43.504
+ Data arrival time 6.560
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.763
+ Slack (MET) 36.944
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK
-Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[0]
-Path Group : clk_200m
+Startpoint : u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+Endpoint : u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
+Path Group : clk_25m
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.844
- Launch Clock Delay : 3.432
- Clock Pessimism Removal : -0.270
+Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.741
+ Launch Clock Delay : 3.441
+ Clock Pessimism Removal : -0.299
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_25m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT
- net (fanout=759) 0.895 3.432 ntR3909
- APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK
+ PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.603 2.546 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 3.441 ntclkbufg_8
+ CLMS_122_9/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
- APM_206_240/PO[0] tco 0.239 3.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[0]
- net (fanout=1) 0.000 3.671 u_zoom_image/mult_image0[2] [0]
- APM_206_252/PI[0] r u_zoom_image/mult_image_g1/N2/gopapm/PI[0]
+ CLMS_122_9/Q1 tco 0.184 3.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 0.194 3.819 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ CLMS_122_9/M0 r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
- Data arrival time 3.671 Logic Levels: 0
- Logic: 0.239ns(100.000%), Route: 0.000ns(0.000%)
+ Data arrival time 3.819 Logic Levels: 0
+ Logic: 0.184ns(48.677%), Route: 0.194ns(51.323%)
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_25m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.037 3.844 ntR3909
- APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK
- clock pessimism -0.270 3.574
- clock uncertainty 0.000 3.574
+ PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.614 2.816 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMS_122_9/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
+ clock pessimism -0.299 3.442
+ clock uncertainty 0.000 3.442
- Hold time -0.099 3.475
+ Hold time -0.011 3.431
- Data required time 3.475
+ Data required time 3.431
----------------------------------------------------------------------------------------------------
- Data required time 3.475
- Data arrival time 3.671
+ Data required time 3.431
+ Data arrival time 3.819
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.196
+ Slack (MET) 0.388
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK
-Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[1]
-Path Group : clk_200m
+Startpoint : u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+Endpoint : u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
+Path Group : clk_25m
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.844
- Launch Clock Delay : 3.432
- Clock Pessimism Removal : -0.270
+Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.741
+ Launch Clock Delay : 3.441
+ Clock Pessimism Removal : -0.299
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_25m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT
- net (fanout=759) 0.895 3.432 ntR3909
- APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK
+ PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.603 2.546 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 3.441 ntclkbufg_8
+ CLMA_122_12/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK
- APM_206_240/PO[1] tco 0.239 3.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[1]
- net (fanout=1) 0.000 3.671 u_zoom_image/mult_image0[2] [1]
- APM_206_252/PI[1] r u_zoom_image/mult_image_g1/N2/gopapm/PI[1]
+ CLMA_122_12/Q1 tco 0.184 3.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 0.217 3.842 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ CLMA_122_12/M0 r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
- Data arrival time 3.671 Logic Levels: 0
- Logic: 0.239ns(100.000%), Route: 0.000ns(0.000%)
+ Data arrival time 3.842 Logic Levels: 0
+ Logic: 0.184ns(45.885%), Route: 0.217ns(54.115%)
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_25m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.037 3.844 ntR3909
- APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK
- clock pessimism -0.270 3.574
- clock uncertainty 0.000 3.574
+ PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.614 2.816 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMA_122_12/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
+ clock pessimism -0.299 3.442
+ clock uncertainty 0.000 3.442
- Hold time -0.099 3.475
+ Hold time -0.011 3.431
- Data required time 3.475
+ Data required time 3.431
----------------------------------------------------------------------------------------------------
- Data required time 3.475
- Data arrival time 3.671
+ Data required time 3.431
+ Data arrival time 3.842
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.196
+ Slack (MET) 0.411
====================================================================================================
====================================================================================================
-Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK
-Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[2]
-Path Group : clk_200m
+Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK
+Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D
+Path Group : clk_25m
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.844
- Launch Clock Delay : 3.432
- Clock Pessimism Removal : -0.270
+Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.741
+ Launch Clock Delay : 3.441
+ Clock Pessimism Removal : -0.300
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_25m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT
- net (fanout=759) 0.895 3.432 ntR3909
- APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK
+ PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.603 2.546 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 3.441 ntclkbufg_8
+ CLMS_118_13/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK
- APM_206_240/PO[2] tco 0.239 3.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[2]
- net (fanout=1) 0.000 3.671 u_zoom_image/mult_image0[2] [2]
- APM_206_252/PI[2] r u_zoom_image/mult_image_g1/N2/gopapm/PI[2]
+ CLMS_118_13/Q0 tco 0.179 3.620 f u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/Q
+ net (fanout=3) 0.061 3.681 u_ov5640/coms1_reg_config/clock_20k_cnt [1]
+ CLMS_118_13/Y0 td 0.184 3.865 r u_ov5640/coms1_reg_config/N11_2_1/gateop_A2/Y0
+ net (fanout=1) 0.065 3.930 u_ov5640/coms1_reg_config/N1114 [1]
+ CLMS_118_13/M0 r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D
- Data arrival time 3.671 Logic Levels: 0
- Logic: 0.239ns(100.000%), Route: 0.000ns(0.000%)
+ Data arrival time 3.930 Logic Levels: 1
+ Logic: 0.363ns(74.233%), Route: 0.126ns(25.767%)
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_25m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.037 3.844 ntR3909
- APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK
- clock pessimism -0.270 3.574
- clock uncertainty 0.000 3.574
+ PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
+ net (fanout=1) 0.614 2.816 clk_25m
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMS_118_13/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK
+ clock pessimism -0.300 3.441
+ clock uncertainty 0.000 3.441
- Hold time -0.099 3.475
+ Hold time -0.011 3.430
- Data required time 3.475
+ Data required time 3.430
----------------------------------------------------------------------------------------------------
- Data required time 3.475
- Data arrival time 3.671
+ Data required time 3.430
+ Data arrival time 3.930
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.196
+ Slack (MET) 0.500
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D
-Path Group : clk_25m
+Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+Endpoint : ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE
+Path Group : clk_10m
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.441
- Launch Clock Delay : 3.741
- Clock Pessimism Removal : 0.299
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.547
+ Launch Clock Delay : 3.849
+ Clock Pessimism Removal : 0.283
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 0.000 0.000 r
+ Clock clk_10m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-
- CLMA_182_17/Q0 tco 0.221 3.962 f u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q
- net (fanout=4) 0.365 4.327 u_ov5640/coms1_reg_config/clock_20k_cnt [0]
- CLMA_182_13/Y2 td 0.381 4.708 f u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z
- net (fanout=1) 0.256 4.964 u_ov5640/coms1_reg_config/_N9664
- CLMA_186_16/Y0 td 0.150 5.114 f u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z
- net (fanout=13) 0.508 5.622 u_ov5640/coms1_reg_config/N8
- CLMA_182_12/COUT td 0.391 6.013 r u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Cout
- net (fanout=1) 0.000 6.013 u_ov5640/coms1_reg_config/_N16248
- td 0.044 6.057 r u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Cout
- net (fanout=1) 0.000 6.057 u_ov5640/coms1_reg_config/_N16250
- CLMA_182_16/Y3 td 0.365 6.422 f u_ov5640/coms1_reg_config/N11_2_7/gateop_A2/Y1
- net (fanout=1) 0.375 6.797 u_ov5640/coms1_reg_config/N1114 [8]
- CLMA_182_17/M2 f u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D
-
- Data arrival time 6.797 Logic Levels: 4
- Logic: 1.552ns(50.785%), Route: 1.504ns(49.215%)
+ PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.614 2.812 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.037 3.849 ntclkbufg_4
+ CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_218_329/Q2 tco 0.223 4.072 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
+ net (fanout=3) 0.174 4.246 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
+ CLMS_218_333/Y3 td 0.358 4.604 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
+ net (fanout=1) 0.157 4.761 ms72xx_ctl/ms7200_ctl/_N96627
+ CLMS_218_333/Y0 td 0.150 4.911 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
+ net (fanout=6) 0.269 5.180 ms72xx_ctl/ms7200_ctl/_N96632
+ CLMS_222_329/Y0 td 0.150 5.330 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
+ net (fanout=15) 0.363 5.693 ms72xx_ctl/ms7200_ctl/N261
+ CLMS_214_321/Y0 td 0.264 5.957 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
+ net (fanout=4) 0.353 6.310 ms72xx_ctl/ms7200_ctl/N2093 [4]
+ CLMA_222_324/Y1 td 0.151 6.461 f ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z
+ net (fanout=12) 0.363 6.824 ms72xx_ctl/ms7200_ctl/N1955
+ CLMA_230_324/CECO td 0.132 6.956 f ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 6.956 ntR1800
+ CLMA_230_328/CECI f ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 6.956 Logic Levels: 6
+ Logic: 1.428ns(45.961%), Route: 1.679ns(54.039%)
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 40.000 40.000 r
- P20 0.000 40.000 r clk (port)
- net (fanout=1) 0.074 40.074 clk
- IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 41.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 41.860 _N69
- PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.603 42.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 43.441 ntclkbufg_7
- CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK
- clock pessimism 0.299 43.740
- clock uncertainty -0.150 43.590
+ Clock clk_10m (rising edge) 100.000 100.000 r
+ P20 0.000 100.000 r clk (port)
+ net (fanout=1) 0.074 100.074 clk
+ IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 101.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 101.860 _N69
+ PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.603 102.542 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.005 103.547 ntclkbufg_4
+ CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.283 103.830
+ clock uncertainty -0.150 103.680
- Setup time -0.068 43.522
+ Setup time -0.576 103.104
- Data required time 43.522
+ Data required time 103.104
----------------------------------------------------------------------------------------------------
- Data required time 43.522
- Data arrival time 6.797
+ Data required time 103.104
+ Data arrival time 6.956
----------------------------------------------------------------------------------------------------
- Slack (MET) 36.725
+ Slack (MET) 96.148
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[10]/opit_0_inv/D
-Path Group : clk_25m
+Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+Endpoint : ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE
+Path Group : clk_10m
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.441
- Launch Clock Delay : 3.741
- Clock Pessimism Removal : 0.285
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.547
+ Launch Clock Delay : 3.849
+ Clock Pessimism Removal : 0.283
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 0.000 0.000 r
+ Clock clk_10m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-
- CLMA_182_17/Q0 tco 0.221 3.962 f u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q
- net (fanout=4) 0.365 4.327 u_ov5640/coms1_reg_config/clock_20k_cnt [0]
- CLMA_182_13/Y2 td 0.381 4.708 f u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z
- net (fanout=1) 0.256 4.964 u_ov5640/coms1_reg_config/_N9664
- CLMA_186_16/Y0 td 0.150 5.114 f u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z
- net (fanout=13) 0.508 5.622 u_ov5640/coms1_reg_config/N8
- CLMA_182_12/COUT td 0.391 6.013 r u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Cout
- net (fanout=1) 0.000 6.013 u_ov5640/coms1_reg_config/_N16248
- td 0.044 6.057 r u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Cout
- net (fanout=1) 0.000 6.057 u_ov5640/coms1_reg_config/_N16250
- CLMA_182_16/COUT td 0.044 6.101 r u_ov5640/coms1_reg_config/N11_2_7/gateop_A2/Cout
- net (fanout=1) 0.000 6.101 u_ov5640/coms1_reg_config/_N16252
- CLMA_182_20/Y1 td 0.366 6.467 f u_ov5640/coms1_reg_config/N11_2_9/gateop_A2/Y1
- net (fanout=1) 0.273 6.740 u_ov5640/coms1_reg_config/N1114 [10]
- CLMA_182_20/M0 f u_ov5640/coms1_reg_config/clock_20k_cnt[10]/opit_0_inv/D
-
- Data arrival time 6.740 Logic Levels: 5
- Logic: 1.597ns(53.251%), Route: 1.402ns(46.749%)
+ PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.614 2.812 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.037 3.849 ntclkbufg_4
+ CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_218_329/Q2 tco 0.223 4.072 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
+ net (fanout=3) 0.174 4.246 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
+ CLMS_218_333/Y3 td 0.358 4.604 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
+ net (fanout=1) 0.157 4.761 ms72xx_ctl/ms7200_ctl/_N96627
+ CLMS_218_333/Y0 td 0.150 4.911 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
+ net (fanout=6) 0.269 5.180 ms72xx_ctl/ms7200_ctl/_N96632
+ CLMS_222_329/Y0 td 0.150 5.330 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
+ net (fanout=15) 0.363 5.693 ms72xx_ctl/ms7200_ctl/N261
+ CLMS_214_321/Y0 td 0.264 5.957 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
+ net (fanout=4) 0.353 6.310 ms72xx_ctl/ms7200_ctl/N2093 [4]
+ CLMA_222_324/Y1 td 0.151 6.461 f ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z
+ net (fanout=12) 0.363 6.824 ms72xx_ctl/ms7200_ctl/N1955
+ CLMA_230_324/CECO td 0.132 6.956 f ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 6.956 ntR1800
+ CLMA_230_328/CECI f ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 6.956 Logic Levels: 6
+ Logic: 1.428ns(45.961%), Route: 1.679ns(54.039%)
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 40.000 40.000 r
- P20 0.000 40.000 r clk (port)
- net (fanout=1) 0.074 40.074 clk
- IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 41.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 41.860 _N69
- PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.603 42.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 43.441 ntclkbufg_7
- CLMA_182_20/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK
- clock pessimism 0.285 43.726
- clock uncertainty -0.150 43.576
+ Clock clk_10m (rising edge) 100.000 100.000 r
+ P20 0.000 100.000 r clk (port)
+ net (fanout=1) 0.074 100.074 clk
+ IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 101.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 101.860 _N69
+ PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.603 102.542 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.005 103.547 ntclkbufg_4
+ CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.283 103.830
+ clock uncertainty -0.150 103.680
- Setup time -0.068 43.508
+ Setup time -0.576 103.104
- Data required time 43.508
+ Data required time 103.104
----------------------------------------------------------------------------------------------------
- Data required time 43.508
- Data arrival time 6.740
+ Data required time 103.104
+ Data arrival time 6.956
----------------------------------------------------------------------------------------------------
- Slack (MET) 36.768
+ Slack (MET) 96.148
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D
-Path Group : clk_25m
+Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+Endpoint : ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE
+Path Group : clk_10m
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.441
- Launch Clock Delay : 3.741
- Clock Pessimism Removal : 0.285
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.547
+ Launch Clock Delay : 3.849
+ Clock Pessimism Removal : 0.283
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 0.000 0.000 r
+ Clock clk_10m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_21/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
-
- CLMA_182_21/Q2 tco 0.223 3.964 f u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q
- net (fanout=4) 0.352 4.316 u_ov5640/coms2_reg_config/clock_20k_cnt [0]
- CLMA_186_16/Y1 td 0.360 4.676 f u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z
- net (fanout=1) 0.251 4.927 u_ov5640/coms2_reg_config/_N9736
- CLMA_186_20/Y1 td 0.244 5.171 f u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z
- net (fanout=13) 0.398 5.569 u_ov5640/coms2_reg_config/N8
- td 0.368 5.937 f u_ov5640/coms2_reg_config/N11_2_1/gateop_A2/Cout
- net (fanout=1) 0.000 5.937 u_ov5640/coms2_reg_config/_N16399
- CLMA_182_21/COUT td 0.044 5.981 r u_ov5640/coms2_reg_config/N11_2_3/gateop_A2/Cout
- net (fanout=1) 0.000 5.981 u_ov5640/coms2_reg_config/_N16401
- CLMA_182_25/Y1 td 0.366 6.347 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Y1
- net (fanout=1) 0.393 6.740 u_ov5640/coms2_reg_config/N1114 [6]
- CLMA_182_20/M1 f u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D
-
- Data arrival time 6.740 Logic Levels: 4
- Logic: 1.605ns(53.518%), Route: 1.394ns(46.482%)
+ PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.614 2.812 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.037 3.849 ntclkbufg_4
+ CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_218_329/Q2 tco 0.223 4.072 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
+ net (fanout=3) 0.174 4.246 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
+ CLMS_218_333/Y3 td 0.358 4.604 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
+ net (fanout=1) 0.157 4.761 ms72xx_ctl/ms7200_ctl/_N96627
+ CLMS_218_333/Y0 td 0.150 4.911 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
+ net (fanout=6) 0.269 5.180 ms72xx_ctl/ms7200_ctl/_N96632
+ CLMS_222_329/Y0 td 0.150 5.330 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
+ net (fanout=15) 0.363 5.693 ms72xx_ctl/ms7200_ctl/N261
+ CLMS_214_321/Y0 td 0.264 5.957 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
+ net (fanout=4) 0.353 6.310 ms72xx_ctl/ms7200_ctl/N2093 [4]
+ CLMA_222_324/Y1 td 0.151 6.461 f ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z
+ net (fanout=12) 0.363 6.824 ms72xx_ctl/ms7200_ctl/N1955
+ CLMA_230_324/CECO td 0.132 6.956 f ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT
+ net (fanout=4) 0.000 6.956 ntR1800
+ CLMA_230_328/CECI f ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE
+
+ Data arrival time 6.956 Logic Levels: 6
+ Logic: 1.428ns(45.961%), Route: 1.679ns(54.039%)
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 40.000 40.000 r
- P20 0.000 40.000 r clk (port)
- net (fanout=1) 0.074 40.074 clk
- IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 41.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 41.860 _N69
- PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.603 42.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 43.441 ntclkbufg_7
- CLMA_182_20/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/CLK
- clock pessimism 0.285 43.726
- clock uncertainty -0.150 43.576
+ Clock clk_10m (rising edge) 100.000 100.000 r
+ P20 0.000 100.000 r clk (port)
+ net (fanout=1) 0.074 100.074 clk
+ IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 101.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 101.860 _N69
+ PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.603 102.542 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.005 103.547 ntclkbufg_4
+ CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.283 103.830
+ clock uncertainty -0.150 103.680
- Setup time -0.068 43.508
+ Setup time -0.576 103.104
- Data required time 43.508
+ Data required time 103.104
----------------------------------------------------------------------------------------------------
- Data required time 43.508
- Data arrival time 6.740
+ Data required time 103.104
+ Data arrival time 6.956
----------------------------------------------------------------------------------------------------
- Slack (MET) 36.768
+ Slack (MET) 96.148
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
-Endpoint : u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
-Path Group : clk_25m
+Startpoint : ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK
+Endpoint : ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D
+Path Group : clk_10m
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.741
- Launch Clock Delay : 3.441
- Clock Pessimism Removal : -0.299
+Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.849
+ Launch Clock Delay : 3.547
+ Clock Pessimism Removal : -0.287
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 0.000 0.000 r
+ Clock clk_10m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.603 2.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 3.441 ntclkbufg_7
- CLMA_182_12/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+ PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.603 2.542 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.005 3.547 ntclkbufg_4
+ CLMA_194_305/CLK r ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK
- CLMA_182_12/Q1 tco 0.184 3.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 0.212 3.837 u_ov5640/coms1_reg_config/clk_20k_regdiv
- CLMA_182_12/M0 r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
+ CLMA_194_305/Y2 tco 0.228 3.775 f ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/Q
+ net (fanout=2) 0.059 3.834 ms72xx_ctl/iic_dri_tx/receiv_data [5]
+ CLMA_194_304/CD f ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D
- Data arrival time 3.837 Logic Levels: 0
- Logic: 0.184ns(46.465%), Route: 0.212ns(53.535%)
+ Data arrival time 3.834 Logic Levels: 0
+ Logic: 0.228ns(79.443%), Route: 0.059ns(20.557%)
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 0.000 0.000 r
+ Clock clk_10m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_12/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
- clock pessimism -0.299 3.442
- clock uncertainty 0.000 3.442
+ PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.614 2.812 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.037 3.849 ntclkbufg_4
+ CLMA_194_304/CLK r ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/CLK
+ clock pessimism -0.287 3.562
+ clock uncertainty 0.000 3.562
- Hold time -0.011 3.431
+ Hold time 0.040 3.602
- Data required time 3.431
+ Data required time 3.602
----------------------------------------------------------------------------------------------------
- Data required time 3.431
- Data arrival time 3.837
+ Data required time 3.602
+ Data arrival time 3.834
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.406
+ Slack (MET) 0.232
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK
-Endpoint : u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
-Path Group : clk_25m
+Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK
+Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[10]
+Path Group : clk_10m
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.741
- Launch Clock Delay : 3.441
- Clock Pessimism Removal : -0.299
+Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.849
+ Launch Clock Delay : 3.547
+ Clock Pessimism Removal : -0.283
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 0.000 0.000 r
+ Clock clk_10m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.603 2.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 3.441 ntclkbufg_7
- CLMA_182_25/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+ PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.603 2.542 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.005 3.547 ntclkbufg_4
+ CLMA_230_325/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK
- CLMA_182_25/Q1 tco 0.184 3.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 0.288 3.913 u_ov5640/coms2_reg_config/clk_20k_regdiv
- CLMA_182_25/M0 r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
+ CLMA_230_325/Q1 tco 0.184 3.731 r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q1
+ net (fanout=3) 0.197 3.928 ms72xx_ctl/ms7200_ctl/cmd_index [5]
+ DRM_234_316/ADA0[10] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[10]
- Data arrival time 3.913 Logic Levels: 0
- Logic: 0.184ns(38.983%), Route: 0.288ns(61.017%)
+ Data arrival time 3.928 Logic Levels: 0
+ Logic: 0.184ns(48.294%), Route: 0.197ns(51.706%)
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 0.000 0.000 r
+ Clock clk_10m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_25/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
- clock pessimism -0.299 3.442
- clock uncertainty 0.000 3.442
+ PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.614 2.812 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.037 3.849 ntclkbufg_4
+ DRM_234_316/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
+ clock pessimism -0.283 3.566
+ clock uncertainty 0.000 3.566
- Hold time -0.011 3.431
+ Hold time 0.127 3.693
- Data required time 3.431
+ Data required time 3.693
----------------------------------------------------------------------------------------------------
- Data required time 3.431
- Data arrival time 3.913
+ Data required time 3.693
+ Data arrival time 3.928
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.482
+ Slack (MET) 0.235
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK
-Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D
-Path Group : clk_25m
+Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK
+Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12]
+Path Group : clk_10m
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.741
- Launch Clock Delay : 3.441
- Clock Pessimism Removal : -0.300
+Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.849
+ Launch Clock Delay : 3.547
+ Clock Pessimism Removal : -0.283
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 0.000 0.000 r
+ Clock clk_10m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.603 2.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 3.441 ntclkbufg_7
- CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK
+ PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.603 2.542 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.005 3.547 ntclkbufg_4
+ CLMA_230_325/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK
- CLMA_182_17/Y0 tco 0.228 3.669 f u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/Q
- net (fanout=2) 0.060 3.729 u_ov5640/coms1_reg_config/clock_20k_cnt [5]
- CLMA_182_16/Y0 td 0.184 3.913 r u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Y0
- net (fanout=1) 0.131 4.044 u_ov5640/coms1_reg_config/N1114 [5]
- CLMA_182_17/AD r u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D
+ CLMA_230_325/Q3 tco 0.182 3.729 r ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/Q1
+ net (fanout=3) 0.199 3.928 ms72xx_ctl/ms7200_ctl/cmd_index [7]
+ DRM_234_316/ADA0[12] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12]
- Data arrival time 4.044 Logic Levels: 1
- Logic: 0.412ns(68.325%), Route: 0.191ns(31.675%)
+ Data arrival time 3.928 Logic Levels: 0
+ Logic: 0.182ns(47.769%), Route: 0.199ns(52.231%)
----------------------------------------------------------------------------------------------------
- Clock clk_25m (rising edge) 0.000 0.000 r
+ Clock clk_10m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
- net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK
- clock pessimism -0.300 3.441
- clock uncertainty 0.000 3.441
+ PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.614 2.812 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.037 3.849 ntclkbufg_4
+ DRM_234_316/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
+ clock pessimism -0.283 3.566
+ clock uncertainty 0.000 3.566
- Hold time 0.034 3.475
+ Hold time 0.127 3.693
- Data required time 3.475
+ Data required time 3.693
----------------------------------------------------------------------------------------------------
- Data required time 3.475
- Data arrival time 4.044
+ Data required time 3.693
+ Data arrival time 3.928
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.569
+ Slack (MET) 0.235
====================================================================================================
====================================================================================================
-Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-Endpoint : ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE
-Path Group : clk_10m
+Startpoint : u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+Endpoint : u_zoom_image/mult_image_g1_0/N2/gopapm/X[3]
+Path Group : clk_1080p60Hz
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.437
- Launch Clock Delay : 3.737
- Clock Pessimism Removal : 0.285
+Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.520
+ Launch Clock Delay : 5.994
+ Clock Pessimism Removal : 0.332
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.614 2.812 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.925 3.737 ntclkbufg_3
- CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-
- CLMS_242_113/Q3 tco 0.220 3.957 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
- net (fanout=3) 0.274 4.231 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
- CLMS_246_113/Y2 td 0.381 4.612 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
- net (fanout=1) 0.069 4.681 ms72xx_ctl/ms7200_ctl/_N95853
- CLMS_246_113/Y0 td 0.150 4.831 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
- net (fanout=6) 0.271 5.102 ms72xx_ctl/ms7200_ctl/_N95857
- CLMS_242_117/Y1 td 0.244 5.346 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
- net (fanout=15) 0.506 5.852 ms72xx_ctl/ms7200_ctl/N261
- CLMA_226_104/Y1 td 0.151 6.003 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
- net (fanout=4) 0.309 6.312 ms72xx_ctl/ms7200_ctl/N2093 [4]
- CLMA_230_121/Y3 td 0.360 6.672 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z
- net (fanout=12) 0.302 6.974 ms72xx_ctl/ms7200_ctl/N1955
- CLMA_242_116/CECO td 0.141 7.115 r ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CEOUT
- net (fanout=4) 0.000 7.115 ntR1773
- CLMA_242_120/CECI r ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE
-
- Data arrival time 7.115 Logic Levels: 6
- Logic: 1.647ns(48.757%), Route: 1.731ns(51.243%)
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.037 5.994 ntclkbufg_3
+ APM_206_264/CLK r u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+
+ APM_206_264/P[34] tco 0.822 6.816 f u_zoom_image/mult_fra1_0/N2/gopapm/P[10]
+ net (fanout=3) 1.403 8.219 u_zoom_image/coe_mult_p1_0 [10]
+ APM_206_140/X[3] f u_zoom_image/mult_image_g1_0/N2/gopapm/X[3]
+
+ Data arrival time 8.219 Logic Levels: 0
+ Logic: 0.822ns(36.944%), Route: 1.403ns(63.056%)
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 100.000 100.000 r
- P20 0.000 100.000 r clk (port)
- net (fanout=1) 0.074 100.074 clk
- IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 101.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 101.860 _N69
- PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.603 102.542 clk_10m
- USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.895 103.437 ntclkbufg_3
- CLMA_242_120/CLK r ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK
- clock pessimism 0.285 103.722
- clock uncertainty -0.150 103.572
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.095 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 8.596 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 9.277 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 10.368 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 11.361 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.895 12.256 ntclkbufg_3
+ APM_206_140/CLK r u_zoom_image/mult_image_g1_0/N2/gopapm/CLK
+ clock pessimism 0.332 12.588
+ clock uncertainty -0.150 12.438
- Setup time -0.563 103.009
+ Setup time -1.731 10.707
- Data required time 103.009
+ Data required time 10.707
----------------------------------------------------------------------------------------------------
- Data required time 103.009
- Data arrival time 7.115
+ Data required time 10.707
+ Data arrival time 8.219
----------------------------------------------------------------------------------------------------
- Slack (MET) 95.894
+ Slack (MET) 2.488
====================================================================================================
====================================================================================================
-Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-Endpoint : ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CE
-Path Group : clk_10m
+Startpoint : u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+Endpoint : u_zoom_image/mult_image_g1_0/N2/gopapm/X[0]
+Path Group : clk_1080p60Hz
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.437
- Launch Clock Delay : 3.737
- Clock Pessimism Removal : 0.285
+Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.520
+ Launch Clock Delay : 5.994
+ Clock Pessimism Removal : 0.332
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.614 2.812 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.925 3.737 ntclkbufg_3
- CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-
- CLMS_242_113/Q3 tco 0.220 3.957 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
- net (fanout=3) 0.274 4.231 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
- CLMS_246_113/Y2 td 0.381 4.612 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
- net (fanout=1) 0.069 4.681 ms72xx_ctl/ms7200_ctl/_N95853
- CLMS_246_113/Y0 td 0.150 4.831 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
- net (fanout=6) 0.271 5.102 ms72xx_ctl/ms7200_ctl/_N95857
- CLMS_242_117/Y1 td 0.244 5.346 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
- net (fanout=15) 0.506 5.852 ms72xx_ctl/ms7200_ctl/N261
- CLMA_226_104/Y1 td 0.151 6.003 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
- net (fanout=4) 0.309 6.312 ms72xx_ctl/ms7200_ctl/N2093 [4]
- CLMA_230_121/Y3 td 0.360 6.672 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z
- net (fanout=12) 0.302 6.974 ms72xx_ctl/ms7200_ctl/N1955
- CLMA_242_116/CECO td 0.141 7.115 r ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CEOUT
- net (fanout=4) 0.000 7.115 ntR1773
- CLMA_242_120/CECI r ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CE
-
- Data arrival time 7.115 Logic Levels: 6
- Logic: 1.647ns(48.757%), Route: 1.731ns(51.243%)
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.037 5.994 ntclkbufg_3
+ APM_206_264/CLK r u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+
+ APM_206_264/P[31] tco 0.822 6.816 f u_zoom_image/mult_fra1_0/N2/gopapm/P[7]
+ net (fanout=3) 1.398 8.214 u_zoom_image/coe_mult_p1_0 [7]
+ APM_206_140/X[0] f u_zoom_image/mult_image_g1_0/N2/gopapm/X[0]
+
+ Data arrival time 8.214 Logic Levels: 0
+ Logic: 0.822ns(37.027%), Route: 1.398ns(62.973%)
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 100.000 100.000 r
- P20 0.000 100.000 r clk (port)
- net (fanout=1) 0.074 100.074 clk
- IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 101.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 101.860 _N69
- PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.603 102.542 clk_10m
- USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.895 103.437 ntclkbufg_3
- CLMA_242_120/CLK r ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CLK
- clock pessimism 0.285 103.722
- clock uncertainty -0.150 103.572
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.095 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 8.596 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 9.277 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 10.368 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 11.361 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.895 12.256 ntclkbufg_3
+ APM_206_140/CLK r u_zoom_image/mult_image_g1_0/N2/gopapm/CLK
+ clock pessimism 0.332 12.588
+ clock uncertainty -0.150 12.438
- Setup time -0.563 103.009
+ Setup time -1.731 10.707
- Data required time 103.009
+ Data required time 10.707
----------------------------------------------------------------------------------------------------
- Data required time 103.009
- Data arrival time 7.115
+ Data required time 10.707
+ Data arrival time 8.214
----------------------------------------------------------------------------------------------------
- Slack (MET) 95.894
+ Slack (MET) 2.493
====================================================================================================
====================================================================================================
-Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-Endpoint : ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CE
-Path Group : clk_10m
+Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK
+Endpoint : u_zoom_image/mult_image_g0_0/N2/gopapm/X[1]
+Path Group : clk_1080p60Hz
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.437
- Launch Clock Delay : 3.737
- Clock Pessimism Removal : 0.285
+Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.520
+ Launch Clock Delay : 5.994
+ Clock Pessimism Removal : 0.332
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.614 2.812 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.925 3.737 ntclkbufg_3
- CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
-
- CLMS_242_113/Q3 tco 0.220 3.957 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q
- net (fanout=3) 0.274 4.231 ms72xx_ctl/ms7200_ctl/dri_cnt [4]
- CLMS_246_113/Y2 td 0.381 4.612 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z
- net (fanout=1) 0.069 4.681 ms72xx_ctl/ms7200_ctl/_N95853
- CLMS_246_113/Y0 td 0.150 4.831 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z
- net (fanout=6) 0.271 5.102 ms72xx_ctl/ms7200_ctl/_N95857
- CLMS_242_117/Y1 td 0.244 5.346 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z
- net (fanout=15) 0.506 5.852 ms72xx_ctl/ms7200_ctl/N261
- CLMA_226_104/Y1 td 0.151 6.003 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z
- net (fanout=4) 0.309 6.312 ms72xx_ctl/ms7200_ctl/N2093 [4]
- CLMA_230_121/Y3 td 0.360 6.672 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z
- net (fanout=12) 0.302 6.974 ms72xx_ctl/ms7200_ctl/N1955
- CLMA_242_116/CECO td 0.141 7.115 r ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CEOUT
- net (fanout=4) 0.000 7.115 ntR1773
- CLMA_242_120/CECI r ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CE
-
- Data arrival time 7.115 Logic Levels: 6
- Logic: 1.647ns(48.757%), Route: 1.731ns(51.243%)
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.037 5.994 ntclkbufg_3
+ APM_206_264/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK
+
+ APM_206_264/P[8] tco 0.822 6.816 f u_zoom_image/mult_fra0_0/N2/gopapm/P[8]
+ net (fanout=3) 1.373 8.189 u_zoom_image/coe_mult_p0_0 [8]
+ APM_206_128/X[1] f u_zoom_image/mult_image_g0_0/N2/gopapm/X[1]
+
+ Data arrival time 8.189 Logic Levels: 0
+ Logic: 0.822ns(37.449%), Route: 1.373ns(62.551%)
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 100.000 100.000 r
- P20 0.000 100.000 r clk (port)
- net (fanout=1) 0.074 100.074 clk
- IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 101.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 101.860 _N69
- PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.603 102.542 clk_10m
- USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.895 103.437 ntclkbufg_3
- CLMA_242_120/CLK r ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CLK
- clock pessimism 0.285 103.722
- clock uncertainty -0.150 103.572
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.095 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 8.596 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 9.277 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 10.368 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 11.361 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.895 12.256 ntclkbufg_3
+ APM_206_128/CLK r u_zoom_image/mult_image_g0_0/N2/gopapm/CLK
+ clock pessimism 0.332 12.588
+ clock uncertainty -0.150 12.438
- Setup time -0.563 103.009
+ Setup time -1.731 10.707
- Data required time 103.009
+ Data required time 10.707
----------------------------------------------------------------------------------------------------
- Data required time 103.009
- Data arrival time 7.115
+ Data required time 10.707
+ Data arrival time 8.189
----------------------------------------------------------------------------------------------------
- Slack (MET) 95.894
+ Slack (MET) 2.518
====================================================================================================
====================================================================================================
-Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK
-Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9]
-Path Group : clk_10m
+Startpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK
+Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7]
+Path Group : clk_1080p60Hz
Path Type : min (fast corner)
Path Class : sequential timing path
Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.737
- Launch Clock Delay : 3.437
- Clock Pessimism Removal : -0.281
+ Capture Clock Delay : 5.882
+ Launch Clock Delay : 5.520
+ Clock Pessimism Removal : -0.343
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.603 2.542 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.895 3.437 ntclkbufg_3
- CLMA_230_117/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 3.632 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 4.625 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.895 5.520 ntclkbufg_3
+ CLMA_146_76/CLK r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK
- CLMA_230_117/Q0 tco 0.182 3.619 r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q0
- net (fanout=3) 0.196 3.815 ms72xx_ctl/ms7200_ctl/cmd_index [4]
- DRM_234_108/ADA0[9] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9]
+ CLMA_146_76/Q2 tco 0.183 5.703 r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Q0
+ net (fanout=3) 0.162 5.865 u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/wr_addr [2]
+ DRM_142_68/ADA0[7] r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7]
- Data arrival time 3.815 Logic Levels: 0
- Logic: 0.182ns(48.148%), Route: 0.196ns(51.852%)
+ Data arrival time 5.865 Logic Levels: 0
+ Logic: 0.183ns(53.043%), Route: 0.162ns(46.957%)
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.614 2.812 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.925 3.737 ntclkbufg_3
- DRM_234_108/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
- clock pessimism -0.281 3.456
- clock uncertainty 0.000 3.456
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.925 5.882 ntclkbufg_3
+ DRM_142_68/CLKA[0] r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA
+ clock pessimism -0.343 5.539
+ clock uncertainty 0.000 5.539
- Hold time 0.127 3.583
+ Hold time 0.166 5.705
- Data required time 3.583
+ Data required time 5.705
----------------------------------------------------------------------------------------------------
- Data required time 3.583
- Data arrival time 3.815
+ Data required time 5.705
+ Data arrival time 5.865
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.232
+ Slack (MET) 0.160
====================================================================================================
====================================================================================================
-Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK
-Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[8]
-Path Group : clk_10m
+Startpoint : u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK
+Endpoint : u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5]
+Path Group : clk_1080p60Hz
Path Type : min (fast corner)
Path Class : sequential timing path
Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.737
- Launch Clock Delay : 3.437
- Clock Pessimism Removal : -0.281
+ Capture Clock Delay : 5.882
+ Launch Clock Delay : 5.520
+ Clock Pessimism Removal : -0.343
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.603 2.542 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.895 3.437 ntclkbufg_3
- CLMA_230_113/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 3.632 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 4.625 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.895 5.520 ntclkbufg_3
+ CLMS_174_177/CLK r u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK
- CLMA_230_113/Q3 tco 0.182 3.619 r ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/Q1
- net (fanout=3) 0.199 3.818 ms72xx_ctl/ms7200_ctl/cmd_index [3]
- DRM_234_108/ADA0[8] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[8]
+ CLMS_174_177/Q1 tco 0.184 5.704 r u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/Q1
+ net (fanout=6) 0.144 5.848 u_zoom_image/wr_addr1 [2]
+ DRM_178_168/ADA0[5] r u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5]
- Data arrival time 3.818 Logic Levels: 0
- Logic: 0.182ns(47.769%), Route: 0.199ns(52.231%)
+ Data arrival time 5.848 Logic Levels: 0
+ Logic: 0.184ns(56.098%), Route: 0.144ns(43.902%)
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.614 2.812 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.925 3.737 ntclkbufg_3
- DRM_234_108/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
- clock pessimism -0.281 3.456
- clock uncertainty 0.000 3.456
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.925 5.882 ntclkbufg_3
+ DRM_178_168/CLKA[0] r u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism -0.343 5.539
+ clock uncertainty 0.000 5.539
- Hold time 0.127 3.583
+ Hold time 0.127 5.666
- Data required time 3.583
+ Data required time 5.666
----------------------------------------------------------------------------------------------------
- Data required time 3.583
- Data arrival time 3.818
+ Data required time 5.666
+ Data arrival time 5.848
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.235
+ Slack (MET) 0.182
====================================================================================================
====================================================================================================
-Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK
-Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12]
-Path Group : clk_10m
+Startpoint : u_zoom_image/image_valid[2][1]/opit_0/CLK
+Endpoint : u_zoom_image/image_valid[3][1]/opit_0/D
+Path Group : clk_1080p60Hz
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.737
- Launch Clock Delay : 3.437
- Clock Pessimism Removal : -0.281
+Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.882
+ Launch Clock Delay : 5.520
+ Clock Pessimism Removal : -0.361
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.603 2.542 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.895 3.437 ntclkbufg_3
- CLMA_230_117/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK
-
- CLMA_230_117/Q3 tco 0.182 3.619 r ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/Q1
- net (fanout=3) 0.201 3.820 ms72xx_ctl/ms7200_ctl/cmd_index [7]
- DRM_234_108/ADA0[12] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12]
-
- Data arrival time 3.820 Logic Levels: 0
- Logic: 0.182ns(47.520%), Route: 0.201ns(52.480%)
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 3.632 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 4.625 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.895 5.520 ntclkbufg_3
+ CLMA_210_153/CLK r u_zoom_image/image_valid[2][1]/opit_0/CLK
+
+ CLMA_210_153/Q3 tco 0.178 5.698 f u_zoom_image/image_valid[2][1]/opit_0/Q
+ net (fanout=1) 0.058 5.756 u_zoom_image/image_valid[2] [1]
+ CLMA_210_153/AD f u_zoom_image/image_valid[3][1]/opit_0/D
+
+ Data arrival time 5.756 Logic Levels: 0
+ Logic: 0.178ns(75.424%), Route: 0.058ns(24.576%)
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.614 2.812 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.925 3.737 ntclkbufg_3
- DRM_234_108/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
- clock pessimism -0.281 3.456
- clock uncertainty 0.000 3.456
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.925 5.882 ntclkbufg_3
+ CLMA_210_153/CLK r u_zoom_image/image_valid[3][1]/opit_0/CLK
+ clock pessimism -0.361 5.521
+ clock uncertainty 0.000 5.521
- Hold time 0.127 3.583
+ Hold time 0.040 5.561
- Data required time 3.583
+ Data required time 5.561
----------------------------------------------------------------------------------------------------
- Data required time 3.583
- Data arrival time 3.820
+ Data required time 5.561
+ Data arrival time 5.756
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.237
+ Slack (MET) 0.195
====================================================================================================
====================================================================================================
-Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE
+Startpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin
Path Group : clk_720p60Hz
Path Type : max (fast corner)
Path Class : sequential timing path
Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.516
- Launch Clock Delay : 5.878
- Clock Pessimism Removal : 0.343
+ Capture Clock Delay : 5.626
+ Launch Clock Delay : 5.990
+ Clock Pessimism Removal : 0.345
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -10887,37 +12143,35 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.925 5.878 ntclkbufg_2
- CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-
- CLMS_186_117/Q2 tco 0.223 6.101 f u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0
- net (fanout=1) 0.530 6.631 pos_y[7]
- CLMA_186_116/COUT td 0.397 7.028 r udp_osd_inst/N29.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 7.028 udp_osd_inst/N29.co [6]
- CLMA_186_120/Y1 td 0.383 7.411 r udp_osd_inst/N29.eq_4/gateop_A2/Y1
- net (fanout=5) 0.247 7.658 udp_osd_inst/N29
- CLMA_190_120/Y3 td 0.222 7.880 f udp_osd_inst/N69_5/gateop_perm/Z
- net (fanout=2) 0.356 8.236 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64
- CLMA_186_112/Y1 td 0.151 8.387 f udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z
- net (fanout=2) 0.255 8.642 udp_osd_inst/char_osd_inst/row_pixels_ready
- CLMA_186_108/Y2 td 0.150 8.792 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z
- net (fanout=6) 0.399 9.191 udp_osd_inst/char_osd_inst/char_next
- CLMA_182_88/Y3 td 0.162 9.353 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z
- net (fanout=1) 0.148 9.501 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79
- CLMA_182_88/Y2 td 0.150 9.651 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z
- net (fanout=3) 0.352 10.003 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518
- CLMA_186_80/Y0 td 0.264 10.267 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z
- net (fanout=1) 0.359 10.626 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786
- CLMA_182_73/CECO td 0.132 10.758 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT
- net (fanout=4) 0.000 10.758 ntR2038
- CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE
-
- Data arrival time 10.758 Logic Levels: 9
- Logic: 2.234ns(45.779%), Route: 2.646ns(54.221%)
+ net (fanout=1635) 1.037 5.990 ntclkbufg_2
+ CLMA_214_292/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK
+
+ CLMA_214_292/Q1 tco 0.223 6.213 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/Q1
+ net (fanout=3) 0.352 6.565 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt [5]
+ CLMA_218_284/Y1 td 0.244 6.809 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_20/gateop_perm/Z
+ net (fanout=1) 0.467 7.276 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107752
+ CLMA_214_280/Y1 td 0.360 7.636 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_29/gateop_perm/Z
+ net (fanout=3) 0.169 7.805 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N98274
+ CLMA_214_284/Y1 td 0.151 7.956 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_7/gateop_perm/Z
+ net (fanout=15) 0.628 8.584 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en
+ td 0.365 8.949 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q1/Cout
+ net (fanout=1) 0.000 8.949 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13665
+ CLMS_186_277/COUT td 0.044 8.993 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout
+ net (fanout=1) 0.000 8.993 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13667
+ CLMS_186_281/Y1 td 0.383 9.376 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1
+ net (fanout=3) 0.282 9.658 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N84 [5]
+ CLMA_186_292/Y2 td 0.379 10.037 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm/Z
+ net (fanout=1) 0.396 10.433 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rrptr [5]
+ CLMS_190_285/COUT td 0.394 10.827 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.eq_2/gateop_A2/Cout
+ net (fanout=1) 0.000 10.827 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.co [6]
+ CLMS_190_289/CIN r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin
+
+ Data arrival time 10.827 Logic Levels: 7
+ Logic: 2.543ns(52.574%), Route: 2.294ns(47.426%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 13.473 13.473 r
@@ -10930,36 +12184,36 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 16.014 rd3_clk
USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 17.105 ntR3907
+ net (fanout=1) 1.091 17.105 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 18.094 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.895 18.989 ntclkbufg_2
- CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK
- clock pessimism 0.343 19.332
- clock uncertainty -0.150 19.182
+ net (fanout=1635) 1.005 19.099 ntclkbufg_2
+ CLMS_190_289/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK
+ clock pessimism 0.345 19.444
+ clock uncertainty -0.150 19.294
- Setup time -0.576 18.606
+ Setup time -0.276 19.018
- Data required time 18.606
+ Data required time 19.018
----------------------------------------------------------------------------------------------------
- Data required time 18.606
- Data arrival time 10.758
+ Data required time 19.018
+ Data arrival time 10.827
----------------------------------------------------------------------------------------------------
- Slack (MET) 7.848
+ Slack (MET) 8.191
====================================================================================================
====================================================================================================
Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE
+Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE
Path Group : clk_720p60Hz
Path Type : max (fast corner)
Path Class : sequential timing path
Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.516
- Launch Clock Delay : 5.878
- Clock Pessimism Removal : 0.343
+ Capture Clock Delay : 5.626
+ Launch Clock Delay : 5.990
+ Clock Pessimism Removal : 0.345
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -10974,37 +12228,37 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.925 5.878 ntclkbufg_2
- CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-
- CLMS_186_117/Q2 tco 0.223 6.101 f u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0
- net (fanout=1) 0.530 6.631 pos_y[7]
- CLMA_186_116/COUT td 0.397 7.028 r udp_osd_inst/N29.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 7.028 udp_osd_inst/N29.co [6]
- CLMA_186_120/Y1 td 0.383 7.411 r udp_osd_inst/N29.eq_4/gateop_A2/Y1
- net (fanout=5) 0.247 7.658 udp_osd_inst/N29
- CLMA_190_120/Y3 td 0.222 7.880 f udp_osd_inst/N69_5/gateop_perm/Z
- net (fanout=2) 0.356 8.236 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64
- CLMA_186_112/Y1 td 0.151 8.387 f udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z
- net (fanout=2) 0.255 8.642 udp_osd_inst/char_osd_inst/row_pixels_ready
- CLMA_186_108/Y2 td 0.150 8.792 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z
- net (fanout=6) 0.399 9.191 udp_osd_inst/char_osd_inst/char_next
- CLMA_182_88/Y3 td 0.162 9.353 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z
- net (fanout=1) 0.148 9.501 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79
- CLMA_182_88/Y2 td 0.150 9.651 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z
- net (fanout=3) 0.352 10.003 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518
- CLMA_186_80/Y0 td 0.264 10.267 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z
- net (fanout=1) 0.359 10.626 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786
- CLMA_182_73/CECO td 0.132 10.758 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT
- net (fanout=4) 0.000 10.758 ntR2038
- CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE
-
- Data arrival time 10.758 Logic Levels: 9
- Logic: 2.234ns(45.779%), Route: 2.646ns(54.221%)
+ net (fanout=1635) 1.037 5.990 ntclkbufg_2
+ CLMA_246_256/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
+
+ CLMA_246_256/Q2 tco 0.223 6.213 f u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0
+ net (fanout=1) 0.460 6.673 pos_y[7]
+ CLMS_242_257/COUT td 0.397 7.070 r udp_osd_inst/N29.eq_2/gateop_A2/Cout
+ net (fanout=1) 0.000 7.070 udp_osd_inst/N29.co [6]
+ CLMS_242_261/Y1 td 0.383 7.453 r udp_osd_inst/N29.eq_4/gateop_A2/Y1
+ net (fanout=5) 0.285 7.738 udp_osd_inst/N29
+ CLMA_250_257/Y2 td 0.227 7.965 f udp_osd_inst/N69_5/gateop_perm/Z
+ net (fanout=2) 0.156 8.121 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64
+ CLMA_250_257/Y3 td 0.151 8.272 f udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z
+ net (fanout=2) 0.253 8.525 udp_osd_inst/char_osd_inst/row_pixels_ready
+ CLMA_250_261/Y1 td 0.151 8.676 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z
+ net (fanout=12) 0.417 9.093 udp_osd_inst/char_osd_inst/char_next
+ CLMA_246_284/Y2 td 0.162 9.255 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z
+ net (fanout=1) 0.148 9.403 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74
+ CLMA_246_284/Y1 td 0.151 9.554 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z
+ net (fanout=3) 0.255 9.809 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126
+ CLMA_250_284/Y0 td 0.150 9.959 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z
+ net (fanout=1) 0.249 10.208 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786
+ CLMA_254_288/CECO td 0.132 10.340 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT
+ net (fanout=4) 0.000 10.340 ntR2066
+ CLMA_254_292/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE
+
+ Data arrival time 10.340 Logic Levels: 9
+ Logic: 2.127ns(48.897%), Route: 2.223ns(51.103%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 13.473 13.473 r
@@ -11017,36 +12271,36 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 16.014 rd3_clk
USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 17.105 ntR3907
+ net (fanout=1) 1.091 17.105 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 18.094 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.895 18.989 ntclkbufg_2
- CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK
- clock pessimism 0.343 19.332
- clock uncertainty -0.150 19.182
+ net (fanout=1635) 1.005 19.099 ntclkbufg_2
+ CLMA_254_292/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK
+ clock pessimism 0.345 19.444
+ clock uncertainty -0.150 19.294
- Setup time -0.576 18.606
+ Setup time -0.576 18.718
- Data required time 18.606
+ Data required time 18.718
----------------------------------------------------------------------------------------------------
- Data required time 18.606
- Data arrival time 10.758
+ Data required time 18.718
+ Data arrival time 10.340
----------------------------------------------------------------------------------------------------
- Slack (MET) 7.848
+ Slack (MET) 8.378
====================================================================================================
====================================================================================================
Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE
+Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE
Path Group : clk_720p60Hz
Path Type : max (fast corner)
Path Class : sequential timing path
Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.516
- Launch Clock Delay : 5.878
- Clock Pessimism Removal : 0.343
+ Capture Clock Delay : 5.626
+ Launch Clock Delay : 5.990
+ Clock Pessimism Removal : 0.345
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11061,37 +12315,37 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.925 5.878 ntclkbufg_2
- CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
-
- CLMS_186_117/Q2 tco 0.223 6.101 f u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0
- net (fanout=1) 0.530 6.631 pos_y[7]
- CLMA_186_116/COUT td 0.397 7.028 r udp_osd_inst/N29.eq_2/gateop_A2/Cout
- net (fanout=1) 0.000 7.028 udp_osd_inst/N29.co [6]
- CLMA_186_120/Y1 td 0.383 7.411 r udp_osd_inst/N29.eq_4/gateop_A2/Y1
- net (fanout=5) 0.247 7.658 udp_osd_inst/N29
- CLMA_190_120/Y3 td 0.222 7.880 f udp_osd_inst/N69_5/gateop_perm/Z
- net (fanout=2) 0.356 8.236 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64
- CLMA_186_112/Y1 td 0.151 8.387 f udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z
- net (fanout=2) 0.255 8.642 udp_osd_inst/char_osd_inst/row_pixels_ready
- CLMA_186_108/Y2 td 0.150 8.792 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z
- net (fanout=6) 0.399 9.191 udp_osd_inst/char_osd_inst/char_next
- CLMA_182_88/Y3 td 0.162 9.353 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z
- net (fanout=1) 0.148 9.501 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79
- CLMA_182_88/Y2 td 0.150 9.651 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z
- net (fanout=3) 0.352 10.003 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518
- CLMA_186_80/Y0 td 0.264 10.267 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z
- net (fanout=1) 0.359 10.626 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786
- CLMA_182_73/CECO td 0.132 10.758 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT
- net (fanout=4) 0.000 10.758 ntR2038
- CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE
-
- Data arrival time 10.758 Logic Levels: 9
- Logic: 2.234ns(45.779%), Route: 2.646ns(54.221%)
+ net (fanout=1635) 1.037 5.990 ntclkbufg_2
+ CLMA_246_256/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
+
+ CLMA_246_256/Q2 tco 0.223 6.213 f u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0
+ net (fanout=1) 0.460 6.673 pos_y[7]
+ CLMS_242_257/COUT td 0.397 7.070 r udp_osd_inst/N29.eq_2/gateop_A2/Cout
+ net (fanout=1) 0.000 7.070 udp_osd_inst/N29.co [6]
+ CLMS_242_261/Y1 td 0.383 7.453 r udp_osd_inst/N29.eq_4/gateop_A2/Y1
+ net (fanout=5) 0.285 7.738 udp_osd_inst/N29
+ CLMA_250_257/Y2 td 0.227 7.965 f udp_osd_inst/N69_5/gateop_perm/Z
+ net (fanout=2) 0.156 8.121 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64
+ CLMA_250_257/Y3 td 0.151 8.272 f udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z
+ net (fanout=2) 0.253 8.525 udp_osd_inst/char_osd_inst/row_pixels_ready
+ CLMA_250_261/Y1 td 0.151 8.676 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z
+ net (fanout=12) 0.417 9.093 udp_osd_inst/char_osd_inst/char_next
+ CLMA_246_284/Y2 td 0.162 9.255 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z
+ net (fanout=1) 0.148 9.403 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74
+ CLMA_246_284/Y1 td 0.151 9.554 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z
+ net (fanout=3) 0.255 9.809 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126
+ CLMA_250_284/Y0 td 0.150 9.959 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z
+ net (fanout=1) 0.249 10.208 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786
+ CLMA_254_288/CECO td 0.132 10.340 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT
+ net (fanout=4) 0.000 10.340 ntR2066
+ CLMA_254_292/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE
+
+ Data arrival time 10.340 Logic Levels: 9
+ Logic: 2.127ns(48.897%), Route: 2.223ns(51.103%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 13.473 13.473 r
@@ -11104,29 +12358,29 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 16.014 rd3_clk
USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 17.105 ntR3907
+ net (fanout=1) 1.091 17.105 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 18.094 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.895 18.989 ntclkbufg_2
- CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CLK
- clock pessimism 0.343 19.332
- clock uncertainty -0.150 19.182
+ net (fanout=1635) 1.005 19.099 ntclkbufg_2
+ CLMA_254_292/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK
+ clock pessimism 0.345 19.444
+ clock uncertainty -0.150 19.294
- Setup time -0.576 18.606
+ Setup time -0.576 18.718
- Data required time 18.606
+ Data required time 18.718
----------------------------------------------------------------------------------------------------
- Data required time 18.606
- Data arrival time 10.758
+ Data required time 18.718
+ Data arrival time 10.340
----------------------------------------------------------------------------------------------------
- Slack (MET) 7.848
+ Slack (MET) 8.378
====================================================================================================
====================================================================================================
-Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK
-Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4
+Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK
+Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4
Path Group : clk_720p60Hz
Path Type : min (fast corner)
Path Class : sequential timing path
@@ -11148,16 +12402,16 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 2.541 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 3.632 ntR3907
+ net (fanout=1) 1.091 3.632 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 4.621 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT
net (fanout=1635) 0.895 5.516 ntclkbufg_2
- CLMA_266_132/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK
+ CLMA_250_177/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK
- CLMA_266_132/Q1 tco 0.180 5.696 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/Q
- net (fanout=1) 0.058 5.754 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[4] [1]
- CLMS_266_133/C4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4
+ CLMA_250_177/Q2 tco 0.180 5.696 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/Q
+ net (fanout=1) 0.058 5.754 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/dividend_t[13] [9]
+ CLMA_250_176/A4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4
Data arrival time 5.754 Logic Levels: 0
Logic: 0.180ns(75.630%), Route: 0.058ns(24.370%)
@@ -11173,36 +12427,36 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
net (fanout=1635) 0.925 5.878 ntclkbufg_2
- CLMS_266_133/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/CLK
+ CLMA_250_176/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK
clock pessimism -0.347 5.531
clock uncertainty 0.000 5.531
- Hold time -0.028 5.503
+ Hold time -0.029 5.502
- Data required time 5.503
+ Data required time 5.502
----------------------------------------------------------------------------------------------------
- Data required time 5.503
+ Data required time 5.502
Data arrival time 5.754
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.251
+ Slack (MET) 0.252
====================================================================================================
====================================================================================================
-Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK
-Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4
+Startpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK
+Endpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04
Path Group : clk_720p60Hz
Path Type : min (fast corner)
Path Class : sequential timing path
Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.878
- Launch Clock Delay : 5.516
- Clock Pessimism Removal : -0.347
+ Capture Clock Delay : 5.990
+ Launch Clock Delay : 5.626
+ Clock Pessimism Removal : -0.349
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11217,19 +12471,19 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 2.541 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 3.632 ntR3907
+ net (fanout=1) 1.091 3.632 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 4.621 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.895 5.516 ntclkbufg_2
- CLMA_262_132/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK
+ net (fanout=1635) 1.005 5.626 ntclkbufg_2
+ CLMA_230_280/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK
- CLMA_262_132/Q2 tco 0.180 5.696 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/Q
- net (fanout=1) 0.058 5.754 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[1] [3]
- CLMS_262_133/A4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4
+ CLMA_230_280/Q1 tco 0.180 5.806 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1
+ net (fanout=2) 0.059 5.865 udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3]
+ CLMA_230_281/C4 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04
- Data arrival time 5.754 Logic Levels: 0
- Logic: 0.180ns(75.630%), Route: 0.058ns(24.370%)
+ Data arrival time 5.865 Logic Levels: 0
+ Logic: 0.180ns(75.314%), Route: 0.059ns(24.686%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 0.000 0.000 r
@@ -11242,36 +12496,36 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.925 5.878 ntclkbufg_2
- CLMS_262_133/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/CLK
- clock pessimism -0.347 5.531
- clock uncertainty 0.000 5.531
+ net (fanout=1635) 1.037 5.990 ntclkbufg_2
+ CLMA_230_281/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK
+ clock pessimism -0.349 5.641
+ clock uncertainty 0.000 5.641
- Hold time -0.029 5.502
+ Hold time -0.028 5.613
- Data required time 5.502
+ Data required time 5.613
----------------------------------------------------------------------------------------------------
- Data required time 5.502
- Data arrival time 5.754
+ Data required time 5.613
+ Data arrival time 5.865
----------------------------------------------------------------------------------------------------
Slack (MET) 0.252
====================================================================================================
====================================================================================================
-Startpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK
-Endpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04
+Startpoint : u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK
+Endpoint : u_sync_vg/pos_y[4]/opit_0_A2Q21/I04
Path Group : clk_720p60Hz
Path Type : min (fast corner)
Path Class : sequential timing path
Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.878
- Launch Clock Delay : 5.516
- Clock Pessimism Removal : -0.347
+ Capture Clock Delay : 5.990
+ Launch Clock Delay : 5.626
+ Clock Pessimism Removal : -0.349
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11286,19 +12540,19 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 2.541 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 3.632 ntR3907
+ net (fanout=1) 1.091 3.632 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 4.621 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.895 5.516 ntclkbufg_2
- CLMA_174_52/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK
+ net (fanout=1635) 1.005 5.626 ntclkbufg_2
+ CLMS_246_253/CLK r u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK
- CLMA_174_52/Q1 tco 0.180 5.696 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1
- net (fanout=2) 0.059 5.755 udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3]
- CLMS_174_53/C4 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04
+ CLMS_246_253/Q1 tco 0.180 5.806 f u_sync_vg/v_count[3]/opit_0_L5Q_perm/Q
+ net (fanout=7) 0.064 5.870 u_sync_vg/v_count [3]
+ CLMA_246_252/C4 f u_sync_vg/pos_y[4]/opit_0_A2Q21/I04
- Data arrival time 5.755 Logic Levels: 0
- Logic: 0.180ns(75.314%), Route: 0.059ns(24.686%)
+ Data arrival time 5.870 Logic Levels: 0
+ Logic: 0.180ns(73.770%), Route: 0.064ns(26.230%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 0.000 0.000 r
@@ -11311,36 +12565,36 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.925 5.878 ntclkbufg_2
- CLMS_174_53/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK
- clock pessimism -0.347 5.531
- clock uncertainty 0.000 5.531
+ net (fanout=1635) 1.037 5.990 ntclkbufg_2
+ CLMA_246_252/CLK r u_sync_vg/pos_y[4]/opit_0_A2Q21/CLK
+ clock pessimism -0.349 5.641
+ clock uncertainty 0.000 5.641
- Hold time -0.028 5.503
+ Hold time -0.028 5.613
- Data required time 5.503
+ Data required time 5.613
----------------------------------------------------------------------------------------------------
- Data required time 5.503
- Data arrival time 5.755
+ Data required time 5.613
+ Data arrival time 5.870
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.252
+ Slack (MET) 0.257
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
-Endpoint : u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
+Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
+Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
Path Group : clk_20k
Path Type : max (fast corner)
Path Class : sequential timing path
Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.644
- Launch Clock Delay : 6.109
- Clock Pessimism Removal : 0.446
+ Capture Clock Delay : 5.862
+ Launch Clock Delay : 6.370
+ Clock Pessimism Removal : 0.489
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11354,26 +12608,26 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.219 5.184 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 5.184 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.925 6.109 u_ov5640/coms2_reg_config/clock_20k
- DRM_178_24/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
-
- DRM_178_24/QB0[5] tco 1.780 7.889 f u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5]
- net (fanout=1) 0.327 8.216 u_ov5640/coms2_reg_config/i2c_data [21]
- CLMA_174_32/Y3 td 0.358 8.574 f u_ov5640/coms2_reg_config/u1/N267_29/gateop/F
- net (fanout=1) 0.250 8.824 u_ov5640/coms2_reg_config/u1/_N25904
- CLMS_174_29/Y2 td 0.162 8.986 r u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z
- net (fanout=1) 0.152 9.138 u_ov5640/coms2_reg_config/u1/_N25910
- CLMS_174_29/Y1 td 0.212 9.350 f u_ov5640/coms2_reg_config/u1/N267_36/gateop/F
- net (fanout=1) 0.167 9.517 u_ov5640/coms2_reg_config/u1/_N25911
- CLMS_174_25/DD f u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
-
- Data arrival time 9.517 Logic Levels: 3
- Logic: 2.512ns(73.709%), Route: 0.896ns(26.291%)
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.480 5.445 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 5.445 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.925 6.370 u_ov5640/coms1_reg_config/clock_20k
+ DRM_142_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
+
+ DRM_142_4/QB0[6] tco 1.780 8.150 f u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6]
+ net (fanout=1) 0.343 8.493 u_ov5640/coms1_reg_config/i2c_data [22]
+ CLMA_146_12/Y1 td 0.359 8.852 f u_ov5640/coms1_reg_config/u1/N267_29/gateop/F
+ net (fanout=1) 0.369 9.221 u_ov5640/coms1_reg_config/u1/_N25311
+ CLMA_138_16/Y0 td 0.162 9.383 r u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z
+ net (fanout=1) 0.151 9.534 u_ov5640/coms1_reg_config/u1/_N25317
+ CLMA_138_16/Y2 td 0.233 9.767 f u_ov5640/coms1_reg_config/u1/N267_36/gateop/F
+ net (fanout=1) 0.272 10.039 u_ov5640/coms1_reg_config/u1/_N25318
+ CLMA_138_9/AD f u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
+
+ Data arrival time 10.039 Logic Levels: 3
+ Logic: 2.534ns(69.065%), Route: 1.135ns(30.935%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 50000.000 50000.000 r
@@ -11385,37 +12639,37 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.463 50001.860 _N69
PLL_158_55/CLK_OUT3 td 0.083 50001.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.603 50002.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 50003.441 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.184 50003.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.124 50004.749 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 50004.749 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.895 50005.644 u_ov5640/coms2_reg_config/clock_20k
- CLMS_174_25/CLK r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK
- clock pessimism 0.446 50006.090
- clock uncertainty -0.050 50006.040
+ USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 50003.441 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.184 50003.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.342 50004.967 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 50004.967 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.895 50005.862 u_ov5640/coms1_reg_config/clock_20k
+ CLMA_138_9/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK
+ clock pessimism 0.489 50006.351
+ clock uncertainty -0.050 50006.301
- Setup time -0.123 50005.917
+ Setup time -0.151 50006.150
- Data required time 50005.917
+ Data required time 50006.150
----------------------------------------------------------------------------------------------------
- Data required time 50005.917
- Data arrival time 9.517
+ Data required time 50006.150
+ Data arrival time 10.039
----------------------------------------------------------------------------------------------------
- Slack (MET) 49996.400
+ Slack (MET) 49996.111
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
-Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
+Startpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
+Endpoint : u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4
Path Group : clk_20k
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.784
- Launch Clock Delay : 6.274
- Clock Pessimism Removal : 0.471
+Clock Skew : -0.066 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.796
+ Launch Clock Delay : 6.335
+ Clock Pessimism Removal : 0.473
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11429,26 +12683,26 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.384 5.349 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 5.349 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.925 6.274 u_ov5640/coms1_reg_config/clock_20k
- DRM_178_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
-
- DRM_178_4/QB0[6] tco 1.780 8.054 f u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6]
- net (fanout=1) 0.400 8.454 u_ov5640/coms1_reg_config/i2c_data [22]
- CLMS_174_9/Y2 td 0.379 8.833 f u_ov5640/coms1_reg_config/u1/N267_29/gateop/F
- net (fanout=1) 0.069 8.902 u_ov5640/coms1_reg_config/u1/_N25461
- CLMA_174_8/Y0 td 0.162 9.064 r u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z
- net (fanout=1) 0.072 9.136 u_ov5640/coms1_reg_config/u1/_N25467
- CLMA_174_8/Y1 td 0.211 9.347 r u_ov5640/coms1_reg_config/u1/N267_36/gateop/F
- net (fanout=1) 0.268 9.615 u_ov5640/coms1_reg_config/u1/_N25468
- CLMA_174_16/DD r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
-
- Data arrival time 9.615 Logic Levels: 3
- Logic: 2.532ns(75.786%), Route: 0.809ns(24.214%)
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMA_122_12/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.398 5.363 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ USCM_84_121/CLK_USCM td 0.000 5.363 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.972 6.335 u_ov5640/coms2_reg_config/clock_20k
+ DRM_82_4/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
+
+ DRM_82_4/QB0[5] tco 1.780 8.115 f u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5]
+ net (fanout=1) 0.306 8.421 u_ov5640/coms2_reg_config/i2c_data [21]
+ CLMS_78_9/Y1 td 0.359 8.780 f u_ov5640/coms2_reg_config/u1/N267_29/gateop/F
+ net (fanout=1) 0.391 9.171 u_ov5640/coms2_reg_config/u1/_N25853
+ CLMA_90_12/Y2 td 0.162 9.333 r u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z
+ net (fanout=1) 0.151 9.484 u_ov5640/coms2_reg_config/u1/_N25859
+ CLMA_90_12/Y6AB td 0.200 9.684 r u_ov5640/coms2_reg_config/u1/N267_37_muxf6/F
+ net (fanout=1) 0.151 9.835 u_ov5640/coms2_reg_config/u1/N267
+ CLMA_90_13/A4 r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4
+
+ Data arrival time 9.835 Logic Levels: 3
+ Logic: 2.501ns(71.457%), Route: 0.999ns(28.543%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 50000.000 50000.000 r
@@ -11460,37 +12714,37 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.463 50001.860 _N69
PLL_158_55/CLK_OUT3 td 0.083 50001.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.603 50002.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 50003.441 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.184 50003.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.264 50004.889 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 50004.889 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.895 50005.784 u_ov5640/coms1_reg_config/clock_20k
- CLMA_174_16/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK
- clock pessimism 0.471 50006.255
- clock uncertainty -0.050 50006.205
+ USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 50003.441 ntclkbufg_8
+ CLMA_122_12/Q1 tco 0.184 50003.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.276 50004.901 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ USCM_84_121/CLK_USCM td 0.000 50004.901 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.895 50005.796 u_ov5640/coms2_reg_config/clock_20k
+ CLMA_90_13/CLK r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.473 50006.269
+ clock uncertainty -0.050 50006.219
- Setup time -0.127 50006.078
+ Setup time -0.093 50006.126
- Data required time 50006.078
+ Data required time 50006.126
----------------------------------------------------------------------------------------------------
- Data required time 50006.078
- Data arrival time 9.615
+ Data required time 50006.126
+ Data arrival time 9.835
----------------------------------------------------------------------------------------------------
- Slack (MET) 49996.463
+ Slack (MET) 49996.291
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
-Endpoint : u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3
+Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
+Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3
Path Group : clk_20k
Path Type : max (fast corner)
Path Class : sequential timing path
Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.644
- Launch Clock Delay : 6.109
- Clock Pessimism Removal : 0.446
+ Capture Clock Delay : 5.862
+ Launch Clock Delay : 6.370
+ Clock Pessimism Removal : 0.489
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11504,22 +12758,22 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.219 5.184 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 5.184 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.925 6.109 u_ov5640/coms2_reg_config/clock_20k
- DRM_178_24/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.480 5.445 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 5.445 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.925 6.370 u_ov5640/coms1_reg_config/clock_20k
+ DRM_142_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
- DRM_178_24/QB0[1] tco 1.780 7.889 f u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[1]
- net (fanout=1) 0.514 8.403 u_ov5640/coms2_reg_config/i2c_data [17]
- CLMA_182_33/Y1 td 0.469 8.872 f u_ov5640/coms2_reg_config/u1/N267_18_muxf7/F
- net (fanout=1) 0.469 9.341 u_ov5640/coms2_reg_config/u1/_N25893
- CLMS_174_25/D0 f u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3
+ DRM_142_4/QA0[9] tco 1.815 8.185 f u_ov5640/coms1_reg_config/reg_data/iGopDrm/QA0[9]
+ net (fanout=1) 0.410 8.595 u_ov5640/coms1_reg_config/i2c_data [8]
+ CLMA_146_8/Y1 td 0.469 9.064 f u_ov5640/coms1_reg_config/u1/N267_18_muxf7/F
+ net (fanout=1) 0.378 9.442 u_ov5640/coms1_reg_config/u1/_N25300
+ CLMA_138_9/A0 f u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3
- Data arrival time 9.341 Logic Levels: 1
- Logic: 2.249ns(69.585%), Route: 0.983ns(30.415%)
+ Data arrival time 9.442 Logic Levels: 1
+ Logic: 2.284ns(74.349%), Route: 0.788ns(25.651%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 50000.000 50000.000 r
@@ -11531,37 +12785,37 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
net (fanout=1) 0.463 50001.860 _N69
PLL_158_55/CLK_OUT3 td 0.083 50001.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.603 50002.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 50003.441 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.184 50003.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.124 50004.749 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 50004.749 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.895 50005.644 u_ov5640/coms2_reg_config/clock_20k
- CLMS_174_25/CLK r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK
- clock pessimism 0.446 50006.090
- clock uncertainty -0.050 50006.040
+ USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 50003.441 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.184 50003.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.342 50004.967 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 50004.967 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.895 50005.862 u_ov5640/coms1_reg_config/clock_20k
+ CLMA_138_9/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK
+ clock pessimism 0.489 50006.351
+ clock uncertainty -0.050 50006.301
- Setup time -0.148 50005.892
+ Setup time -0.154 50006.147
- Data required time 50005.892
+ Data required time 50006.147
----------------------------------------------------------------------------------------------------
- Data required time 50005.892
- Data arrival time 9.341
+ Data required time 50006.147
+ Data arrival time 9.442
----------------------------------------------------------------------------------------------------
- Slack (MET) 49996.551
+ Slack (MET) 49996.705
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5]
+Startpoint : u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5]
Path Group : clk_20k
Path Type : min (fast corner)
Path Class : sequential timing path
Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.109
- Launch Clock Delay : 5.644
- Clock Pessimism Removal : -0.446
+ Capture Clock Delay : 6.370
+ Launch Clock Delay : 5.862
+ Clock Pessimism Removal : -0.489
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11575,20 +12829,20 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.603 2.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 3.441 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.184 3.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.124 4.749 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 4.749 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.895 5.644 u_ov5640/coms2_reg_config/clock_20k
- CLMA_182_32/CLK r u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
+ USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 3.441 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.184 3.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.342 4.967 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 4.967 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.895 5.862 u_ov5640/coms1_reg_config/clock_20k
+ CLMA_146_12/CLK r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
- CLMA_182_32/Q0 tco 0.182 5.826 r u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q
- net (fanout=6) 0.233 6.059 u_ov5640/coms2_reg_config/reg_index [0]
- DRM_178_24/ADA0[5] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5]
+ CLMA_146_12/Q0 tco 0.182 6.044 r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q
+ net (fanout=6) 0.237 6.281 u_ov5640/coms1_reg_config/reg_index [0]
+ DRM_142_4/ADA0[5] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5]
- Data arrival time 6.059 Logic Levels: 0
- Logic: 0.182ns(43.855%), Route: 0.233ns(56.145%)
+ Data arrival time 6.281 Logic Levels: 0
+ Logic: 0.182ns(43.437%), Route: 0.237ns(56.563%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 0.000 0.000 r
@@ -11600,37 +12854,37 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_25/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.219 5.184 u_ov5640/coms2_reg_config/clk_20k_regdiv
- USCM_84_120/CLK_USCM td 0.000 5.184 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.925 6.109 u_ov5640/coms2_reg_config/clock_20k
- DRM_178_24/CLKA[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKA[0]
- clock pessimism -0.446 5.663
- clock uncertainty 0.000 5.663
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMS_122_9/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.480 5.445 u_ov5640/coms1_reg_config/clk_20k_regdiv
+ USCM_84_120/CLK_USCM td 0.000 5.445 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.925 6.370 u_ov5640/coms1_reg_config/clock_20k
+ DRM_142_4/CLKA[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
+ clock pessimism -0.489 5.881
+ clock uncertainty 0.000 5.881
- Hold time 0.127 5.790
+ Hold time 0.127 6.008
- Data required time 5.790
+ Data required time 6.008
----------------------------------------------------------------------------------------------------
- Data required time 5.790
- Data arrival time 6.059
+ Data required time 6.008
+ Data arrival time 6.281
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.269
+ Slack (MET) 0.273
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5]
+Startpoint : u_ov5640/coms2_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK
+Endpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADB0[8]
Path Group : clk_20k
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.274
- Launch Clock Delay : 5.784
- Clock Pessimism Removal : -0.471
+Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 6.335
+ Launch Clock Delay : 5.826
+ Clock Pessimism Removal : -0.473
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11644,20 +12898,20 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.603 2.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 3.441 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.184 3.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.264 4.889 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 4.889 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.895 5.784 u_ov5640/coms1_reg_config/clock_20k
- CLMA_182_13/CLK r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
+ USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 3.441 ntclkbufg_8
+ CLMA_122_12/Q1 tco 0.184 3.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.276 4.901 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ USCM_84_121/CLK_USCM td 0.000 4.901 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.925 5.826 u_ov5640/coms2_reg_config/clock_20k
+ CLMS_78_13/CLK r u_ov5640/coms2_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK
- CLMA_182_13/Q0 tco 0.182 5.966 r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q
- net (fanout=6) 0.235 6.201 u_ov5640/coms1_reg_config/reg_index [0]
- DRM_178_4/ADA0[5] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5]
+ CLMS_78_13/Q2 tco 0.183 6.009 r u_ov5640/coms2_reg_config/reg_index[4]/opit_0_inv_A2Q21/Q0
+ net (fanout=4) 0.199 6.208 u_ov5640/coms2_reg_config/reg_index [3]
+ DRM_82_4/ADB0[8] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADB0[8]
- Data arrival time 6.201 Logic Levels: 0
- Logic: 0.182ns(43.645%), Route: 0.235ns(56.355%)
+ Data arrival time 6.208 Logic Levels: 0
+ Logic: 0.183ns(47.906%), Route: 0.199ns(52.094%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 0.000 0.000 r
@@ -11669,37 +12923,37 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.384 5.349 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 5.349 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.925 6.274 u_ov5640/coms1_reg_config/clock_20k
- DRM_178_4/CLKA[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
- clock pessimism -0.471 5.803
- clock uncertainty 0.000 5.803
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMA_122_12/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.398 5.363 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ USCM_84_121/CLK_USCM td 0.000 5.363 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.972 6.335 u_ov5640/coms2_reg_config/clock_20k
+ DRM_82_4/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
+ clock pessimism -0.473 5.862
+ clock uncertainty 0.000 5.862
- Hold time 0.127 5.930
+ Hold time 0.061 5.923
- Data required time 5.930
+ Data required time 5.923
----------------------------------------------------------------------------------------------------
- Data required time 5.930
- Data arrival time 6.201
+ Data required time 5.923
+ Data arrival time 6.208
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.271
+ Slack (MET) 0.285
====================================================================================================
====================================================================================================
-Startpoint : u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK
-Endpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADB0[8]
+Startpoint : u_ov5640/coms2_reg_config/reg_index[8]/opit_0_inv_A2Q21/CLK
+Endpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA_CAS
Path Group : clk_20k
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.274
- Launch Clock Delay : 5.784
- Clock Pessimism Removal : -0.471
+Clock Skew : 0.028 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 6.331
+ Launch Clock Delay : 5.830
+ Clock Pessimism Removal : -0.473
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11713,20 +12967,20 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.603 2.546 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.895 3.441 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.184 3.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.264 4.889 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 4.889 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.895 5.784 u_ov5640/coms1_reg_config/clock_20k
- CLMS_174_13/CLK r u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK
+ USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.895 3.441 ntclkbufg_8
+ CLMA_122_12/Q1 tco 0.184 3.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.276 4.901 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ USCM_84_121/CLK_USCM td 0.000 4.901 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.929 5.830 u_ov5640/coms2_reg_config/clock_20k
+ CLMS_78_17/CLK r u_ov5640/coms2_reg_config/reg_index[8]/opit_0_inv_A2Q21/CLK
- CLMS_174_13/Q2 tco 0.183 5.967 r u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/Q0
- net (fanout=4) 0.197 6.164 u_ov5640/coms1_reg_config/reg_index [3]
- DRM_178_4/ADB0[8] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADB0[8]
+ CLMS_78_17/Q3 tco 0.182 6.012 r u_ov5640/coms2_reg_config/reg_index[8]/opit_0_inv_A2Q21/Q1
+ net (fanout=5) 0.204 6.216 u_ov5640/coms2_reg_config/reg_index [8]
+ DRM_82_4/ADA_CAS r u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA_CAS
- Data arrival time 6.164 Logic Levels: 0
- Logic: 0.183ns(48.158%), Route: 0.197ns(51.842%)
+ Data arrival time 6.216 Logic Levels: 0
+ Logic: 0.182ns(47.150%), Route: 0.204ns(52.850%)
----------------------------------------------------------------------------------------------------
Clock clk_20k (rising edge) 0.000 0.000 r
@@ -11738,37 +12992,37 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3
net (fanout=1) 0.614 2.816 clk_25m
- USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT
- net (fanout=26) 0.925 3.741 ntclkbufg_7
- CLMA_182_12/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q
- net (fanout=3) 1.384 5.349 u_ov5640/coms1_reg_config/clk_20k_regdiv
- USCM_84_119/CLK_USCM td 0.000 5.349 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
- net (fanout=19) 0.925 6.274 u_ov5640/coms1_reg_config/clock_20k
- DRM_178_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
- clock pessimism -0.471 5.803
- clock uncertainty 0.000 5.803
+ USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT
+ net (fanout=26) 0.925 3.741 ntclkbufg_8
+ CLMA_122_12/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q
+ net (fanout=3) 1.398 5.363 u_ov5640/coms2_reg_config/clk_20k_regdiv
+ USCM_84_121/CLK_USCM td 0.000 5.363 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT
+ net (fanout=19) 0.968 6.331 u_ov5640/coms2_reg_config/clock_20k
+ DRM_82_4/CLKA[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKA[0]
+ clock pessimism -0.473 5.858
+ clock uncertainty 0.000 5.858
- Hold time 0.061 5.864
+ Hold time 0.069 5.927
- Data required time 5.864
+ Data required time 5.927
----------------------------------------------------------------------------------------------------
- Data required time 5.864
- Data arrival time 6.164
+ Data required time 5.927
+ Data arrival time 6.216
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.300
+ Slack (MET) 0.289
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0
Path Group : ddrphy_clkin
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 6.654
Launch Clock Delay : 7.101
- Clock Pessimism Removal : 0.417
+ Clock Pessimism Removal : 0.428
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11781,41 +13035,41 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
-
- CLMA_22_124/Q3 tco 0.220 7.321 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q
- net (fanout=5) 0.657 7.978 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2]
- CLMA_30_168/Y3 td 0.358 8.336 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
- net (fanout=2) 0.260 8.596 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
- td 0.368 8.964 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 8.964 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
- CLMA_34_168/Y2 td 0.202 9.166 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0
- net (fanout=1) 0.360 9.526 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2]
- CLMA_30_160/Y3 td 0.151 9.677 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z
- net (fanout=4) 0.451 10.128 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2]
- CLMA_30_172/COUT td 0.387 10.515 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
- net (fanout=1) 0.000 10.515 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576
- CLMA_30_176/Y0 td 0.206 10.721 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
- net (fanout=4) 0.996 11.717 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
- CLMA_30_248/Y0 td 0.380 12.097 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z
- net (fanout=40) 0.617 12.714 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196
- CLMS_38_245/Y1 td 0.360 13.074 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[2]/gateop/F
- net (fanout=1) 0.315 13.389 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24359
- CLMS_22_245/D3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
-
- Data arrival time 13.389 Logic Levels: 7
- Logic: 2.632ns(41.858%), Route: 3.656ns(58.142%)
+ CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_10_133/Q2 tco 0.224 7.325 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q
+ net (fanout=5) 0.420 7.745 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2]
+ CLMS_18_149/Y1 td 0.224 7.969 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
+ net (fanout=2) 0.257 8.226 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
+ td 0.368 8.594 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
+ net (fanout=1) 0.000 8.594 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
+ CLMS_18_145/Y3 td 0.365 8.959 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1
+ net (fanout=1) 0.432 9.391 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3]
+ CLMS_46_145/Y1 td 0.244 9.635 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z
+ net (fanout=4) 0.261 9.896 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3]
+ CLMA_50_144/COUT td 0.391 10.287 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
+ net (fanout=1) 0.000 10.287 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534
+ CLMA_50_148/Y0 td 0.206 10.493 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
+ net (fanout=4) 0.169 10.662 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
+ CLMS_46_149/Y0 td 0.226 10.888 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z
+ net (fanout=40) 0.458 11.346 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975
+ CLMA_62_164/Y2 td 0.379 11.725 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[12]/gateop/F
+ net (fanout=1) 0.254 11.979 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24148
+ CLMA_58_161/C3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0
+
+ Data arrival time 11.979 Logic Levels: 7
+ Logic: 2.627ns(53.854%), Route: 2.251ns(46.146%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -11826,42 +13080,42 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 11.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 12.537 zoom_clk
+ net (fanout=2) 0.603 12.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 14.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 14.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.895 16.654 ntclkbufg_0
- CLMS_22_245/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK
- clock pessimism 0.417 17.071
- clock uncertainty -0.150 16.921
+ CLMA_58_161/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK
+ clock pessimism 0.428 17.082
+ clock uncertainty -0.150 16.932
- Setup time -0.287 16.634
+ Setup time -0.308 16.624
- Data required time 16.634
+ Data required time 16.624
----------------------------------------------------------------------------------------------------
- Data required time 16.634
- Data arrival time 13.389
+ Data required time 16.624
+ Data arrival time 11.979
----------------------------------------------------------------------------------------------------
- Slack (MET) 3.245
+ Slack (MET) 4.645
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
Path Group : ddrphy_clkin
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
Capture Clock Delay : 6.654
Launch Clock Delay : 7.101
- Clock Pessimism Removal : 0.417
+ Clock Pessimism Removal : 0.428
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11874,41 +13128,41 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
-
- CLMA_22_124/Q3 tco 0.220 7.321 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q
- net (fanout=5) 0.657 7.978 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2]
- CLMA_30_168/Y3 td 0.358 8.336 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
- net (fanout=2) 0.260 8.596 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
- td 0.368 8.964 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 8.964 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
- CLMA_34_168/Y2 td 0.202 9.166 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0
- net (fanout=1) 0.360 9.526 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2]
- CLMA_30_160/Y3 td 0.151 9.677 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z
- net (fanout=4) 0.451 10.128 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2]
- CLMA_30_172/COUT td 0.387 10.515 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
- net (fanout=1) 0.000 10.515 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576
- CLMA_30_176/Y0 td 0.206 10.721 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
- net (fanout=4) 0.996 11.717 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
- CLMA_30_248/Y0 td 0.380 12.097 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z
- net (fanout=40) 0.491 12.588 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196
- CLMA_30_248/Y1 td 0.360 12.948 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[0]/gateop/F
- net (fanout=1) 0.398 13.346 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24357
- CLMS_22_245/A3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0
-
- Data arrival time 13.346 Logic Levels: 7
- Logic: 2.632ns(42.146%), Route: 3.613ns(57.854%)
+ CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_10_133/Q2 tco 0.224 7.325 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q
+ net (fanout=5) 0.420 7.745 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2]
+ CLMS_18_149/Y1 td 0.224 7.969 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
+ net (fanout=2) 0.257 8.226 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
+ td 0.368 8.594 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
+ net (fanout=1) 0.000 8.594 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
+ CLMS_18_145/Y3 td 0.365 8.959 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1
+ net (fanout=1) 0.432 9.391 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3]
+ CLMS_46_145/Y1 td 0.244 9.635 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z
+ net (fanout=4) 0.261 9.896 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3]
+ CLMA_50_144/COUT td 0.391 10.287 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
+ net (fanout=1) 0.000 10.287 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534
+ CLMA_50_148/Y0 td 0.206 10.493 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
+ net (fanout=4) 0.169 10.662 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
+ CLMS_46_149/Y0 td 0.226 10.888 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z
+ net (fanout=40) 0.519 11.407 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975
+ CLMA_66_156/Y2 td 0.381 11.788 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[10]/gateop/F
+ net (fanout=1) 0.173 11.961 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24146
+ CLMA_66_152/B3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
+
+ Data arrival time 11.961 Logic Levels: 7
+ Logic: 2.629ns(54.095%), Route: 2.231ns(45.905%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -11919,42 +13173,42 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 11.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 12.537 zoom_clk
+ net (fanout=2) 0.603 12.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 14.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 14.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.895 16.654 ntclkbufg_0
- CLMS_22_245/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK
- clock pessimism 0.417 17.071
- clock uncertainty -0.150 16.921
+ CLMA_66_152/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK
+ clock pessimism 0.428 17.082
+ clock uncertainty -0.150 16.932
- Setup time -0.308 16.613
+ Setup time -0.287 16.645
- Data required time 16.613
+ Data required time 16.645
----------------------------------------------------------------------------------------------------
- Data required time 16.613
- Data arrival time 13.346
+ Data required time 16.645
+ Data arrival time 11.961
----------------------------------------------------------------------------------------------------
- Slack (MET) 3.267
+ Slack (MET) 4.684
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
Path Group : ddrphy_clkin
Path Type : max (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.764
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 6.654
Launch Clock Delay : 7.101
- Clock Pessimism Removal : 0.417
+ Clock Pessimism Removal : 0.428
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -11967,41 +13221,41 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
-
- CLMA_22_124/Q3 tco 0.220 7.321 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q
- net (fanout=5) 0.657 7.978 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2]
- CLMA_30_168/Y3 td 0.358 8.336 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
- net (fanout=2) 0.260 8.596 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
- td 0.368 8.964 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
- net (fanout=1) 0.000 8.964 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
- CLMA_34_168/Y2 td 0.202 9.166 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0
- net (fanout=1) 0.360 9.526 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2]
- CLMA_30_160/Y3 td 0.151 9.677 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z
- net (fanout=4) 0.451 10.128 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2]
- CLMA_30_172/COUT td 0.387 10.515 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
- net (fanout=1) 0.000 10.515 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576
- CLMA_30_176/Y0 td 0.206 10.721 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
- net (fanout=4) 0.996 11.717 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
- CLMA_30_248/Y0 td 0.380 12.097 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z
- net (fanout=40) 0.510 12.607 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196
- CLMA_34_268/Y3 td 0.360 12.967 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[10]/gateop/F
- net (fanout=1) 0.484 13.451 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24367
- CLMS_22_265/B3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
-
- Data arrival time 13.451 Logic Levels: 7
- Logic: 2.632ns(41.449%), Route: 3.718ns(58.551%)
+ CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+
+ CLMS_10_133/Q2 tco 0.224 7.325 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q
+ net (fanout=5) 0.420 7.745 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2]
+ CLMS_18_149/Y1 td 0.224 7.969 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z
+ net (fanout=2) 0.257 8.226 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1]
+ td 0.368 8.594 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout
+ net (fanout=1) 0.000 8.594 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2]
+ CLMS_18_145/Y3 td 0.365 8.959 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1
+ net (fanout=1) 0.432 9.391 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3]
+ CLMS_46_145/Y1 td 0.244 9.635 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z
+ net (fanout=4) 0.261 9.896 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3]
+ CLMA_50_144/COUT td 0.391 10.287 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout
+ net (fanout=1) 0.000 10.287 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534
+ CLMA_50_148/Y0 td 0.206 10.493 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y
+ net (fanout=4) 0.169 10.662 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4]
+ CLMS_46_149/Y0 td 0.226 10.888 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z
+ net (fanout=40) 0.539 11.427 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975
+ CLMA_62_160/Y1 td 0.244 11.671 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[14]/gateop/F
+ net (fanout=1) 0.259 11.930 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24150
+ CLMA_58_161/A3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
+
+ Data arrival time 11.930 Logic Levels: 7
+ Logic: 2.492ns(51.605%), Route: 2.337ns(48.395%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -12012,42 +13266,42 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 11.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 12.537 zoom_clk
+ net (fanout=2) 0.603 12.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 14.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 14.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.005 16.764 ntclkbufg_0
- CLMS_22_265/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK
- clock pessimism 0.417 17.181
- clock uncertainty -0.150 17.031
+ net (fanout=5464) 0.895 16.654 ntclkbufg_0
+ CLMA_58_161/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK
+ clock pessimism 0.428 17.082
+ clock uncertainty -0.150 16.932
- Setup time -0.287 16.744
+ Setup time -0.308 16.624
- Data required time 16.744
+ Data required time 16.624
----------------------------------------------------------------------------------------------------
- Data required time 16.744
- Data arrival time 13.451
+ Data required time 16.624
+ Data arrival time 11.930
----------------------------------------------------------------------------------------------------
- Slack (MET) 3.293
+ Slack (MET) 4.694
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0
Path Group : ddrphy_clkin
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 7.101
- Launch Clock Delay : 6.654
- Clock Pessimism Removal : -0.417
+Clock Skew : 0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 7.144
+ Launch Clock Delay : 6.677
+ Clock Pessimism Removal : -0.428
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -12060,25 +13314,25 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 0.895 6.654 ntclkbufg_0
- CLMA_58_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK
+ net (fanout=5464) 0.918 6.677 ntclkbufg_0
+ CLMA_34_76/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
- CLMA_58_124/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/Q
- net (fanout=2) 0.255 7.088 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [22]
- CLMS_50_129/DD f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD
+ CLMA_34_76/Q0 tco 0.179 6.856 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0
+ net (fanout=44) 0.268 7.124 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
+ CLMS_42_81/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0
- Data arrival time 7.088 Logic Levels: 0
- Logic: 0.179ns(41.244%), Route: 0.255ns(58.756%)
+ Data arrival time 7.124 Logic Levels: 0
+ Logic: 0.179ns(40.045%), Route: 0.268ns(59.955%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -12089,41 +13343,41 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMS_50_129/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK
- clock pessimism -0.417 6.684
- clock uncertainty 0.000 6.684
+ net (fanout=5464) 0.968 7.144 ntclkbufg_0
+ CLMS_42_81/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK
+ clock pessimism -0.428 6.716
+ clock uncertainty 0.000 6.716
- Hold time 0.293 6.977
+ Hold time 0.293 7.009
- Data required time 6.977
+ Data required time 7.009
----------------------------------------------------------------------------------------------------
- Data required time 6.977
- Data arrival time 7.088
+ Data required time 7.009
+ Data arrival time 7.124
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.111
+ Slack (MET) 0.115
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WADM0
Path Group : ddrphy_clkin
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 7.101
- Launch Clock Delay : 6.654
+Clock Skew : 0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 7.144
+ Launch Clock Delay : 6.677
Clock Pessimism Removal : -0.428
Location Delay Type Incr Path Logical Resource
@@ -12137,25 +13391,25 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 0.895 6.654 ntclkbufg_0
- CLMA_58_144/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
+ net (fanout=5464) 0.918 6.677 ntclkbufg_0
+ CLMA_34_76/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
- CLMA_58_144/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0
- net (fanout=7) 0.251 7.084 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
- CLMS_62_145/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0
+ CLMA_34_76/Q0 tco 0.179 6.856 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0
+ net (fanout=44) 0.268 7.124 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
+ CLMS_42_81/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WADM0
- Data arrival time 7.084 Logic Levels: 0
- Logic: 0.179ns(41.628%), Route: 0.251ns(58.372%)
+ Data arrival time 7.124 Logic Levels: 0
+ Logic: 0.179ns(40.045%), Route: 0.268ns(59.955%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -12166,41 +13420,41 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMS_62_145/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WCLK
- clock pessimism -0.428 6.673
- clock uncertainty 0.000 6.673
+ net (fanout=5464) 0.968 7.144 ntclkbufg_0
+ CLMS_42_81/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WCLK
+ clock pessimism -0.428 6.716
+ clock uncertainty 0.000 6.716
- Hold time 0.293 6.966
+ Hold time 0.293 7.009
- Data required time 6.966
+ Data required time 7.009
----------------------------------------------------------------------------------------------------
- Data required time 6.966
- Data arrival time 7.084
+ Data required time 7.009
+ Data arrival time 7.124
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.118
+ Slack (MET) 0.115
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WADM0
Path Group : ddrphy_clkin
Path Type : min (fast corner)
Path Class : sequential timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 7.101
- Launch Clock Delay : 6.654
+Clock Skew : 0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 7.144
+ Launch Clock Delay : 6.677
Clock Pessimism Removal : -0.428
Location Delay Type Incr Path Logical Resource
@@ -12214,25 +13468,25 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 0.895 6.654 ntclkbufg_0
- CLMA_58_144/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
+ net (fanout=5464) 0.918 6.677 ntclkbufg_0
+ CLMA_34_76/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
- CLMA_58_144/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0
- net (fanout=7) 0.251 7.084 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
- CLMS_62_145/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0
+ CLMA_34_76/Q0 tco 0.179 6.856 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0
+ net (fanout=44) 0.268 7.124 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0]
+ CLMS_42_81/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WADM0
- Data arrival time 7.084 Logic Levels: 0
- Logic: 0.179ns(41.628%), Route: 0.251ns(58.372%)
+ Data arrival time 7.124 Logic Levels: 0
+ Logic: 0.179ns(40.045%), Route: 0.268ns(59.955%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -12243,29 +13497,29 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMS_62_145/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WCLK
- clock pessimism -0.428 6.673
- clock uncertainty 0.000 6.673
+ net (fanout=5464) 0.968 7.144 ntclkbufg_0
+ CLMS_42_81/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK
+ clock pessimism -0.428 6.716
+ clock uncertainty 0.000 6.716
- Hold time 0.293 6.966
+ Hold time 0.293 7.009
- Data required time 6.966
+ Data required time 7.009
----------------------------------------------------------------------------------------------------
- Data required time 6.966
- Data arrival time 7.084
+ Data required time 7.009
+ Data arrival time 7.124
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.118
+ Slack (MET) 0.115
====================================================================================================
====================================================================================================
@@ -12291,9 +13545,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12316,9 +13570,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 4.360 _N69
PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 5.037 zoom_clk
+ net (fanout=2) 0.603 5.037 ddr_clk
USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 6.776 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12360,9 +13614,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12385,9 +13639,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 4.360 _N69
PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 5.037 zoom_clk
+ net (fanout=2) 0.603 5.037 ddr_clk
USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 6.776 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12429,9 +13683,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12454,9 +13708,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 4.360 _N69
PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 5.037 zoom_clk
+ net (fanout=2) 0.603 5.037 ddr_clk
USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 6.776 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12498,9 +13752,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12523,9 +13777,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12567,9 +13821,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12592,9 +13846,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12636,9 +13890,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12661,9 +13915,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT
@@ -12705,9 +13959,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -12730,9 +13984,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 4.360 _N69
PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 5.037 zoom_clk
+ net (fanout=2) 0.603 5.037 ddr_clk
USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 6.776 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -12774,9 +14028,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -12799,9 +14053,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 4.360 _N69
PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 5.037 zoom_clk
+ net (fanout=2) 0.603 5.037 ddr_clk
USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 6.776 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -12843,9 +14097,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -12868,9 +14122,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 4.360 _N69
PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 5.037 zoom_clk
+ net (fanout=2) 0.603 5.037 ddr_clk
USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 6.776 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -12912,9 +14166,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -12937,9 +14191,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -12981,9 +14235,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -13006,9 +14260,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -13050,9 +14304,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -13075,9 +14329,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT
@@ -13099,12 +14353,134 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
====================================================================================================
Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS
+Path Group : clk_50m
+Path Type : max (fast corner)
+Path Class : async timing path
+Clock Skew : -0.018 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.448
+ Launch Clock Delay : 3.736
+ Clock Pessimism Removal : 0.270
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.925 3.736 ntclkbufg_1
+ CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
+
+ CLMS_158_237/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=589) 2.173 6.130 rd3_rst
+ CLMA_58_40/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS
+
+ Data arrival time 6.130 Logic Levels: 0
+ Logic: 0.221ns(9.231%), Route: 2.173ns(90.769%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 20.000 20.000 r
+ P20 0.000 20.000 r clk (port)
+ net (fanout=1) 0.074 20.074 clk
+ IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 21.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 21.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 22.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.907 23.448 ntclkbufg_1
+ CLMA_58_40/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK
+ clock pessimism 0.270 23.718
+ clock uncertainty -0.150 23.568
+
+ Recovery time -0.476 23.092
+
+ Data required time 23.092
+----------------------------------------------------------------------------------------------------
+ Data required time 23.092
+ Data arrival time 6.130
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 16.962
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS
+Path Group : clk_50m
+Path Type : max (fast corner)
+Path Class : async timing path
+Clock Skew : -0.010 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.456
+ Launch Clock Delay : 3.736
+ Clock Pessimism Removal : 0.270
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.925 3.736 ntclkbufg_1
+ CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
+
+ CLMS_158_237/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=589) 2.069 6.026 rd3_rst
+ CLMA_58_33/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS
+
+ Data arrival time 6.026 Logic Levels: 0
+ Logic: 0.221ns(9.651%), Route: 2.069ns(90.349%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 20.000 20.000 r
+ P20 0.000 20.000 r clk (port)
+ net (fanout=1) 0.074 20.074 clk
+ IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 21.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 21.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 22.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.915 23.456 ntclkbufg_1
+ CLMA_58_33/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK
+ clock pessimism 0.270 23.726
+ clock uncertainty -0.150 23.576
+
+ Recovery time -0.476 23.100
+
+ Data required time 23.100
+----------------------------------------------------------------------------------------------------
+ Data required time 23.100
+ Data arrival time 6.026
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 17.074
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS
Path Group : clk_50m
Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.436
+Clock Skew : -0.010 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.456
Launch Clock Delay : 3.736
Clock Pessimism Removal : 0.270
@@ -13121,891 +14497,1141 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.925 3.736 ntclkbufg_1
- CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-
- CLMS_94_177/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=573) 1.712 5.669 rd3_rst
- CLMS_146_37/RSCO td 0.113 5.782 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT
- net (fanout=4) 0.000 5.782 ntR414
- CLMS_146_41/RSCO td 0.113 5.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 5.895 ntR413
- CLMS_146_45/RSCO td 0.113 6.008 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=3) 0.000 6.008 ntR412
- CLMS_146_49/RSCO td 0.113 6.121 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT
- net (fanout=2) 0.000 6.121 ntR411
- CLMS_146_53/RSCO td 0.113 6.234 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
- net (fanout=4) 0.000 6.234 ntR410
- CLMS_146_57/RSCO td 0.113 6.347 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT
- net (fanout=6) 0.000 6.347 ntR409
- CLMS_146_61/RSCO td 0.113 6.460 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT
- net (fanout=5) 0.000 6.460 ntR408
- CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS
-
- Data arrival time 6.460 Logic Levels: 7
- Logic: 1.012ns(37.151%), Route: 1.712ns(62.849%)
+ net (fanout=2516) 0.925 3.736 ntclkbufg_1
+ CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
+
+ CLMS_158_237/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=589) 2.069 6.026 rd3_rst
+ CLMA_58_33/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS
+
+ Data arrival time 6.026 Logic Levels: 0
+ Logic: 0.221ns(9.651%), Route: 2.069ns(90.349%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 20.000 20.000 r
+ P20 0.000 20.000 r clk (port)
+ net (fanout=1) 0.074 20.074 clk
+ IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 21.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 21.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 22.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 0.915 23.456 ntclkbufg_1
+ CLMA_58_33/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK
+ clock pessimism 0.270 23.726
+ clock uncertainty -0.150 23.576
+
+ Recovery time -0.476 23.100
+
+ Data required time 23.100
+----------------------------------------------------------------------------------------------------
+ Data required time 23.100
+ Data arrival time 6.026
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 17.074
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS
+Path Group : clk_50m
+Path Type : min (fast corner)
+Path Class : async timing path
+Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.848
+ Launch Clock Delay : 3.546
+ Clock Pessimism Removal : -0.283
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 1.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 1.005 3.546 ntclkbufg_1
+ CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+
+ CLMS_98_321/Q0 tco 0.182 3.728 r image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
+ net (fanout=40) 0.206 3.934 image_filiter_inst/multiline_buffer_inst/srst
+ CLMS_102_325/RSCO td 0.085 4.019 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 4.019 ntR19
+ CLMS_102_329/RSCI r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS
+
+ Data arrival time 4.019 Logic Levels: 1
+ Logic: 0.267ns(56.448%), Route: 0.206ns(43.552%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 1.037 3.848 ntclkbufg_1
+ CLMS_102_329/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK
+ clock pessimism -0.283 3.565
+ clock uncertainty 0.000 3.565
+
+ Removal time 0.000 3.565
+
+ Data required time 3.565
+----------------------------------------------------------------------------------------------------
+ Data required time 3.565
+ Data arrival time 4.019
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 0.454
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS
+Path Group : clk_50m
+Path Type : min (fast corner)
+Path Class : async timing path
+Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.848
+ Launch Clock Delay : 3.546
+ Clock Pessimism Removal : -0.283
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 1.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 1.005 3.546 ntclkbufg_1
+ CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+
+ CLMS_98_321/Q0 tco 0.182 3.728 r image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
+ net (fanout=40) 0.206 3.934 image_filiter_inst/multiline_buffer_inst/srst
+ CLMS_102_325/RSCO td 0.085 4.019 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 4.019 ntR19
+ CLMS_102_329/RSCI r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS
+
+ Data arrival time 4.019 Logic Levels: 1
+ Logic: 0.267ns(56.448%), Route: 0.206ns(43.552%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 1.037 3.848 ntclkbufg_1
+ CLMS_102_329/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK
+ clock pessimism -0.283 3.565
+ clock uncertainty 0.000 3.565
+
+ Removal time 0.000 3.565
+
+ Data required time 3.565
+----------------------------------------------------------------------------------------------------
+ Data required time 3.565
+ Data arrival time 4.019
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 0.454
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+Endpoint : image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+Path Group : clk_50m
+Path Type : min (fast corner)
+Path Class : async timing path
+Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.848
+ Launch Clock Delay : 3.546
+ Clock Pessimism Removal : -0.283
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 1.860 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 1.005 3.546 ntclkbufg_1
+ CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+
+ CLMS_98_321/Q0 tco 0.179 3.725 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
+ net (fanout=40) 0.282 4.007 image_filiter_inst/multiline_buffer_inst/srst
+ DRM_82_316/RSTB[0] f image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+
+ Data arrival time 4.007 Logic Levels: 0
+ Logic: 0.179ns(38.829%), Route: 0.282ns(61.171%)
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_50m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
+ net (fanout=2516) 1.037 3.848 ntclkbufg_1
+ DRM_82_316/CLKB[0] r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0]
+ clock pessimism -0.283 3.565
+ clock uncertainty 0.000 3.565
+
+ Removal time -0.018 3.547
+
+ Data required time 3.547
+----------------------------------------------------------------------------------------------------
+ Data required time 3.547
+ Data arrival time 4.007
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 0.460
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS
+Path Group : clk_200m
+Path Type : max (fast corner)
+Path Class : async timing path
+Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.432
+ Launch Clock Delay : 3.844
+ Clock Pessimism Removal : 0.270
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_200m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.037 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+
+ CLMA_174_252/Q1 tco 0.223 4.067 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q
+ net (fanout=687) 1.849 5.916 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn
+ CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS
+
+ Data arrival time 5.916 Logic Levels: 0
+ Logic: 0.223ns(10.763%), Route: 1.849ns(89.237%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 20.000 20.000 r
- P20 0.000 20.000 r clk (port)
- net (fanout=1) 0.074 20.074 clk
- IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 21.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 21.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 22.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.895 23.436 ntclkbufg_1
- CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK
- clock pessimism 0.270 23.706
- clock uncertainty -0.150 23.556
+ Clock clk_200m (rising edge) 5.000 5.000 r
+ P20 0.000 5.000 r clk (port)
+ net (fanout=1) 0.074 5.074 clk
+ IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 6.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 6.860 _N69
+ PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 7.537 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/CLK
+ clock pessimism 0.270 8.702
+ clock uncertainty -0.150 8.552
- Recovery time 0.000 23.556
+ Recovery time -0.476 8.076
- Data required time 23.556
+ Data required time 8.076
----------------------------------------------------------------------------------------------------
- Data required time 23.556
- Data arrival time 6.460
+ Data required time 8.076
+ Data arrival time 5.916
----------------------------------------------------------------------------------------------------
- Slack (MET) 17.096
+ Slack (MET) 2.160
====================================================================================================
====================================================================================================
-Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS
-Path Group : clk_50m
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS
+Path Group : clk_200m
Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.436
- Launch Clock Delay : 3.736
+Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.432
+ Launch Clock Delay : 3.844
Clock Pessimism Removal : 0.270
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.614 2.811 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.925 3.736 ntclkbufg_1
- CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-
- CLMS_94_177/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=573) 1.712 5.669 rd3_rst
- CLMS_146_37/RSCO td 0.113 5.782 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT
- net (fanout=4) 0.000 5.782 ntR414
- CLMS_146_41/RSCO td 0.113 5.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 5.895 ntR413
- CLMS_146_45/RSCO td 0.113 6.008 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=3) 0.000 6.008 ntR412
- CLMS_146_49/RSCO td 0.113 6.121 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT
- net (fanout=2) 0.000 6.121 ntR411
- CLMS_146_53/RSCO td 0.113 6.234 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
- net (fanout=4) 0.000 6.234 ntR410
- CLMS_146_57/RSCO td 0.113 6.347 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT
- net (fanout=6) 0.000 6.347 ntR409
- CLMS_146_61/RSCO td 0.113 6.460 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT
- net (fanout=5) 0.000 6.460 ntR408
- CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS
-
- Data arrival time 6.460 Logic Levels: 7
- Logic: 1.012ns(37.151%), Route: 1.712ns(62.849%)
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.037 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+
+ CLMA_174_252/Q1 tco 0.223 4.067 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q
+ net (fanout=687) 1.608 5.675 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn
+ CLMA_30_184/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS
+
+ Data arrival time 5.675 Logic Levels: 0
+ Logic: 0.223ns(12.179%), Route: 1.608ns(87.821%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 20.000 20.000 r
- P20 0.000 20.000 r clk (port)
- net (fanout=1) 0.074 20.074 clk
- IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 21.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 21.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 22.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.895 23.436 ntclkbufg_1
- CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK
- clock pessimism 0.270 23.706
- clock uncertainty -0.150 23.556
+ Clock clk_200m (rising edge) 5.000 5.000 r
+ P20 0.000 5.000 r clk (port)
+ net (fanout=1) 0.074 5.074 clk
+ IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 6.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 6.860 _N69
+ PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 7.537 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_30_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK
+ clock pessimism 0.270 8.702
+ clock uncertainty -0.150 8.552
- Recovery time 0.000 23.556
+ Recovery time -0.476 8.076
- Data required time 23.556
+ Data required time 8.076
----------------------------------------------------------------------------------------------------
- Data required time 23.556
- Data arrival time 6.460
+ Data required time 8.076
+ Data arrival time 5.675
----------------------------------------------------------------------------------------------------
- Slack (MET) 17.096
+ Slack (MET) 2.401
====================================================================================================
====================================================================================================
-Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS
-Path Group : clk_50m
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS
+Path Group : clk_200m
Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.436
- Launch Clock Delay : 3.736
+Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.432
+ Launch Clock Delay : 3.844
Clock Pessimism Removal : 0.270
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.614 2.811 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.925 3.736 ntclkbufg_1
- CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
-
- CLMS_94_177/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=573) 1.712 5.669 rd3_rst
- CLMS_146_37/RSCO td 0.113 5.782 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT
- net (fanout=4) 0.000 5.782 ntR414
- CLMS_146_41/RSCO td 0.113 5.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 5.895 ntR413
- CLMS_146_45/RSCO td 0.113 6.008 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=3) 0.000 6.008 ntR412
- CLMS_146_49/RSCO td 0.113 6.121 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT
- net (fanout=2) 0.000 6.121 ntR411
- CLMS_146_53/RSCO td 0.113 6.234 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
- net (fanout=4) 0.000 6.234 ntR410
- CLMS_146_57/RSCO td 0.113 6.347 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT
- net (fanout=6) 0.000 6.347 ntR409
- CLMS_146_61/RSCO td 0.113 6.460 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT
- net (fanout=5) 0.000 6.460 ntR408
- CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS
-
- Data arrival time 6.460 Logic Levels: 7
- Logic: 1.012ns(37.151%), Route: 1.712ns(62.849%)
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.037 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+
+ CLMA_174_252/Q1 tco 0.223 4.067 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q
+ net (fanout=687) 1.608 5.675 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn
+ CLMA_30_184/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS
+
+ Data arrival time 5.675 Logic Levels: 0
+ Logic: 0.223ns(12.179%), Route: 1.608ns(87.821%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 20.000 20.000 r
- P20 0.000 20.000 r clk (port)
- net (fanout=1) 0.074 20.074 clk
- IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 21.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 21.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 22.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.895 23.436 ntclkbufg_1
- CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK
- clock pessimism 0.270 23.706
- clock uncertainty -0.150 23.556
+ Clock clk_200m (rising edge) 5.000 5.000 r
+ P20 0.000 5.000 r clk (port)
+ net (fanout=1) 0.074 5.074 clk
+ IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 6.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 6.860 _N69
+ PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 7.537 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_30_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK
+ clock pessimism 0.270 8.702
+ clock uncertainty -0.150 8.552
- Recovery time 0.000 23.556
+ Recovery time -0.476 8.076
- Data required time 23.556
+ Data required time 8.076
----------------------------------------------------------------------------------------------------
- Data required time 23.556
- Data arrival time 6.460
+ Data required time 8.076
+ Data arrival time 5.675
----------------------------------------------------------------------------------------------------
- Slack (MET) 17.096
+ Slack (MET) 2.401
====================================================================================================
====================================================================================================
-Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
-Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
-Path Group : clk_50m
+Startpoint : u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS
+Path Group : clk_200m
Path Type : min (fast corner)
Path Class : async timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.736
- Launch Clock Delay : 3.436
- Clock Pessimism Removal : -0.281
+Clock Skew : 0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.844
+ Launch Clock Delay : 3.542
+ Clock Pessimism Removal : -0.263
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 2.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.895 3.436 ntclkbufg_1
- CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+ PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 2.537 ddr_clk
+ USCM_84_153/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT
+ net (fanout=6) 1.005 3.542 ntR3952
+ CLMS_174_253/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
- CLMS_134_93/Q0 tco 0.179 3.615 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
- net (fanout=37) 0.240 3.855 image_filiter_inst/multiline_buffer_inst/srst
- DRM_142_88/RSTB[0] f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+ CLMS_174_253/Q0 tco 0.179 3.721 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q
+ net (fanout=2) 0.131 3.852 ddr_rst
+ CLMA_174_252/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS
- Data arrival time 3.855 Logic Levels: 0
- Logic: 0.179ns(42.721%), Route: 0.240ns(57.279%)
+ Data arrival time 3.852 Logic Levels: 0
+ Logic: 0.179ns(57.742%), Route: 0.131ns(42.258%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.614 2.811 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.925 3.736 ntclkbufg_1
- DRM_142_88/CLKB[0] r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0]
- clock pessimism -0.281 3.455
- clock uncertainty 0.000 3.455
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.037 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK
+ clock pessimism -0.263 3.581
+ clock uncertainty 0.000 3.581
- Removal time -0.018 3.437
+ Removal time -0.181 3.400
- Data required time 3.437
+ Data required time 3.400
----------------------------------------------------------------------------------------------------
- Data required time 3.437
- Data arrival time 3.855
+ Data required time 3.400
+ Data arrival time 3.852
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.418
+ Slack (MET) 0.452
====================================================================================================
====================================================================================================
-Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
-Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0]
-Path Group : clk_50m
+Startpoint : u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS
+Path Group : clk_200m
Path Type : min (fast corner)
Path Class : async timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.736
- Launch Clock Delay : 3.436
- Clock Pessimism Removal : -0.281
+Clock Skew : 0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.844
+ Launch Clock Delay : 3.542
+ Clock Pessimism Removal : -0.263
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 2.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.895 3.436 ntclkbufg_1
- CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+ PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 2.537 ddr_clk
+ USCM_84_153/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT
+ net (fanout=6) 1.005 3.542 ntR3952
+ CLMS_174_253/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
- CLMS_134_93/Q0 tco 0.179 3.615 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
- net (fanout=37) 0.240 3.855 image_filiter_inst/multiline_buffer_inst/srst
- DRM_142_88/RSTA[0] f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0]
+ CLMS_174_253/Q0 tco 0.179 3.721 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q
+ net (fanout=2) 0.131 3.852 ddr_rst
+ CLMA_174_252/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS
- Data arrival time 3.855 Logic Levels: 0
- Logic: 0.179ns(42.721%), Route: 0.240ns(57.279%)
+ Data arrival time 3.852 Logic Levels: 0
+ Logic: 0.179ns(57.742%), Route: 0.131ns(42.258%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.614 2.811 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.925 3.736 ntclkbufg_1
- DRM_142_88/CLKA[0] r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- clock pessimism -0.281 3.455
- clock uncertainty 0.000 3.455
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 1.037 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+ clock pessimism -0.263 3.581
+ clock uncertainty 0.000 3.581
- Removal time -0.038 3.417
+ Removal time -0.181 3.400
- Data required time 3.417
+ Data required time 3.400
----------------------------------------------------------------------------------------------------
- Data required time 3.417
- Data arrival time 3.855
+ Data required time 3.400
+ Data arrival time 3.852
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.438
+ Slack (MET) 0.452
====================================================================================================
====================================================================================================
-Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
-Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS
-Path Group : clk_50m
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/RS
+Path Group : clk_200m
Path Type : min (fast corner)
Path Class : async timing path
Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.736
- Launch Clock Delay : 3.436
+ Capture Clock Delay : 3.732
+ Launch Clock Delay : 3.432
Clock Pessimism Removal : -0.281
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.603 2.541 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.895 3.436 ntclkbufg_1
- CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+ PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.603 2.537 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.895 3.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_58_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK
- CLMS_134_93/Q0 tco 0.182 3.618 r image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q
- net (fanout=37) 0.292 3.910 image_filiter_inst/multiline_buffer_inst/srst
- CLMA_138_81/RSCO td 0.085 3.995 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT
- net (fanout=2) 0.000 3.995 ntR38
- CLMA_138_85/RSCI r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS
+ CLMA_58_184/Q0 tco 0.182 3.614 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/Q
+ net (fanout=22) 0.316 3.930 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn
+ CLMA_38_184/RS r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/RS
- Data arrival time 3.995 Logic Levels: 1
- Logic: 0.267ns(47.764%), Route: 0.292ns(52.236%)
+ Data arrival time 3.930 Logic Levels: 0
+ Logic: 0.182ns(36.546%), Route: 0.316ns(63.454%)
----------------------------------------------------------------------------------------------------
- Clock clk_50m (rising edge) 0.000 0.000 r
+ Clock clk_200m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
- net (fanout=2) 0.614 2.811 rd3_clk
- USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT
- net (fanout=2517) 0.925 3.736 ntclkbufg_1
- CLMA_138_85/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK
- clock pessimism -0.281 3.455
- clock uncertainty 0.000 3.455
+ PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
+ net (fanout=2) 0.614 2.807 ddr_clk
+ USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
+ net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ CLMA_38_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/CLK
+ clock pessimism -0.281 3.451
+ clock uncertainty 0.000 3.451
- Removal time 0.000 3.455
+ Removal time -0.187 3.264
- Data required time 3.455
+ Data required time 3.264
----------------------------------------------------------------------------------------------------
- Data required time 3.455
- Data arrival time 3.995
+ Data required time 3.264
+ Data arrival time 3.930
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.540
+ Slack (MET) 0.666
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS
-Path Group : clk_200m
+Startpoint : rstn_out1/opit_0_inv/CLK
+Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS
+Path Group : clk_10m
Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.432
- Launch Clock Delay : 3.732
+Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.547
+ Launch Clock Delay : 3.737
Clock Pessimism Removal : 0.270
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_10m (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+ PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.614 2.812 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 0.925 3.737 ntclkbufg_4
+ CLMS_270_193/CLK r rstn_out1/opit_0_inv/CLK
- CLMA_202_148/Q1 tco 0.223 3.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q
- net (fanout=686) 1.964 5.919 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn
- CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS
+ CLMS_270_193/Q3 tco 0.220 3.957 f rstn_out1/opit_0_inv/Q
+ net (fanout=3) 0.853 4.810 nt_eth_rstn
+ CLMA_262_268/RS f ms72xx_ctl/rstn_temp1/opit_0_inv/RS
- Data arrival time 5.919 Logic Levels: 0
- Logic: 0.223ns(10.197%), Route: 1.964ns(89.803%)
+ Data arrival time 4.810 Logic Levels: 0
+ Logic: 0.220ns(20.503%), Route: 0.853ns(79.497%)
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 5.000 5.000 r
- P20 0.000 5.000 r clk (port)
- net (fanout=1) 0.074 5.074 clk
- IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 6.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 6.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 7.537 zoom_clk
- USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK
- clock pessimism 0.270 8.702
- clock uncertainty -0.150 8.552
+ Clock clk_10m (rising edge) 100.000 100.000 r
+ P20 0.000 100.000 r clk (port)
+ net (fanout=1) 0.074 100.074 clk
+ IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 101.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 101.860 _N69
+ PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.603 102.542 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.005 103.547 ntclkbufg_4
+ CLMA_262_268/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK
+ clock pessimism 0.270 103.817
+ clock uncertainty -0.150 103.667
+
+ Recovery time -0.476 103.191
+
+ Data required time 103.191
+----------------------------------------------------------------------------------------------------
+ Data required time 103.191
+ Data arrival time 4.810
+----------------------------------------------------------------------------------------------------
+ Slack (MET) 98.381
+====================================================================================================
+
+====================================================================================================
+
+Startpoint : rstn_out1/opit_0_inv/CLK
+Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS
+Path Group : clk_10m
+Path Type : min (fast corner)
+Path Class : async timing path
+Clock Skew : 0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 3.849
+ Launch Clock Delay : 3.437
+ Clock Pessimism Removal : -0.270
+
+ Location Delay Type Incr Path Logical Resource
+----------------------------------------------------------------------------------------------------
+
+ Clock clk_10m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.359 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 1.860 _N69
+ PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.603 2.542 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 0.895 3.437 ntclkbufg_4
+ CLMS_270_193/CLK r rstn_out1/opit_0_inv/CLK
+
+ CLMS_270_193/Q3 tco 0.182 3.619 r rstn_out1/opit_0_inv/Q
+ net (fanout=3) 0.646 4.265 nt_eth_rstn
+ CLMA_262_268/RS r ms72xx_ctl/rstn_temp1/opit_0_inv/RS
+
+ Data arrival time 4.265 Logic Levels: 0
+ Logic: 0.182ns(21.981%), Route: 0.646ns(78.019%)
+----------------------------------------------------------------------------------------------------
- Recovery time -0.476 8.076
+ Clock clk_10m (rising edge) 0.000 0.000 r
+ P20 0.000 0.000 r clk (port)
+ net (fanout=1) 0.074 0.074 clk
+ IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 1.578 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.478 2.114 _N69
+ PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
+ net (fanout=1) 0.614 2.812 clk_10m
+ USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT
+ net (fanout=235) 1.037 3.849 ntclkbufg_4
+ CLMA_262_268/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK
+ clock pessimism -0.270 3.579
+ clock uncertainty 0.000 3.579
- Data required time 8.076
+ Removal time -0.187 3.392
+
+ Data required time 3.392
----------------------------------------------------------------------------------------------------
- Data required time 8.076
- Data arrival time 5.919
+ Data required time 3.392
+ Data arrival time 4.265
----------------------------------------------------------------------------------------------------
- Slack (MET) 2.157
+ Slack (MET) 0.873
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS
-Path Group : clk_200m
+Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.432
- Launch Clock Delay : 3.732
- Clock Pessimism Removal : 0.270
+Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.630
+ Launch Clock Delay : 5.882
+ Clock Pessimism Removal : 0.332
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.925 5.882 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
- CLMA_202_148/Q1 tco 0.223 3.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q
- net (fanout=686) 1.964 5.919 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn
- CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS
+ CLMA_170_124/Q0 tco 0.221 6.103 f u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 2.069 8.172 zoom_rst
+ DRM_306_252/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0]
- Data arrival time 5.919 Logic Levels: 0
- Logic: 0.223ns(10.197%), Route: 1.964ns(89.803%)
+ Data arrival time 8.172 Logic Levels: 0
+ Logic: 0.221ns(9.651%), Route: 2.069ns(90.349%)
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 5.000 5.000 r
- P20 0.000 5.000 r clk (port)
- net (fanout=1) 0.074 5.074 clk
- IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 6.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 6.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 7.537 zoom_clk
- USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK
- clock pessimism 0.270 8.702
- clock uncertainty -0.150 8.552
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.095 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 8.596 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 9.277 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 10.368 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 11.361 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.005 12.366 ntclkbufg_3
+ DRM_306_252/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism 0.332 12.698
+ clock uncertainty -0.150 12.548
- Recovery time -0.476 8.076
+ Recovery time -0.088 12.460
- Data required time 8.076
+ Data required time 12.460
----------------------------------------------------------------------------------------------------
- Data required time 8.076
- Data arrival time 5.919
+ Data required time 12.460
+ Data arrival time 8.172
----------------------------------------------------------------------------------------------------
- Slack (MET) 2.157
+ Slack (MET) 4.288
====================================================================================================
====================================================================================================
Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0]
-Path Group : clk_200m
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
Path Type : max (fast corner)
Path Class : async timing path
Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.542
- Launch Clock Delay : 3.732
- Clock Pessimism Removal : 0.270
+ Capture Clock Delay : 5.630
+ Launch Clock Delay : 5.882
+ Clock Pessimism Removal : 0.332
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT
- net (fanout=759) 0.925 3.732 ntR3909
- CLMS_186_125/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.925 5.882 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
- CLMS_186_125/Q0 tco 0.221 3.953 f u_zoom_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=131) 2.332 6.285 zoom_rst
- DRM_278_356/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0]
+ CLMA_170_124/Q0 tco 0.221 6.103 f u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 2.029 8.132 zoom_rst
+ DRM_306_292/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0]
- Data arrival time 6.285 Logic Levels: 0
- Logic: 0.221ns(8.656%), Route: 2.332ns(91.344%)
+ Data arrival time 8.132 Logic Levels: 0
+ Logic: 0.221ns(9.822%), Route: 2.029ns(90.178%)
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 5.000 5.000 r
- P20 0.000 5.000 r clk (port)
- net (fanout=1) 0.074 5.074 clk
- IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 6.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 6.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 7.537 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 7.537 r USCMROUTE_2/CLKOUT
- net (fanout=759) 1.005 8.542 ntR3909
- DRM_278_356/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/CLKA[0]
- clock pessimism 0.270 8.812
- clock uncertainty -0.150 8.662
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.095 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 8.596 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 9.277 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 10.368 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 11.361 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.005 12.366 ntclkbufg_3
+ DRM_306_292/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism 0.332 12.698
+ clock uncertainty -0.150 12.548
- Recovery time -0.088 8.574
+ Recovery time -0.088 12.460
- Data required time 8.574
+ Data required time 12.460
----------------------------------------------------------------------------------------------------
- Data required time 8.574
- Data arrival time 6.285
+ Data required time 12.460
+ Data arrival time 8.132
----------------------------------------------------------------------------------------------------
- Slack (MET) 2.289
+ Slack (MET) 4.328
====================================================================================================
====================================================================================================
-Startpoint : u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS
-Path Group : clk_200m
-Path Type : min (fast corner)
+Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
+Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : 0.037 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.732
- Launch Clock Delay : 3.432
- Clock Pessimism Removal : -0.263
+Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.630
+ Launch Clock Delay : 5.882
+ Clock Pessimism Removal : 0.332
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
- P20 0.000 0.000 r clk (port)
- net (fanout=1) 0.074 0.074 clk
- IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 1.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT
- net (fanout=759) 0.895 3.432 ntR3909
- CLMS_202_149/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
-
- CLMS_202_149/Q0 tco 0.179 3.611 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q
- net (fanout=2) 0.129 3.740 ddr_rst
- CLMA_202_148/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS
-
- Data arrival time 3.740 Logic Levels: 0
- Logic: 0.179ns(58.117%), Route: 0.129ns(41.883%)
-----------------------------------------------------------------------------------------------------
-
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK
- clock pessimism -0.263 3.469
- clock uncertainty 0.000 3.469
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.925 5.882 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+
+ CLMA_170_124/Q0 tco 0.221 6.103 f u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 1.973 8.076 zoom_rst
+ DRM_306_272/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0]
+
+ Data arrival time 8.076 Logic Levels: 0
+ Logic: 0.221ns(10.073%), Route: 1.973ns(89.927%)
+----------------------------------------------------------------------------------------------------
- Removal time -0.181 3.288
+ Clock clk_1080p60Hz (rising edge) 6.736 6.736 r
+ P20 0.000 6.736 r clk (port)
+ net (fanout=1) 0.074 6.810 clk
+ IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O
+ net (fanout=1) 0.000 8.095 clk_ibuf/ntD
+ IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK
+ net (fanout=1) 0.463 8.596 _N69
+ PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 9.277 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 10.368 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 11.361 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 1.005 12.366 ntclkbufg_3
+ DRM_306_272/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism 0.332 12.698
+ clock uncertainty -0.150 12.548
- Data required time 3.288
+ Recovery time -0.088 12.460
+
+ Data required time 12.460
----------------------------------------------------------------------------------------------------
- Data required time 3.288
- Data arrival time 3.740
+ Data required time 12.460
+ Data arrival time 8.076
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.452
+ Slack (MET) 4.384
====================================================================================================
====================================================================================================
-Startpoint : u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS
-Path Group : clk_200m
+Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
Path Type : min (fast corner)
Path Class : async timing path
-Clock Skew : 0.037 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.732
- Launch Clock Delay : 3.432
- Clock Pessimism Removal : -0.263
+Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.882
+ Launch Clock Delay : 5.520
+ Clock Pessimism Removal : -0.332
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
- USCM_84_122/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT
- net (fanout=759) 0.895 3.432 ntR3909
- CLMS_202_149/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 3.632 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 4.625 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.895 5.520 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
- CLMS_202_149/Q0 tco 0.179 3.611 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q
- net (fanout=2) 0.129 3.740 ddr_rst
- CLMA_202_148/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS
+ CLMA_170_124/Q0 tco 0.182 5.702 r u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 0.648 6.350 zoom_rst
+ DRM_234_128/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0]
- Data arrival time 3.740 Logic Levels: 0
- Logic: 0.179ns(58.117%), Route: 0.129ns(41.883%)
+ Data arrival time 6.350 Logic Levels: 0
+ Logic: 0.182ns(21.928%), Route: 0.648ns(78.072%)
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
- clock pessimism -0.263 3.469
- clock uncertainty 0.000 3.469
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.925 5.882 ntclkbufg_3
+ DRM_234_128/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism -0.332 5.550
+ clock uncertainty 0.000 5.550
- Removal time -0.181 3.288
+ Removal time -0.060 5.490
- Data required time 3.288
+ Data required time 5.490
----------------------------------------------------------------------------------------------------
- Data required time 3.288
- Data arrival time 3.740
+ Data required time 5.490
+ Data arrival time 6.350
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.452
+ Slack (MET) 0.860
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS
-Path Group : clk_200m
+Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
Path Type : min (fast corner)
Path Class : async timing path
Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.732
- Launch Clock Delay : 3.432
- Clock Pessimism Removal : -0.281
+ Capture Clock Delay : 5.882
+ Launch Clock Delay : 5.520
+ Clock Pessimism Removal : -0.343
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_200m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
- USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.895 3.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMS_78_181/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK
-
- CLMS_78_181/Q0 tco 0.182 3.614 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/Q
- net (fanout=14) 0.278 3.892 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn
- CLMS_62_181/RSCO td 0.092 3.984 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 3.984 ntR1581
- CLMS_62_185/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS
-
- Data arrival time 3.984 Logic Levels: 1
- Logic: 0.274ns(49.638%), Route: 0.278ns(50.362%)
-----------------------------------------------------------------------------------------------------
-
- Clock clk_200m (rising edge) 0.000 0.000 r
- P20 0.000 0.000 r clk (port)
- net (fanout=1) 0.074 0.074 clk
- IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 1.578 clk_ibuf/ntD
- IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
- USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
- CLMS_62_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/CLK
- clock pessimism -0.281 3.451
- clock uncertainty 0.000 3.451
-
- Removal time 0.000 3.451
-
- Data required time 3.451
-----------------------------------------------------------------------------------------------------
- Data required time 3.451
- Data arrival time 3.984
-----------------------------------------------------------------------------------------------------
- Slack (MET) 0.533
-====================================================================================================
-
-====================================================================================================
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 3.632 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 4.625 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.895 5.520 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
-Startpoint : rstn_out1/opit_0_inv/CLK
-Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS
-Path Group : clk_10m
-Path Type : max (fast corner)
-Path Class : async timing path
-Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.437
- Launch Clock Delay : 3.737
- Clock Pessimism Removal : 0.281
+ CLMA_170_124/Q0 tco 0.182 5.702 r u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 0.689 6.391 zoom_rst
+ DRM_234_88/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0]
- Location Delay Type Incr Path Logical Resource
+ Data arrival time 6.391 Logic Levels: 0
+ Logic: 0.182ns(20.896%), Route: 0.689ns(79.104%)
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.614 2.812 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.925 3.737 ntclkbufg_3
- CLMA_230_69/CLK r rstn_out1/opit_0_inv/CLK
-
- CLMA_230_69/Q3 tco 0.220 3.957 f rstn_out1/opit_0_inv/Q
- net (fanout=3) 0.776 4.733 nt_eth_rstn
- CLMA_246_120/RS f ms72xx_ctl/rstn_temp1/opit_0_inv/RS
-
- Data arrival time 4.733 Logic Levels: 0
- Logic: 0.220ns(22.088%), Route: 0.776ns(77.912%)
-----------------------------------------------------------------------------------------------------
-
- Clock clk_10m (rising edge) 100.000 100.000 r
- P20 0.000 100.000 r clk (port)
- net (fanout=1) 0.074 100.074 clk
- IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O
- net (fanout=1) 0.000 101.359 clk_ibuf/ntD
- IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK
- net (fanout=1) 0.463 101.860 _N69
- PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.603 102.542 clk_10m
- USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.895 103.437 ntclkbufg_3
- CLMA_246_120/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK
- clock pessimism 0.281 103.718
- clock uncertainty -0.150 103.568
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.925 5.882 ntclkbufg_3
+ DRM_234_88/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism -0.343 5.539
+ clock uncertainty 0.000 5.539
- Recovery time -0.476 103.092
+ Removal time -0.060 5.479
- Data required time 103.092
+ Data required time 5.479
----------------------------------------------------------------------------------------------------
- Data required time 103.092
- Data arrival time 4.733
+ Data required time 5.479
+ Data arrival time 6.391
----------------------------------------------------------------------------------------------------
- Slack (MET) 98.359
+ Slack (MET) 0.912
====================================================================================================
====================================================================================================
-Startpoint : rstn_out1/opit_0_inv/CLK
-Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS
-Path Group : clk_10m
+Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0]
+Path Group : clk_1080p60Hz
Path Type : min (fast corner)
Path Class : async timing path
Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 3.737
- Launch Clock Delay : 3.437
- Clock Pessimism Removal : -0.281
+ Capture Clock Delay : 5.882
+ Launch Clock Delay : 5.520
+ Clock Pessimism Removal : -0.343
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.359 clk_ibuf/ntD
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
- PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.603 2.542 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.895 3.437 ntclkbufg_3
- CLMA_230_69/CLK r rstn_out1/opit_0_inv/CLK
+ PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.603 2.541 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.091 3.632 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.915 4.625 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.895 5.520 ntclkbufg_3
+ CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK
- CLMA_230_69/Q3 tco 0.182 3.619 r rstn_out1/opit_0_inv/Q
- net (fanout=3) 0.565 4.184 nt_eth_rstn
- CLMA_246_120/RS r ms72xx_ctl/rstn_temp1/opit_0_inv/RS
+ CLMA_170_124/Q0 tco 0.182 5.702 r u_zoom_rst/rst/opit_0_L5Q_perm/Q
+ net (fanout=114) 0.722 6.424 zoom_rst
+ DRM_234_108/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0]
- Data arrival time 4.184 Logic Levels: 0
- Logic: 0.182ns(24.364%), Route: 0.565ns(75.636%)
+ Data arrival time 6.424 Logic Levels: 0
+ Logic: 0.182ns(20.133%), Route: 0.722ns(79.867%)
----------------------------------------------------------------------------------------------------
- Clock clk_10m (rising edge) 0.000 0.000 r
+ Clock clk_1080p60Hz (rising edge) 0.000 0.000 r
P20 0.000 0.000 r clk (port)
net (fanout=1) 0.074 0.074 clk
IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O
net (fanout=1) 0.000 1.578 clk_ibuf/ntD
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
- PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4
- net (fanout=1) 0.614 2.812 clk_10m
- USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT
- net (fanout=235) 0.925 3.737 ntclkbufg_3
- CLMA_246_120/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK
- clock pessimism -0.281 3.456
- clock uncertainty 0.000 3.456
+ PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
+ net (fanout=2) 0.614 2.811 rd3_clk
+ USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
+ net (fanout=1) 1.131 3.942 ntR3950
+ PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0
+ net (fanout=1) 0.932 4.957 zoom_clk
+ USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT
+ net (fanout=750) 0.925 5.882 ntclkbufg_3
+ DRM_234_108/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ clock pessimism -0.343 5.539
+ clock uncertainty 0.000 5.539
- Removal time -0.187 3.269
+ Removal time -0.060 5.479
- Data required time 3.269
+ Data required time 5.479
----------------------------------------------------------------------------------------------------
- Data required time 3.269
- Data arrival time 4.184
+ Data required time 5.479
+ Data arrival time 6.424
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.915
+ Slack (MET) 0.945
====================================================================================================
====================================================================================================
Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS
Path Group : clk_720p60Hz
Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.516
- Launch Clock Delay : 5.878
+Clock Skew : -0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.626
+ Launch Clock Delay : 5.990
Clock Pessimism Removal : 0.332
Location Delay Type Incr Path Logical Resource
@@ -14021,39 +15647,47 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.925 5.878 ntclkbufg_2
- CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-
- CLMS_150_245/Q0 tco 0.221 6.099 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
- net (fanout=1066) 2.027 8.126 sync_vg_100m
- CLMA_294_132/RSCO td 0.113 8.239 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.239 ntR491
- CLMA_294_136/RSCO td 0.113 8.352 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.352 ntR490
- CLMA_294_140/RSCO td 0.113 8.465 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=1) 0.000 8.465 ntR489
- CLMA_294_144/RSCO td 0.113 8.578 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 8.578 ntR488
- CLMA_294_148/RSCO td 0.113 8.691 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 8.691 ntR487
- CLMA_294_152/RSCO td 0.113 8.804 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.804 ntR486
- CLMA_294_156/RSCO td 0.113 8.917 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.917 ntR485
- CLMA_294_160/RSCO td 0.113 9.030 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.030 ntR484
- CLMA_294_164/RSCO td 0.113 9.143 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 9.143 ntR483
- CLMA_294_168/RSCO td 0.113 9.256 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 9.256 ntR482
- CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS
-
- Data arrival time 9.256 Logic Levels: 10
- Logic: 1.351ns(39.994%), Route: 2.027ns(60.006%)
+ net (fanout=1635) 1.037 5.990 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_150_276/Q0 tco 0.221 6.211 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 1.365 7.576 sync_vg_100m
+ CLMA_190_240/RSCO td 0.113 7.689 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT
+ net (fanout=3) 0.000 7.689 ntR687
+ CLMA_190_244/RSCO td 0.113 7.802 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT
+ net (fanout=4) 0.000 7.802 ntR686
+ CLMA_190_248/RSCO td 0.113 7.915 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 7.915 ntR685
+ CLMA_190_252/RSCO td 0.113 8.028 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT
+ net (fanout=6) 0.000 8.028 ntR684
+ CLMA_190_256/RSCO td 0.113 8.141 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT
+ net (fanout=5) 0.000 8.141 ntR683
+ CLMA_190_260/RSCO td 0.113 8.254 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 8.254 ntR682
+ CLMA_190_264/RSCO td 0.113 8.367 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT
+ net (fanout=4) 0.000 8.367 ntR681
+ CLMA_190_268/RSCO td 0.113 8.480 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.480 ntR680
+ CLMA_190_272/RSCO td 0.113 8.593 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.593 ntR679
+ CLMA_190_276/RSCO td 0.113 8.706 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT
+ net (fanout=4) 0.000 8.706 ntR678
+ CLMA_190_280/RSCO td 0.113 8.819 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT
+ net (fanout=4) 0.000 8.819 ntR677
+ CLMA_190_284/RSCO td 0.113 8.932 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
+ net (fanout=6) 0.000 8.932 ntR676
+ CLMA_190_288/RSCO td 0.113 9.045 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT
+ net (fanout=1) 0.000 9.045 ntR675
+ CLMA_190_292/RSCO td 0.113 9.158 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT
+ net (fanout=6) 0.000 9.158 ntR674
+ CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS
+
+ Data arrival time 9.158 Logic Levels: 14
+ Logic: 1.803ns(56.913%), Route: 1.365ns(43.087%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 13.473 13.473 r
@@ -14066,35 +15700,35 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 16.014 rd3_clk
USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 17.105 ntR3907
+ net (fanout=1) 1.091 17.105 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 18.094 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.895 18.989 ntclkbufg_2
- CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/CLK
- clock pessimism 0.332 19.321
- clock uncertainty -0.150 19.171
+ net (fanout=1635) 1.005 19.099 ntclkbufg_2
+ CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK
+ clock pessimism 0.332 19.431
+ clock uncertainty -0.150 19.281
- Recovery time 0.000 19.171
+ Recovery time 0.000 19.281
- Data required time 19.171
+ Data required time 19.281
----------------------------------------------------------------------------------------------------
- Data required time 19.171
- Data arrival time 9.256
+ Data required time 19.281
+ Data arrival time 9.158
----------------------------------------------------------------------------------------------------
- Slack (MET) 9.915
+ Slack (MET) 10.123
====================================================================================================
====================================================================================================
Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS
Path Group : clk_720p60Hz
Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.516
- Launch Clock Delay : 5.878
+Clock Skew : -0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.626
+ Launch Clock Delay : 5.990
Clock Pessimism Removal : 0.332
Location Delay Type Incr Path Logical Resource
@@ -14110,39 +15744,47 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.925 5.878 ntclkbufg_2
- CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-
- CLMS_150_245/Q0 tco 0.221 6.099 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
- net (fanout=1066) 2.027 8.126 sync_vg_100m
- CLMA_294_132/RSCO td 0.113 8.239 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.239 ntR491
- CLMA_294_136/RSCO td 0.113 8.352 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.352 ntR490
- CLMA_294_140/RSCO td 0.113 8.465 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=1) 0.000 8.465 ntR489
- CLMA_294_144/RSCO td 0.113 8.578 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 8.578 ntR488
- CLMA_294_148/RSCO td 0.113 8.691 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 8.691 ntR487
- CLMA_294_152/RSCO td 0.113 8.804 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.804 ntR486
- CLMA_294_156/RSCO td 0.113 8.917 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.917 ntR485
- CLMA_294_160/RSCO td 0.113 9.030 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.030 ntR484
- CLMA_294_164/RSCO td 0.113 9.143 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 9.143 ntR483
- CLMA_294_168/RSCO td 0.113 9.256 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 9.256 ntR482
- CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS
-
- Data arrival time 9.256 Logic Levels: 10
- Logic: 1.351ns(39.994%), Route: 2.027ns(60.006%)
+ net (fanout=1635) 1.037 5.990 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_150_276/Q0 tco 0.221 6.211 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 1.365 7.576 sync_vg_100m
+ CLMA_190_240/RSCO td 0.113 7.689 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT
+ net (fanout=3) 0.000 7.689 ntR687
+ CLMA_190_244/RSCO td 0.113 7.802 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT
+ net (fanout=4) 0.000 7.802 ntR686
+ CLMA_190_248/RSCO td 0.113 7.915 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 7.915 ntR685
+ CLMA_190_252/RSCO td 0.113 8.028 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT
+ net (fanout=6) 0.000 8.028 ntR684
+ CLMA_190_256/RSCO td 0.113 8.141 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT
+ net (fanout=5) 0.000 8.141 ntR683
+ CLMA_190_260/RSCO td 0.113 8.254 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 8.254 ntR682
+ CLMA_190_264/RSCO td 0.113 8.367 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT
+ net (fanout=4) 0.000 8.367 ntR681
+ CLMA_190_268/RSCO td 0.113 8.480 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.480 ntR680
+ CLMA_190_272/RSCO td 0.113 8.593 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.593 ntR679
+ CLMA_190_276/RSCO td 0.113 8.706 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT
+ net (fanout=4) 0.000 8.706 ntR678
+ CLMA_190_280/RSCO td 0.113 8.819 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT
+ net (fanout=4) 0.000 8.819 ntR677
+ CLMA_190_284/RSCO td 0.113 8.932 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
+ net (fanout=6) 0.000 8.932 ntR676
+ CLMA_190_288/RSCO td 0.113 9.045 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT
+ net (fanout=1) 0.000 9.045 ntR675
+ CLMA_190_292/RSCO td 0.113 9.158 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT
+ net (fanout=6) 0.000 9.158 ntR674
+ CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS
+
+ Data arrival time 9.158 Logic Levels: 14
+ Logic: 1.803ns(56.913%), Route: 1.365ns(43.087%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 13.473 13.473 r
@@ -14155,35 +15797,35 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 16.014 rd3_clk
USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 17.105 ntR3907
+ net (fanout=1) 1.091 17.105 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 18.094 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.895 18.989 ntclkbufg_2
- CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/CLK
- clock pessimism 0.332 19.321
- clock uncertainty -0.150 19.171
+ net (fanout=1635) 1.005 19.099 ntclkbufg_2
+ CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK
+ clock pessimism 0.332 19.431
+ clock uncertainty -0.150 19.281
- Recovery time 0.000 19.171
+ Recovery time 0.000 19.281
- Data required time 19.171
+ Data required time 19.281
----------------------------------------------------------------------------------------------------
- Data required time 19.171
- Data arrival time 9.256
+ Data required time 19.281
+ Data arrival time 9.158
----------------------------------------------------------------------------------------------------
- Slack (MET) 9.915
+ Slack (MET) 10.123
====================================================================================================
====================================================================================================
Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS
Path Group : clk_720p60Hz
Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.516
- Launch Clock Delay : 5.878
+Clock Skew : -0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.626
+ Launch Clock Delay : 5.990
Clock Pessimism Removal : 0.332
Location Delay Type Incr Path Logical Resource
@@ -14199,39 +15841,47 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.925 5.878 ntclkbufg_2
- CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
-
- CLMS_150_245/Q0 tco 0.221 6.099 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
- net (fanout=1066) 2.027 8.126 sync_vg_100m
- CLMA_294_132/RSCO td 0.113 8.239 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.239 ntR491
- CLMA_294_136/RSCO td 0.113 8.352 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.352 ntR490
- CLMA_294_140/RSCO td 0.113 8.465 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=1) 0.000 8.465 ntR489
- CLMA_294_144/RSCO td 0.113 8.578 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 8.578 ntR488
- CLMA_294_148/RSCO td 0.113 8.691 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 8.691 ntR487
- CLMA_294_152/RSCO td 0.113 8.804 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.804 ntR486
- CLMA_294_156/RSCO td 0.113 8.917 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.917 ntR485
- CLMA_294_160/RSCO td 0.113 9.030 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.030 ntR484
- CLMA_294_164/RSCO td 0.113 9.143 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT
- net (fanout=2) 0.000 9.143 ntR483
- CLMA_294_168/RSCO td 0.113 9.256 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT
- net (fanout=4) 0.000 9.256 ntR482
- CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS
-
- Data arrival time 9.256 Logic Levels: 10
- Logic: 1.351ns(39.994%), Route: 2.027ns(60.006%)
+ net (fanout=1635) 1.037 5.990 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+
+ CLMA_150_276/Q0 tco 0.221 6.211 f sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 1.365 7.576 sync_vg_100m
+ CLMA_190_240/RSCO td 0.113 7.689 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT
+ net (fanout=3) 0.000 7.689 ntR687
+ CLMA_190_244/RSCO td 0.113 7.802 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT
+ net (fanout=4) 0.000 7.802 ntR686
+ CLMA_190_248/RSCO td 0.113 7.915 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 7.915 ntR685
+ CLMA_190_252/RSCO td 0.113 8.028 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT
+ net (fanout=6) 0.000 8.028 ntR684
+ CLMA_190_256/RSCO td 0.113 8.141 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT
+ net (fanout=5) 0.000 8.141 ntR683
+ CLMA_190_260/RSCO td 0.113 8.254 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 8.254 ntR682
+ CLMA_190_264/RSCO td 0.113 8.367 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT
+ net (fanout=4) 0.000 8.367 ntR681
+ CLMA_190_268/RSCO td 0.113 8.480 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.480 ntR680
+ CLMA_190_272/RSCO td 0.113 8.593 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.593 ntR679
+ CLMA_190_276/RSCO td 0.113 8.706 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT
+ net (fanout=4) 0.000 8.706 ntR678
+ CLMA_190_280/RSCO td 0.113 8.819 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT
+ net (fanout=4) 0.000 8.819 ntR677
+ CLMA_190_284/RSCO td 0.113 8.932 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT
+ net (fanout=6) 0.000 8.932 ntR676
+ CLMA_190_288/RSCO td 0.113 9.045 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT
+ net (fanout=1) 0.000 9.045 ntR675
+ CLMA_190_292/RSCO td 0.113 9.158 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT
+ net (fanout=6) 0.000 9.158 ntR674
+ CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS
+
+ Data arrival time 9.158 Logic Levels: 14
+ Logic: 1.803ns(56.913%), Route: 1.365ns(43.087%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 13.473 13.473 r
@@ -14244,36 +15894,36 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi
PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 16.014 rd3_clk
USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 17.105 ntR3907
+ net (fanout=1) 1.091 17.105 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 18.094 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.895 18.989 ntclkbufg_2
- CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/CLK
- clock pessimism 0.332 19.321
- clock uncertainty -0.150 19.171
+ net (fanout=1635) 1.005 19.099 ntclkbufg_2
+ CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK
+ clock pessimism 0.332 19.431
+ clock uncertainty -0.150 19.281
- Recovery time 0.000 19.171
+ Recovery time 0.000 19.281
- Data required time 19.171
+ Data required time 19.281
----------------------------------------------------------------------------------------------------
- Data required time 19.171
- Data arrival time 9.256
+ Data required time 19.281
+ Data arrival time 9.158
----------------------------------------------------------------------------------------------------
- Slack (MET) 9.915
+ Slack (MET) 10.123
====================================================================================================
====================================================================================================
-Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0]
+Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
Path Group : clk_720p60Hz
Path Type : min (fast corner)
Path Class : async timing path
-Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.878
- Launch Clock Delay : 5.516
- Clock Pessimism Removal : -0.343
+Clock Skew : 0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.990
+ Launch Clock Delay : 5.626
+ Clock Pessimism Removal : -0.332
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -14288,19 +15938,19 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 2.541 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 3.632 ntR3907
+ net (fanout=1) 1.091 3.632 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 4.621 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.895 5.516 ntclkbufg_2
- CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
+ net (fanout=1635) 1.005 5.626 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
- CLMA_190_124/Q0 tco 0.182 5.698 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=163) 0.625 6.323 rd2_rst
- DRM_234_88/RSTB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0]
+ CLMA_150_276/Q0 tco 0.182 5.808 r sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 0.509 6.317 sync_vg_100m
+ DRM_178_272/RSTB[0] r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
- Data arrival time 6.323 Logic Levels: 0
- Logic: 0.182ns(22.553%), Route: 0.625ns(77.447%)
+ Data arrival time 6.317 Logic Levels: 0
+ Logic: 0.182ns(26.339%), Route: 0.509ns(73.661%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 0.000 0.000 r
@@ -14313,35 +15963,35 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.925 5.878 ntclkbufg_2
- DRM_234_88/CLKB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/CLKB[0]
- clock pessimism -0.343 5.535
- clock uncertainty 0.000 5.535
+ net (fanout=1635) 1.037 5.990 ntclkbufg_2
+ DRM_178_272/CLKB[0] r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0]
+ clock pessimism -0.332 5.658
+ clock uncertainty 0.000 5.658
- Removal time -0.063 5.472
+ Removal time -0.063 5.595
- Data required time 5.472
+ Data required time 5.595
----------------------------------------------------------------------------------------------------
- Data required time 5.472
- Data arrival time 6.323
+ Data required time 5.595
+ Data arrival time 6.317
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.851
+ Slack (MET) 0.722
====================================================================================================
====================================================================================================
-Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS
Path Group : clk_720p60Hz
Path Type : min (fast corner)
Path Class : async timing path
-Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.878
- Launch Clock Delay : 5.516
+Clock Skew : 0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.990
+ Launch Clock Delay : 5.626
Clock Pessimism Removal : -0.332
Location Delay Type Incr Path Logical Resource
@@ -14357,19 +16007,25 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 2.541 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 3.632 ntR3907
+ net (fanout=1) 1.091 3.632 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 4.621 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.895 5.516 ntclkbufg_2
- CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
+ net (fanout=1635) 1.005 5.626 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
- CLMA_190_124/Q0 tco 0.182 5.698 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=163) 0.711 6.409 rd2_rst
- DRM_234_148/RSTB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+ CLMA_150_276/Q0 tco 0.182 5.808 r sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 0.519 6.327 sync_vg_100m
+ CLMA_182_281/RSCO td 0.085 6.412 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=3) 0.000 6.412 ntR691
+ CLMA_182_285/RSCO td 0.085 6.497 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 6.497 ntR690
+ CLMA_182_289/RSCO td 0.085 6.582 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT
+ net (fanout=5) 0.000 6.582 ntR689
+ CLMA_182_293/RSCI r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS
- Data arrival time 6.409 Logic Levels: 0
- Logic: 0.182ns(20.381%), Route: 0.711ns(79.619%)
+ Data arrival time 6.582 Logic Levels: 3
+ Logic: 0.437ns(45.711%), Route: 0.519ns(54.289%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 0.000 0.000 r
@@ -14382,35 +16038,35 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.925 5.878 ntclkbufg_2
- DRM_234_148/CLKB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0]
- clock pessimism -0.332 5.546
- clock uncertainty 0.000 5.546
+ net (fanout=1635) 1.037 5.990 ntclkbufg_2
+ CLMA_182_293/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK
+ clock pessimism -0.332 5.658
+ clock uncertainty 0.000 5.658
- Removal time -0.063 5.483
+ Removal time 0.000 5.658
- Data required time 5.483
+ Data required time 5.658
----------------------------------------------------------------------------------------------------
- Data required time 5.483
- Data arrival time 6.409
+ Data required time 5.658
+ Data arrival time 6.582
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.926
+ Slack (MET) 0.924
====================================================================================================
====================================================================================================
-Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
-Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS
Path Group : clk_720p60Hz
Path Type : min (fast corner)
Path Class : async timing path
-Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 5.878
- Launch Clock Delay : 5.516
+Clock Skew : 0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 5.990
+ Launch Clock Delay : 5.626
Clock Pessimism Removal : -0.332
Location Delay Type Incr Path Logical Resource
@@ -14426,19 +16082,25 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.603 2.541 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.091 3.632 ntR3907
+ net (fanout=1) 1.091 3.632 ntR3950
PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.915 4.621 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.895 5.516 ntclkbufg_2
- CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
+ net (fanout=1635) 1.005 5.626 ntclkbufg_2
+ CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK
- CLMA_190_124/Q0 tco 0.182 5.698 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q
- net (fanout=163) 0.738 6.436 rd2_rst
- DRM_234_168/RSTB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+ CLMA_150_276/Q0 tco 0.182 5.808 r sync_vg_100m/opit_0_inv_L5Q_perm/Q
+ net (fanout=911) 0.519 6.327 sync_vg_100m
+ CLMA_182_281/RSCO td 0.085 6.412 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=3) 0.000 6.412 ntR691
+ CLMA_182_285/RSCO td 0.085 6.497 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 6.497 ntR690
+ CLMA_182_289/RSCO td 0.085 6.582 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT
+ net (fanout=5) 0.000 6.582 ntR689
+ CLMA_182_293/RSCI r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS
- Data arrival time 6.436 Logic Levels: 0
- Logic: 0.182ns(19.783%), Route: 0.738ns(80.217%)
+ Data arrival time 6.582 Logic Levels: 3
+ Logic: 0.437ns(45.711%), Route: 0.519ns(54.289%)
----------------------------------------------------------------------------------------------------
Clock clk_720p60Hz (rising edge) 0.000 0.000 r
@@ -14451,36 +16113,36 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0
net (fanout=2) 0.614 2.811 rd3_clk
USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT
- net (fanout=1) 1.131 3.942 ntR3907
+ net (fanout=1) 1.131 3.942 ntR3950
PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1
net (fanout=2) 0.932 4.953 nt_pix_clk
USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT
- net (fanout=1635) 0.925 5.878 ntclkbufg_2
- DRM_234_168/CLKB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0]
- clock pessimism -0.332 5.546
- clock uncertainty 0.000 5.546
+ net (fanout=1635) 1.037 5.990 ntclkbufg_2
+ CLMA_182_293/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK
+ clock pessimism -0.332 5.658
+ clock uncertainty 0.000 5.658
- Removal time -0.063 5.483
+ Removal time 0.000 5.658
- Data required time 5.483
+ Data required time 5.658
----------------------------------------------------------------------------------------------------
- Data required time 5.483
- Data arrival time 6.436
+ Data required time 5.658
+ Data arrival time 6.582
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.953
+ Slack (MET) 0.924
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS
Path Group : ddrphy_clkin
Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.764
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 6.654
Launch Clock Delay : 7.101
- Clock Pessimism Removal : 0.417
+ Clock Pessimism Removal : 0.428
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -14493,59 +16155,57 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-
- CLMA_70_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 1.016 8.340 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_10_224/RSCO td 0.113 8.453 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.453 ntR1395
- CLMA_10_228/RSCO td 0.113 8.566 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.566 ntR1394
- CLMA_10_232/RSCO td 0.113 8.679 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.679 ntR1393
- CLMA_10_236/RSCO td 0.113 8.792 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 8.792 ntR1392
- CLMA_10_240/RSCO td 0.113 8.905 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 8.905 ntR1391
- CLMA_10_244/RSCO td 0.113 9.018 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.018 ntR1390
- CLMA_10_248/RSCO td 0.113 9.131 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 9.131 ntR1389
- CLMA_10_252/RSCO td 0.113 9.244 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT
- net (fanout=4) 0.000 9.244 ntR1388
- CLMA_10_256/RSCO td 0.113 9.357 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.357 ntR1387
- CLMA_10_260/RSCO td 0.113 9.470 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.470 ntR1386
- CLMA_10_264/RSCO td 0.113 9.583 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 9.583 ntR1385
- CLMA_10_268/RSCO td 0.113 9.696 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT
- net (fanout=3) 0.000 9.696 ntR1384
- CLMA_10_272/RSCO td 0.113 9.809 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT
- net (fanout=2) 0.000 9.809 ntR1383
- CLMA_10_276/RSCO td 0.113 9.922 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT
- net (fanout=2) 0.000 9.922 ntR1382
- CLMA_10_280/RSCO td 0.113 10.035 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT
- net (fanout=4) 0.000 10.035 ntR1381
- CLMA_10_284/RSCO td 0.113 10.148 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 10.148 ntR1380
- CLMA_10_288/RSCO td 0.113 10.261 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 10.261 ntR1379
- CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS
-
- Data arrival time 10.261 Logic Levels: 17
- Logic: 2.144ns(67.848%), Route: 1.016ns(32.152%)
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+
+ CLMA_46_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 0.921 8.245 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_34_148/RSCO td 0.113 8.358 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.358 ntR882
+ CLMA_34_152/RSCO td 0.113 8.471 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.471 ntR881
+ CLMA_34_156/RSCO td 0.113 8.584 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.584 ntR880
+ CLMA_34_160/RSCO td 0.113 8.697 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 8.697 ntR879
+ CLMA_34_164/RSCO td 0.113 8.810 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=3) 0.000 8.810 ntR878
+ CLMA_34_168/RSCO td 0.113 8.923 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 8.923 ntR877
+ CLMA_34_172/RSCO td 0.113 9.036 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 9.036 ntR876
+ CLMA_34_176/RSCO td 0.113 9.149 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 9.149 ntR875
+ CLMA_34_180/RSCO td 0.113 9.262 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 9.262 ntR874
+ CLMA_34_184/RSCO td 0.113 9.375 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 9.375 ntR873
+ CLMA_34_192/RSCO td 0.113 9.488 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 9.488 ntR872
+ CLMA_34_196/RSCO td 0.113 9.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=1) 0.000 9.601 ntR871
+ CLMA_34_200/RSCO td 0.113 9.714 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT
+ net (fanout=6) 0.000 9.714 ntR870
+ CLMA_34_204/RSCO td 0.113 9.827 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 9.827 ntR869
+ CLMA_34_208/RSCO td 0.113 9.940 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 9.940 ntR868
+ CLMA_34_212/RSCO td 0.113 10.053 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 10.053 ntR867
+ CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS
+
+ Data arrival time 10.053 Logic Levels: 16
+ Logic: 2.031ns(68.801%), Route: 0.921ns(31.199%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -14556,42 +16216,42 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 11.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 12.537 zoom_clk
+ net (fanout=2) 0.603 12.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 14.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 14.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.005 16.764 ntclkbufg_0
- CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/CLK
- clock pessimism 0.417 17.181
- clock uncertainty -0.150 17.031
+ net (fanout=5464) 0.895 16.654 ntclkbufg_0
+ CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK
+ clock pessimism 0.428 17.082
+ clock uncertainty -0.150 16.932
- Recovery time 0.000 17.031
+ Recovery time 0.000 16.932
- Data required time 17.031
+ Data required time 16.932
----------------------------------------------------------------------------------------------------
- Data required time 17.031
- Data arrival time 10.261
+ Data required time 16.932
+ Data arrival time 10.053
----------------------------------------------------------------------------------------------------
- Slack (MET) 6.770
+ Slack (MET) 6.879
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS
Path Group : ddrphy_clkin
Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.764
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 6.654
Launch Clock Delay : 7.101
- Clock Pessimism Removal : 0.417
+ Clock Pessimism Removal : 0.428
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -14604,59 +16264,57 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-
- CLMA_70_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 1.016 8.340 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_10_224/RSCO td 0.113 8.453 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.453 ntR1395
- CLMA_10_228/RSCO td 0.113 8.566 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.566 ntR1394
- CLMA_10_232/RSCO td 0.113 8.679 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.679 ntR1393
- CLMA_10_236/RSCO td 0.113 8.792 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 8.792 ntR1392
- CLMA_10_240/RSCO td 0.113 8.905 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 8.905 ntR1391
- CLMA_10_244/RSCO td 0.113 9.018 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.018 ntR1390
- CLMA_10_248/RSCO td 0.113 9.131 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 9.131 ntR1389
- CLMA_10_252/RSCO td 0.113 9.244 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT
- net (fanout=4) 0.000 9.244 ntR1388
- CLMA_10_256/RSCO td 0.113 9.357 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.357 ntR1387
- CLMA_10_260/RSCO td 0.113 9.470 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.470 ntR1386
- CLMA_10_264/RSCO td 0.113 9.583 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 9.583 ntR1385
- CLMA_10_268/RSCO td 0.113 9.696 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT
- net (fanout=3) 0.000 9.696 ntR1384
- CLMA_10_272/RSCO td 0.113 9.809 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT
- net (fanout=2) 0.000 9.809 ntR1383
- CLMA_10_276/RSCO td 0.113 9.922 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT
- net (fanout=2) 0.000 9.922 ntR1382
- CLMA_10_280/RSCO td 0.113 10.035 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT
- net (fanout=4) 0.000 10.035 ntR1381
- CLMA_10_284/RSCO td 0.113 10.148 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 10.148 ntR1380
- CLMA_10_288/RSCO td 0.113 10.261 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 10.261 ntR1379
- CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS
-
- Data arrival time 10.261 Logic Levels: 17
- Logic: 2.144ns(67.848%), Route: 1.016ns(32.152%)
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+
+ CLMA_46_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 0.921 8.245 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_34_148/RSCO td 0.113 8.358 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.358 ntR882
+ CLMA_34_152/RSCO td 0.113 8.471 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.471 ntR881
+ CLMA_34_156/RSCO td 0.113 8.584 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.584 ntR880
+ CLMA_34_160/RSCO td 0.113 8.697 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 8.697 ntR879
+ CLMA_34_164/RSCO td 0.113 8.810 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=3) 0.000 8.810 ntR878
+ CLMA_34_168/RSCO td 0.113 8.923 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 8.923 ntR877
+ CLMA_34_172/RSCO td 0.113 9.036 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 9.036 ntR876
+ CLMA_34_176/RSCO td 0.113 9.149 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 9.149 ntR875
+ CLMA_34_180/RSCO td 0.113 9.262 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 9.262 ntR874
+ CLMA_34_184/RSCO td 0.113 9.375 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 9.375 ntR873
+ CLMA_34_192/RSCO td 0.113 9.488 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 9.488 ntR872
+ CLMA_34_196/RSCO td 0.113 9.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=1) 0.000 9.601 ntR871
+ CLMA_34_200/RSCO td 0.113 9.714 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT
+ net (fanout=6) 0.000 9.714 ntR870
+ CLMA_34_204/RSCO td 0.113 9.827 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 9.827 ntR869
+ CLMA_34_208/RSCO td 0.113 9.940 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 9.940 ntR868
+ CLMA_34_212/RSCO td 0.113 10.053 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 10.053 ntR867
+ CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS
+
+ Data arrival time 10.053 Logic Levels: 16
+ Logic: 2.031ns(68.801%), Route: 0.921ns(31.199%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -14667,42 +16325,42 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 11.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 12.537 zoom_clk
+ net (fanout=2) 0.603 12.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 14.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 14.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.005 16.764 ntclkbufg_0
- CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/CLK
- clock pessimism 0.417 17.181
- clock uncertainty -0.150 17.031
+ net (fanout=5464) 0.895 16.654 ntclkbufg_0
+ CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/CLK
+ clock pessimism 0.428 17.082
+ clock uncertainty -0.150 16.932
- Recovery time 0.000 17.031
+ Recovery time 0.000 16.932
- Data required time 17.031
+ Data required time 16.932
----------------------------------------------------------------------------------------------------
- Data required time 17.031
- Data arrival time 10.261
+ Data required time 16.932
+ Data arrival time 10.053
----------------------------------------------------------------------------------------------------
- Slack (MET) 6.770
+ Slack (MET) 6.879
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS
Path Group : ddrphy_clkin
Path Type : max (fast corner)
Path Class : async timing path
-Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
- Capture Clock Delay : 6.764
+Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal)
+ Capture Clock Delay : 6.654
Launch Clock Delay : 7.101
- Clock Pessimism Removal : 0.417
+ Clock Pessimism Removal : 0.428
Location Delay Type Incr Path Logical Resource
----------------------------------------------------------------------------------------------------
@@ -14715,59 +16373,57 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-
- CLMA_70_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 1.016 8.340 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_10_224/RSCO td 0.113 8.453 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.453 ntR1395
- CLMA_10_228/RSCO td 0.113 8.566 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.566 ntR1394
- CLMA_10_232/RSCO td 0.113 8.679 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 8.679 ntR1393
- CLMA_10_236/RSCO td 0.113 8.792 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 8.792 ntR1392
- CLMA_10_240/RSCO td 0.113 8.905 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 8.905 ntR1391
- CLMA_10_244/RSCO td 0.113 9.018 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.018 ntR1390
- CLMA_10_248/RSCO td 0.113 9.131 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 9.131 ntR1389
- CLMA_10_252/RSCO td 0.113 9.244 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT
- net (fanout=4) 0.000 9.244 ntR1388
- CLMA_10_256/RSCO td 0.113 9.357 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.357 ntR1387
- CLMA_10_260/RSCO td 0.113 9.470 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=2) 0.000 9.470 ntR1386
- CLMA_10_264/RSCO td 0.113 9.583 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT
- net (fanout=3) 0.000 9.583 ntR1385
- CLMA_10_268/RSCO td 0.113 9.696 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT
- net (fanout=3) 0.000 9.696 ntR1384
- CLMA_10_272/RSCO td 0.113 9.809 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT
- net (fanout=2) 0.000 9.809 ntR1383
- CLMA_10_276/RSCO td 0.113 9.922 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT
- net (fanout=2) 0.000 9.922 ntR1382
- CLMA_10_280/RSCO td 0.113 10.035 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT
- net (fanout=4) 0.000 10.035 ntR1381
- CLMA_10_284/RSCO td 0.113 10.148 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=4) 0.000 10.148 ntR1380
- CLMA_10_288/RSCO td 0.113 10.261 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT
- net (fanout=6) 0.000 10.261 ntR1379
- CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS
-
- Data arrival time 10.261 Logic Levels: 17
- Logic: 2.144ns(67.848%), Route: 1.016ns(32.152%)
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+
+ CLMA_46_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 0.921 8.245 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_34_148/RSCO td 0.113 8.358 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.358 ntR882
+ CLMA_34_152/RSCO td 0.113 8.471 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.471 ntR881
+ CLMA_34_156/RSCO td 0.113 8.584 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=4) 0.000 8.584 ntR880
+ CLMA_34_160/RSCO td 0.113 8.697 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 8.697 ntR879
+ CLMA_34_164/RSCO td 0.113 8.810 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=3) 0.000 8.810 ntR878
+ CLMA_34_168/RSCO td 0.113 8.923 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=6) 0.000 8.923 ntR877
+ CLMA_34_172/RSCO td 0.113 9.036 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 9.036 ntR876
+ CLMA_34_176/RSCO td 0.113 9.149 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT
+ net (fanout=2) 0.000 9.149 ntR875
+ CLMA_34_180/RSCO td 0.113 9.262 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 9.262 ntR874
+ CLMA_34_184/RSCO td 0.113 9.375 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 9.375 ntR873
+ CLMA_34_192/RSCO td 0.113 9.488 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=2) 0.000 9.488 ntR872
+ CLMA_34_196/RSCO td 0.113 9.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT
+ net (fanout=1) 0.000 9.601 ntR871
+ CLMA_34_200/RSCO td 0.113 9.714 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT
+ net (fanout=6) 0.000 9.714 ntR870
+ CLMA_34_204/RSCO td 0.113 9.827 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 9.827 ntR869
+ CLMA_34_208/RSCO td 0.113 9.940 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 9.940 ntR868
+ CLMA_34_212/RSCO td 0.113 10.053 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT
+ net (fanout=5) 0.000 10.053 ntR867
+ CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS
+
+ Data arrival time 10.053 Logic Levels: 16
+ Logic: 2.031ns(68.801%), Route: 0.921ns(31.199%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 10.000 10.000 r
@@ -14778,35 +16434,35 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 11.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 12.537 zoom_clk
+ net (fanout=2) 0.603 12.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 14.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 14.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT
- net (fanout=5464) 1.005 16.764 ntclkbufg_0
- CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/CLK
- clock pessimism 0.417 17.181
- clock uncertainty -0.150 17.031
+ net (fanout=5464) 0.895 16.654 ntclkbufg_0
+ CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/CLK
+ clock pessimism 0.428 17.082
+ clock uncertainty -0.150 16.932
- Recovery time 0.000 17.031
+ Recovery time 0.000 16.932
- Data required time 17.031
+ Data required time 16.932
----------------------------------------------------------------------------------------------------
- Data required time 17.031
- Data arrival time 10.261
+ Data required time 16.932
+ Data arrival time 10.053
----------------------------------------------------------------------------------------------------
- Slack (MET) 6.770
+ Slack (MET) 6.879
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS
Path Group : ddrphy_clkin
Path Type : min (fast corner)
Path Class : async timing path
@@ -14826,27 +16482,27 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.895 6.654 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- CLMA_70_192/Q0 tco 0.182 6.836 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 0.300 7.136 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_66_212/RSCO td 0.092 7.228 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 7.228 ntR1484
- CLMA_66_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS
+ CLMA_46_192/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 0.237 7.070 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_38_192/RSCO td 0.085 7.155 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT
+ net (fanout=4) 0.000 7.155 ntR984
+ CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS
- Data arrival time 7.228 Logic Levels: 1
- Logic: 0.274ns(47.735%), Route: 0.300ns(52.265%)
+ Data arrival time 7.155 Logic Levels: 1
+ Logic: 0.264ns(52.695%), Route: 0.237ns(47.305%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -14857,18 +16513,18 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/CLK
+ CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/CLK
clock pessimism -0.428 6.673
clock uncertainty 0.000 6.673
@@ -14877,15 +16533,15 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 6.673
----------------------------------------------------------------------------------------------------
Data required time 6.673
- Data arrival time 7.228
+ Data arrival time 7.155
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.555
+ Slack (MET) 0.482
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS
Path Group : ddrphy_clkin
Path Type : min (fast corner)
Path Class : async timing path
@@ -14905,27 +16561,27 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.895 6.654 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- CLMA_70_192/Q0 tco 0.182 6.836 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 0.300 7.136 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_66_212/RSCO td 0.092 7.228 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 7.228 ntR1484
- CLMA_66_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS
+ CLMA_46_192/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 0.237 7.070 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_38_192/RSCO td 0.085 7.155 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT
+ net (fanout=4) 0.000 7.155 ntR984
+ CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS
- Data arrival time 7.228 Logic Levels: 1
- Logic: 0.274ns(47.735%), Route: 0.300ns(52.265%)
+ Data arrival time 7.155 Logic Levels: 1
+ Logic: 0.264ns(52.695%), Route: 0.237ns(47.305%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -14936,18 +16592,18 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/CLK
+ CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/CLK
clock pessimism -0.428 6.673
clock uncertainty 0.000 6.673
@@ -14956,15 +16612,15 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 6.673
----------------------------------------------------------------------------------------------------
Data required time 6.673
- Data arrival time 7.228
+ Data arrival time 7.155
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.555
+ Slack (MET) 0.482
====================================================================================================
====================================================================================================
Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
-Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS
+Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS
Path Group : ddrphy_clkin
Path Type : min (fast corner)
Path Class : async timing path
@@ -14984,27 +16640,27 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.463 1.860 _N69
PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.603 2.537 zoom_clk
+ net (fanout=2) 0.603 2.537 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.669 4.276 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.476 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.895 6.654 ntclkbufg_0
- CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- CLMA_70_192/Q0 tco 0.182 6.836 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
- net (fanout=619) 0.300 7.136 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
- CLMA_66_212/RSCO td 0.092 7.228 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT
- net (fanout=4) 0.000 7.228 ntR1484
- CLMA_66_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS
+ CLMA_46_192/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q
+ net (fanout=729) 0.237 7.070 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n
+ CLMA_38_192/RSCO td 0.085 7.155 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT
+ net (fanout=4) 0.000 7.155 ntR984
+ CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS
- Data arrival time 7.228 Logic Levels: 1
- Logic: 0.274ns(47.735%), Route: 0.300ns(52.265%)
+ Data arrival time 7.155 Logic Levels: 1
+ Logic: 0.264ns(52.695%), Route: 0.237ns(47.305%)
----------------------------------------------------------------------------------------------------
Clock ddrphy_clkin (rising edge) 0.000 0.000 r
@@ -15015,18 +16671,18 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/CLK
+ CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/CLK
clock pessimism -0.428 6.673
clock uncertainty 0.000 6.673
@@ -15035,14 +16691,14 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim
Data required time 6.673
----------------------------------------------------------------------------------------------------
Data required time 6.673
- Data arrival time 7.228
+ Data arrival time 7.155
----------------------------------------------------------------------------------------------------
- Slack (MET) 0.555
+ Slack (MET) 0.482
====================================================================================================
====================================================================================================
-Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/CLK
+Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK
Endpoint : mem_rst_n (port)
Path Group : **default**
Path Type : max (fast corner)
@@ -15059,37 +16715,37 @@ Path Class : combinational timing path
IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK
net (fanout=1) 0.478 2.114 _N69
PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1
- net (fanout=2) 0.614 2.807 zoom_clk
+ net (fanout=2) 0.614 2.807 ddr_clk
USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT
- net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
+ net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin
PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL
net (fanout=3) 0.682 4.602 clkout0_wl_0
- IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT
+ IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT
net (fanout=1) 0.000 4.870 ntclkgate_0
IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV
net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk
USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT
net (fanout=5464) 0.925 7.101 ntclkbufg_0
- CLMS_46_173/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/CLK
-
- CLMS_46_173/Q1 tco 0.223 7.324 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/Q
- net (fanout=575) 1.703 9.027 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done
- CLMS_18_317/Y0 td 0.150 9.177 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm/Z
- net (fanout=1) 0.772 9.949 nt_mem_rst_n
- IOL_7_369/DO td 0.106 10.055 f mem_rst_n_obuf/opit_1/O
- net (fanout=1) 0.000 10.055 mem_rst_n_obuf/ntO
- IOBS_LR_0_368/PAD td 3.229 13.284 f mem_rst_n_obuf/opit_0/O
- net (fanout=1) 0.096 13.380 mem_rst_n
+ CLMA_46_156/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK
+
+ CLMA_46_156/Q0 tco 0.221 7.322 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/Q
+ net (fanout=1) 0.497 7.819 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_rst
+ CLMS_34_173/Y3 td 0.151 7.970 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm/Z
+ net (fanout=1) 1.679 9.649 nt_mem_rst_n
+ IOL_7_369/DO td 0.106 9.755 f mem_rst_n_obuf/opit_1/O
+ net (fanout=1) 0.000 9.755 mem_rst_n_obuf/ntO
+ IOBS_LR_0_368/PAD td 3.229 12.984 f mem_rst_n_obuf/opit_0/O
+ net (fanout=1) 0.096 13.080 mem_rst_n
C1 f mem_rst_n (port)
- Data arrival time 13.380 Logic Levels: 3
- Logic: 3.708ns(59.054%), Route: 2.571ns(40.946%)
+ Data arrival time 13.080 Logic Levels: 3
+ Logic: 3.707ns(62.000%), Route: 2.272ns(38.000%)
====================================================================================================
====================================================================================================
-Startpoint : param_manager_inst/index[1]/opit_0_L5Q_perm/CLK
-Endpoint : led[2] (port)
+Startpoint : param_manager_inst/index[0]/opit_0_L5Q_perm/CLK
+Endpoint : led[1] (port)
Path Group : **default**
Path Type : max (fast corner)
Path Class : combinational timing path
@@ -15107,25 +16763,25 @@ Path Class : combinational timing path
IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.925 6.734 gmii_clk
- CLMA_194_168/CLK r param_manager_inst/index[1]/opit_0_L5Q_perm/CLK
-
- CLMA_194_168/Q3 tco 0.220 6.954 f param_manager_inst/index[1]/opit_0_L5Q_perm/Q
- net (fanout=19) 2.648 9.602 nt_led[2]
- IOL_19_373/DO td 0.106 9.708 f led_obuf[2]/opit_1/O
- net (fanout=1) 0.000 9.708 led_obuf[2]/ntO
- IOBS_TB_17_376/PAD td 3.238 12.946 f led_obuf[2]/opit_0/O
- net (fanout=1) 0.107 13.053 led[2]
- A2 f led[2] (port)
+ net (fanout=1862) 0.925 6.734 gmii_clk
+ CLMA_210_205/CLK r param_manager_inst/index[0]/opit_0_L5Q_perm/CLK
- Data arrival time 13.053 Logic Levels: 2
- Logic: 3.564ns(56.401%), Route: 2.755ns(43.599%)
+ CLMA_210_205/Q0 tco 0.221 6.955 f param_manager_inst/index[0]/opit_0_L5Q_perm/Q
+ net (fanout=20) 2.671 9.626 nt_led[1]
+ IOL_19_374/DO td 0.106 9.732 f led_obuf[1]/opit_1/O
+ net (fanout=1) 0.000 9.732 led_obuf[1]/ntO
+ IOBD_16_376/PAD td 3.238 12.970 f led_obuf[1]/opit_0/O
+ net (fanout=1) 0.109 13.079 led[1]
+ B2 f led[1] (port)
+
+ Data arrival time 13.079 Logic Levels: 2
+ Logic: 3.565ns(56.186%), Route: 2.780ns(43.814%)
====================================================================================================
====================================================================================================
-Startpoint : param_manager_inst/index[3]/opit_0_L5Q_perm/CLK
-Endpoint : led[4] (port)
+Startpoint : param_manager_inst/index[1]/opit_0_L5Q_perm/CLK
+Endpoint : led[2] (port)
Path Group : **default**
Path Type : max (fast corner)
Path Class : combinational timing path
@@ -15143,19 +16799,19 @@ Path Class : combinational timing path
IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT
net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf
USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT
- net (fanout=1861) 0.925 6.734 gmii_clk
- CLMA_194_168/CLK r param_manager_inst/index[3]/opit_0_L5Q_perm/CLK
-
- CLMA_194_168/Q1 tco 0.223 6.957 f param_manager_inst/index[3]/opit_0_L5Q_perm/Q
- net (fanout=18) 2.603 9.560 nt_led[4]
- IOL_35_373/DO td 0.106 9.666 f led_obuf[4]/opit_1/O
- net (fanout=1) 0.000 9.666 led_obuf[4]/ntO
- IOBS_TB_33_376/PAD td 3.238 12.904 f led_obuf[4]/opit_0/O
- net (fanout=1) 0.087 12.991 led[4]
- A3 f led[4] (port)
+ net (fanout=1862) 0.925 6.734 gmii_clk
+ CLMA_210_205/CLK r param_manager_inst/index[1]/opit_0_L5Q_perm/CLK
+
+ CLMA_210_205/Q3 tco 0.220 6.954 f param_manager_inst/index[1]/opit_0_L5Q_perm/Q
+ net (fanout=19) 2.580 9.534 nt_led[2]
+ IOL_19_373/DO td 0.106 9.640 f led_obuf[2]/opit_1/O
+ net (fanout=1) 0.000 9.640 led_obuf[2]/ntO
+ IOBS_TB_17_376/PAD td 3.238 12.878 f led_obuf[2]/opit_0/O
+ net (fanout=1) 0.107 12.985 led[2]
+ A2 f led[2] (port)
- Data arrival time 12.991 Logic Levels: 2
- Logic: 3.567ns(57.008%), Route: 2.690ns(42.992%)
+ Data arrival time 12.985 Logic Levels: 2
+ Logic: 3.564ns(57.015%), Route: 2.687ns(42.985%)
====================================================================================================
====================================================================================================
@@ -15228,35 +16884,35 @@ Path Class : combinational timing path
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 5.232 5.950 0.718 Low Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 5.232 5.950 0.718 High Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 5.454 5.950 0.496 High Pulse Width CLMS_146_9/CLK u_ov5640/cmos1_8_16bit/de_in0/opit_0/CLK
+ 5.232 5.950 0.718 Low Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 5.232 5.950 0.718 High Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 5.454 5.950 0.496 Low Pulse Width CLMS_134_25/CLK u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm/CLK
====================================================================================================
{cmos2_pclk} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 5.232 5.950 0.718 Low Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 5.232 5.950 0.718 High Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 5.454 5.950 0.496 Low Pulse Width CLMS_150_41/CLK u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q/CLK
+ 5.232 5.950 0.718 Low Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 5.232 5.950 0.718 High Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 5.454 5.950 0.496 High Pulse Width CLMS_74_17/CLK u_ov5640/cmos2_8_16bit/de_in0/opit_0/CLK
====================================================================================================
{hdmi_in_clk} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 2.615 3.333 0.718 Low Pulse Width DRM_82_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 2.615 3.333 0.718 High Pulse Width DRM_82_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
- 2.615 3.333 0.718 High Pulse Width DRM_54_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 2.615 3.333 0.718 Low Pulse Width DRM_82_128/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 2.615 3.333 0.718 High Pulse Width DRM_82_128/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0]
+ 2.615 3.333 0.718 Low Pulse Width DRM_82_88/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0]
====================================================================================================
{eth_rxc} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 2.787 4.000 1.213 High Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK
2.787 4.000 1.213 Low Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK
+ 2.787 4.000 1.213 High Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK
2.787 4.000 1.213 Low Pulse Width IOL_311_374/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft1/opit_1_IOL/SYSCLK
====================================================================================================
@@ -15264,63 +16920,72 @@ Path Class : combinational timing path
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 9.090 10.000 0.910 High Pulse Width APM_106_116/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK
- 9.090 10.000 0.910 Low Pulse Width APM_106_116/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK
- 9.090 10.000 0.910 High Pulse Width APM_106_104/CLK u_rotate_image/u_rotate_mult1/N2/gopapm/CLK
+ 9.090 10.000 0.910 Low Pulse Width APM_206_228/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK
+ 9.090 10.000 0.910 High Pulse Width APM_206_228/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK
+ 9.090 10.000 0.910 High Pulse Width APM_206_216/CLK u_rotate_image/u_rotate_mult1/N2/gopapm/CLK
====================================================================================================
{clk_200m} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 1.590 2.500 0.910 Low Pulse Width APM_206_228/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK
- 1.590 2.500 0.910 High Pulse Width APM_206_228/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK
- 1.590 2.500 0.910 Low Pulse Width APM_206_140/CLK u_zoom_image/mult_fra0_0/N2/gopapm/CLK
+ 2.004 2.500 0.496 Low Pulse Width CLMS_34_181/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK
+ 2.004 2.500 0.496 High Pulse Width CLMS_34_181/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK
+ 2.004 2.500 0.496 High Pulse Width CLMS_34_193/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm/CLK
====================================================================================================
{clk_25m} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 19.664 20.000 0.336 High Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
- 19.664 20.000 0.336 Low Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
- 19.664 20.000 0.336 High Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
+ 19.504 20.000 0.496 High Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+ 19.504 20.000 0.496 Low Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+ 19.504 20.000 0.496 High Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK
====================================================================================================
{clk_10m} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 49.282 50.000 0.718 Low Pulse Width DRM_234_108/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
- 49.282 50.000 0.718 High Pulse Width DRM_234_108/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
- 49.282 50.000 0.718 Low Pulse Width DRM_234_108/CLKB[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0]
+ 49.282 50.000 0.718 Low Pulse Width DRM_234_316/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
+ 49.282 50.000 0.718 High Pulse Width DRM_234_316/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0]
+ 49.282 50.000 0.718 Low Pulse Width DRM_234_316/CLKB[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0]
+====================================================================================================
+
+{clk_1080p60Hz} Minimum Pulse Width :
+****************************************************************************************************
+ Slack Actual Width Require Width Type Location Pin
+----------------------------------------------------------------------------------------------------
+ 2.458 3.368 0.910 High Pulse Width APM_206_28/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK
+ 2.458 3.368 0.910 Low Pulse Width APM_206_28/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK
+ 2.458 3.368 0.910 High Pulse Width APM_206_264/CLK u_zoom_image/mult_fra0_0/N2/gopapm/CLK
====================================================================================================
{clk_720p60Hz} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 5.826 6.736 0.910 High Pulse Width APM_258_140/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK
- 5.826 6.736 0.910 High Pulse Width APM_258_128/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm/CLK
- 5.827 6.737 0.910 Low Pulse Width APM_258_140/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK
+ 5.826 6.736 0.910 High Pulse Width APM_258_216/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK
+ 5.826 6.736 0.910 High Pulse Width APM_258_204/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm/CLK
+ 5.827 6.737 0.910 Low Pulse Width APM_258_216/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK
====================================================================================================
{clk_20k} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 24999.282 25000.000 0.718 Low Pulse Width DRM_178_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
- 24999.282 25000.000 0.718 High Pulse Width DRM_178_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
- 24999.282 25000.000 0.718 Low Pulse Width DRM_178_4/CLKB[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
+ 24999.282 25000.000 0.718 Low Pulse Width DRM_142_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
+ 24999.282 25000.000 0.718 High Pulse Width DRM_142_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0]
+ 24999.282 25000.000 0.718 Low Pulse Width DRM_142_4/CLKB[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
====================================================================================================
{ddrphy_clkin} Minimum Pulse Width :
****************************************************************************************************
Slack Actual Width Require Width Type Location Pin
----------------------------------------------------------------------------------------------------
- 3.480 5.000 1.520 High Pulse Width CLMS_38_109/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK
- 3.480 5.000 1.520 Low Pulse Width CLMS_38_109/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK
- 3.480 5.000 1.520 High Pulse Width CLMS_34_113/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK
+ 3.480 5.000 1.520 Low Pulse Width CLMS_38_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK
+ 3.480 5.000 1.520 High Pulse Width CLMS_38_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK
+ 3.480 5.000 1.520 Low Pulse Width CLMS_42_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK
====================================================================================================
{ioclk0} Minimum Pulse Width :
@@ -15373,6 +17038,6 @@ Inputs and Outputs :
Flow Command: report_timing
Peak memory: 1,325 MB
-Total CPU time to report_timing completion : 0h:0m:25s
-Process Total CPU time to report_timing completion : 0h:0m:32s
-Total real time to report_timing completion : 0h:0m:26s
+Total CPU time to report_timing completion : 0h:0m:26s
+Process Total CPU time to report_timing completion : 0h:0m:35s
+Total real time to report_timing completion : 0h:0m:28s
diff --git a/project/report_timing/multimedia_video_processor_rtp.adf b/project/report_timing/multimedia_video_processor_rtp.adf
index e9f1e03..1104ed2 100644
Binary files a/project/report_timing/multimedia_video_processor_rtp.adf and b/project/report_timing/multimedia_video_processor_rtp.adf differ
diff --git a/project/report_timing/rtr.db b/project/report_timing/rtr.db
index d0b002a..1ecc4d2 100644
--- a/project/report_timing/rtr.db
+++ b/project/report_timing/rtr.db
@@ -892,7 +892,7 @@
50.000MHz
0.000
10.000
- 2517
+ 2516
0
clk
{ u_sys_pll/u_pll_e3/goppll/CLKOUT0 }
@@ -904,7 +904,7 @@
200.000MHz
0.000
2.500
- 825
+ 75
5
clk
{ u_sys_pll/u_pll_e3/goppll/CLKOUT1 }
@@ -1024,7 +1024,7 @@
148.438MHz
0.000
3.368
- 0
+ 750
0
clk
{ U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 }
@@ -1085,13 +1085,13 @@
125.000MHz
0.000
4.000
- 1861
+ 1862
1
{ eth_rxc }
-
+
-
+
@@ -1988,82 +2058,90 @@
Failing Endpoints
Total Endpoints
+
-
-
- -0.788
- 0
- 3
- u_zoom_image/mult_fra0_0/N2/gopapm/CLK
- u_zoom_image/mult_image_r0_0/N2/gopapm/X[0]
-
- clk_200m
- clk_200m
- rise-rise
- 0.067
- 5.867
- 5.495
- 0.439
- 5.000
- 3.462
- 1.067 (30.8%)
- 2.395 (69.2%)
-
- Path #2: setup slack is -0.788(VIOLATED)
-
-
-
-
-
-
-
-
-
-
-
- -0.740
- 0
- 3
- u_zoom_image/mult_fra0_0/N2/gopapm/CLK
- u_zoom_image/mult_image_r0_0/N2/gopapm/X[3]
-
- clk_200m
- clk_200m
- rise-rise
- 0.067
- 5.867
- 5.495
- 0.439
- 5.000
- 3.414
- 1.067 (31.3%)
- 2.347 (68.7%)
-
- Path #3: setup slack is -0.740(VIOLATED)
-
-
-
-
-
-
-
-
-
-
-
- 0.348
- 7
- 40
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
-
- ddrphy_clkin
- ddrphy_clkin
- rise-rise
- -0.054
- 11.394
- 10.665
- 0.675
- 10.000
- 9.071
- 3.183 (35.1%)
- 5.888 (64.9%)
-
- Path #4: setup slack is 0.348(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.411
- 7
- 40
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
-
- ddrphy_clkin
- ddrphy_clkin
- rise-rise
- 0.067
- 11.394
- 10.786
- 0.675
- 10.000
- 9.129
- 3.189 (34.9%)
- 5.940 (65.1%)
-
- Path #5: setup slack is 0.411(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.418
- 7
- 40
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0
-
- ddrphy_clkin
- ddrphy_clkin
- rise-rise
- -0.054
- 11.394
- 10.665
- 0.675
- 10.000
- 8.981
- 3.189 (35.5%)
- 5.792 (64.5%)
-
- Path #6: setup slack is 0.418(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.077
- 7
- 18
- udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
- udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE
-
- eth_rxc
- eth_rxc
- rise-rise
- -0.036
- 10.030
- 8.446
- 1.548
- 8.000
- 6.020
- 2.738 (45.5%)
- 3.282 (54.5%)
-
- Path #7: setup slack is 1.077(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.077
- 7
- 18
- udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
- udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE
-
- eth_rxc
- eth_rxc
- rise-rise
- -0.036
- 10.030
- 8.446
- 1.548
- 8.000
- 6.020
- 2.738 (45.5%)
- 3.282 (54.5%)
-
- Path #8: setup slack is 1.077(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.077
- 7
- 18
- udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK
- udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE
-
- eth_rxc
- eth_rxc
- rise-rise
- -0.036
- 10.030
- 8.446
- 1.548
- 8.000
- 6.020
- 2.738 (45.5%)
- 3.282 (54.5%)
-
- Path #9: setup slack is 1.077(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.130
- 4
- 4
- u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
- u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4
-
- hdmi_in_clk
- hdmi_in_clk
- rise-rise
- -0.036
- 6.435
- 5.951
- 0.448
- 6.666
- 5.127
- 2.593 (50.6%)
- 2.534 (49.4%)
-
- Path #10: setup slack is 1.130(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.692
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
-
- ioclk1
- ioclk1
- rise-rise
- 0.006
- 7.692
- 7.062
- 0.636
- 2.500
- 0.528
- 0.528 (100.0%)
- 0.000 (0.0%)
-
- Path #11: setup slack is 1.692(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.692
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
-
- ioclk1
- ioclk1
- rise-rise
- 0.006
- 7.692
- 7.062
- 0.636
- 2.500
- 0.528
- 0.528 (100.0%)
- 0.000 (0.0%)
-
- Path #12: setup slack is 1.692(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.692
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
-
- ioclk1
- ioclk1
- rise-rise
- 0.006
- 7.692
- 7.062
- 0.636
- 2.500
- 0.528
- 0.528 (100.0%)
- 0.000 (0.0%)
-
- Path #13: setup slack is 1.692(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.692
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
-
- ioclk0
- ioclk0
- rise-rise
- 0.006
- 7.692
- 7.062
- 0.636
- 2.500
- 0.528
- 0.528 (100.0%)
- 0.000 (0.0%)
-
- Path #14: setup slack is 1.692(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.692
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
-
- ioclk0
- ioclk0
- rise-rise
- 0.006
- 7.692
- 7.062
- 0.636
- 2.500
- 0.528
- 0.528 (100.0%)
- 0.000 (0.0%)
-
- Path #15: setup slack is 1.692(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.692
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
-
- ioclk0
- ioclk0
- rise-rise
- 0.006
- 7.692
- 7.062
- 0.636
- 2.500
- 0.528
- 0.528 (100.0%)
- 0.000 (0.0%)
-
- Path #16: setup slack is 1.692(MET)
-
-
-
-
-
-
-
-
-
-
-
- 2.921
- 3
- 4
- u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
- u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0
-
- hdmi_in_clk
- hdmi_in_clk
- rise-rise
- -0.036
- 6.435
- 5.951
- 0.448
- 6.666
- 3.263
- 1.308 (40.1%)
- 1.955 (59.9%)
-
- Path #17: setup slack is 2.921(MET)
-
-
-
-
-
-
-
-
-
-
-
- 2.994
- 3
- 4
- u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
- u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4
-
- hdmi_in_clk
- hdmi_in_clk
- rise-rise
- -0.036
- 6.435
- 5.951
- 0.448
- 6.666
- 3.263
- 1.308 (40.1%)
- 1.955 (59.9%)
-
- Path #18: setup slack is 2.994(MET)
-
-
-
-
-
-
-
-
-
-
-
- 4.291
- 2
- 1
- cmos2_data[7]
- u_ov5640/cmos2_d_d0[7]/opit_0/D
-
- cmos2_pclk
- cmos2_pclk
- rise-rise
- 5.551
- 0.000
- 5.551
- 0.000
- 11.900
- 11.831
- 2.292 (19.4%)
- 9.539 (80.6%)
-
- Path #19: setup slack is 4.291(MET)
-
-
-
-
-
-
-
-
-
-
-
- 4.870
- 2
- 1
- cmos2_data[2]
- u_ov5640/cmos2_d_d0[2]/opit_0/D
-
- cmos2_pclk
- cmos2_pclk
- rise-rise
- 5.551
- 0.000
- 5.551
- 0.000
- 11.900
- 11.252
- 2.292 (20.4%)
- 8.960 (79.6%)
-
- Path #20: setup slack is 4.870(MET)
-
-
-
-
-
-
-
-
-
-
-
- 4.900
- 2
- 1
- cmos2_data[5]
- u_ov5640/cmos2_d_d0[5]/opit_0/D
-
- cmos2_pclk
- cmos2_pclk
- rise-rise
- 5.551
- 0.000
- 5.551
- 0.000
- 11.900
- 11.213
- 1.640 (14.6%)
- 9.573 (85.4%)
-
- Path #21: setup slack is 4.900(MET)
-
-
-
-
-
-
-
-
-
-
-
- 5.450
- 9
- 6
- u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
- udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- -0.036
- 9.434
- 8.831
- 0.567
- 13.473
- 7.090
- 2.943 (41.5%)
- 4.147 (58.5%)
-
- Path #22: setup slack is 5.450(MET)
-
-
-
-
-
-
-
-
-
-
-
- 5.450
- 9
- 6
- u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
- udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- -0.036
- 9.434
- 8.831
- 0.567
- 13.473
- 7.090
- 2.943 (41.5%)
- 4.147 (58.5%)
-
- Path #23: setup slack is 5.450(MET)
-
-
-
-
-
-
-
-
-
-
-
- 5.450
- 9
- 6
- u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK
- udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- -0.036
- 9.434
- 8.831
- 0.567
- 13.473
- 7.090
- 2.943 (41.5%)
- 4.147 (58.5%)
-
- Path #24: setup slack is 5.450(MET)
-
-
-
-
-
-
-
-
-
-
-
- 5.696
- 3
- 1
- cmos1_data[5]
- u_ov5640/cmos1_d_d0[5]/opit_0/D
-
- cmos1_pclk
- cmos1_pclk
- rise-rise
- 5.188
- 0.000
- 5.188
- 0.000
- 11.900
- 10.063
- 2.441 (24.3%)
- 7.622 (75.7%)
-
- Path #25: setup slack is 5.696(MET)
-
-
-
-
-
-
-
-
-
-
-
- 5.704
- 2
- 1
- cmos1_data[4]
- u_ov5640/cmos1_d_d0[4]/opit_0/D
-
- cmos1_pclk
- cmos1_pclk
- rise-rise
- 5.188
- 0.000
- 5.188
- 0.000
- 11.900
- 10.163
- 2.292 (22.6%)
- 7.871 (77.4%)
-
- Path #26: setup slack is 5.704(MET)
-
-
-
-
-
-
-
-
-
-
-
- 5.727
- 2
- 1
- cmos1_href
- u_ov5640/cmos1_href_d0/opit_0/D
-
- cmos1_pclk
- cmos1_pclk
- rise-rise
- 5.188
- 0.000
- 5.188
- 0.000
- 11.900
- 10.140
- 1.494 (14.7%)
- 8.646 (85.3%)
-
- Path #27: setup slack is 5.727(MET)
-
-
-
-
-
-
-
-
-
-
-
- 10.855
- 5
- 6
- u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
- u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
-
- clk_50m
- clk_50m
- rise-rise
- -0.093
- 5.930
- 5.378
- 0.459
- 20.000
- 8.779
- 4.536 (51.7%)
- 4.243 (48.3%)
-
- Path #28: setup slack is 10.855(MET)
-
-
-
-
-
-
-
-
-
-
-
- 11.756
- 5
- 6
- u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
- u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
-
- clk_50m
- clk_50m
- rise-rise
- -0.093
- 5.930
- 5.378
- 0.459
- 20.000
- 7.878
- 4.714 (59.8%)
- 3.164 (40.2%)
-
- Path #29: setup slack is 11.756(MET)
-
-
-
-
-
-
-
-
-
-
-
- 11.848
- 5
- 6
- u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
- u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
-
- clk_50m
- clk_50m
- rise-rise
- -0.093
- 5.930
- 5.378
- 0.459
- 20.000
- 7.552
- 4.136 (54.8%)
- 3.416 (45.2%)
-
- Path #30: setup slack is 11.848(MET)
-
-
-
-
-
-
-
-
-
-
-
- 35.419
- 4
- 13
- u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
- u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D
-
- clk_25m
- clk_25m
- rise-rise
- 0.000
- 5.877
- 5.383
- 0.494
- 40.000
- 4.352
- 2.052 (47.2%)
- 2.300 (52.8%)
-
- Path #31: setup slack is 35.419(MET)
-
-
-
-
-
-
-
-
-
-
-
- 35.435
- 4
- 13
- u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
- u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D
-
- clk_25m
- clk_25m
- rise-rise
- -0.029
- 5.877
- 5.383
- 0.465
- 40.000
- 4.307
- 2.095 (48.6%)
- 2.212 (51.4%)
-
- Path #32: setup slack is 35.435(MET)
-
-
-
-
-
-
-
-
-
-
-
- 35.450
- 3
- 13
- u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
- u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/D
-
- clk_25m
- clk_25m
- rise-rise
- -0.029
- 5.877
- 5.383
- 0.465
- 40.000
- 4.292
- 1.964 (45.8%)
- 2.328 (54.2%)
-
- Path #33: setup slack is 35.450(MET)
-
-
-
-
-
-
-
-
-
-
-
- 94.174
- 6
- 15
- ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
- ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/L4
-
- clk_10m
- clk_10m
- rise-rise
- -0.036
- 5.873
- 5.378
- 0.459
- 100.000
- 5.519
- 2.198 (39.8%)
- 3.321 (60.2%)
-
- Path #34: setup slack is 94.174(MET)
-
-
-
-
-
-
-
-
-
-
-
- 94.230
- 6
- 15
- ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
- ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CE
-
- clk_10m
- clk_10m
- rise-rise
- -0.036
- 5.873
- 5.378
- 0.459
- 100.000
- 4.967
- 1.908 (38.4%)
- 3.059 (61.6%)
-
- Path #35: setup slack is 94.230(MET)
-
-
-
-
-
-
-
-
-
-
-
- 94.230
- 6
- 15
- ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
- ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CE
-
- clk_10m
- clk_10m
- rise-rise
- -0.036
- 5.873
- 5.378
- 0.459
- 100.000
- 4.967
- 1.908 (38.4%)
- 3.059 (61.6%)
-
- Path #36: setup slack is 94.230(MET)
-
-
-
-
-
-
-
-
-
-
-
- 49995.048
- 3
- 1
- u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
- u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
-
- clk_20k
- clk_20k
- rise-rise
- -0.036
- 9.812
- 9.014
- 0.762
- 50000.000
- 4.701
- 3.229 (68.7%)
- 1.472 (31.3%)
-
- Path #37: setup slack is 49995.048(MET)
-
-
-
-
-
-
-
-
-
-
-
- 49995.178
- 3
- 1
- u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
- u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
-
- clk_20k
- clk_20k
- rise-rise
- -0.036
- 10.099
- 9.247
- 0.816
- 50000.000
- 4.571
- 3.269 (71.5%)
- 1.302 (28.5%)
-
- Path #38: setup slack is 49995.178(MET)
-
-
-
-
-
-
-
-
-
-
-
- 49995.210
- 5
- 5
- u_ov5640/coms1_reg_config/reg_index[2]/opit_0_inv_A2Q21/CLK
- u_ov5640/coms1_reg_config/reg_index[6]/opit_0_inv_A2Q21/CE
-
- clk_20k
- clk_20k
- rise-rise
- -0.029
- 10.099
- 9.247
- 0.823
- 50000.000
- 3.982
- 1.684 (42.3%)
- 2.298 (57.7%)
-
- Path #39: setup slack is 49995.210(MET)
-
-
-
-
-
-
-
-
-
-
-
-
-
- 0.162
- 0
- 7
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0
-
- ddrphy_clkin
- ddrphy_clkin
- rise-rise
- 0.036
- 10.665
- 11.394
- -0.693
- 0.000
- 0.578
- 0.222 (38.4%)
- 0.356 (61.6%)
-
- Path #2: hold slack is 0.162(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.162
- 0
- 7
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0
-
- ddrphy_clkin
- ddrphy_clkin
- rise-rise
- 0.036
- 10.665
- 11.394
- -0.693
- 0.000
- 0.578
- 0.222 (38.4%)
- 0.356 (61.6%)
-
- Path #3: hold slack is 0.162(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.182
- 0
- 3
- u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK
- u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8]
-
- clk_50m
- clk_50m
- rise-rise
- 0.088
- 5.378
- 5.925
- -0.459
- 0.000
- 0.480
- 0.224 (46.7%)
- 0.256 (53.3%)
-
- Path #4: hold slack is 0.182(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.191
- 0
- 5
- u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK
- u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0
-
- hdmi_in_clk
- hdmi_in_clk
- rise-rise
- 0.000
- 5.951
- 6.435
- -0.484
- 0.000
- 0.312
- 0.224 (71.8%)
- 0.088 (28.2%)
-
- Path #5: hold slack is 0.191(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.199
- 0
- 24
- u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
- u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0
-
- cmos1_pclk
- cmos1_pclk
- rise-rise
- 0.000
- 5.188
- 5.521
- -0.333
- 0.000
- 0.319
- 0.221 (69.3%)
- 0.098 (30.7%)
-
- Path #6: hold slack is 0.199(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.201
- 0
- 2
- u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK
- u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/L0
-
- cmos1_pclk
- cmos1_pclk
- rise-rise
- 0.000
- 5.188
- 5.521
- -0.333
- 0.000
- 0.307
- 0.222 (72.3%)
- 0.085 (27.7%)
-
- Path #7: hold slack is 0.201(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.201
- 0
- 2
- u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK
- u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/L0
-
- cmos1_pclk
- cmos1_pclk
- rise-rise
- 0.000
- 5.188
- 5.521
- -0.333
- 0.000
- 0.307
- 0.222 (72.3%)
- 0.085 (27.7%)
-
- Path #8: hold slack is 0.201(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.203
- 0
- 24
- u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK
- u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/L0
-
- hdmi_in_clk
- hdmi_in_clk
- rise-rise
- 0.000
- 5.951
- 6.435
- -0.484
- 0.000
- 0.324
- 0.224 (69.1%)
- 0.100 (30.9%)
-
- Path #9: hold slack is 0.203(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.206
- 0
- 13
- u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK
- u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/L0
-
- hdmi_in_clk
- hdmi_in_clk
- rise-rise
- 0.000
- 5.951
- 6.435
- -0.484
- 0.000
- 0.312
- 0.222 (71.2%)
- 0.090 (28.8%)
-
- Path #10: hold slack is 0.206(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.222
- 0
- 1
- u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK
- u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D
-
- clk_50m
- clk_50m
- rise-rise
- 0.030
- 5.403
- 5.899
- -0.466
- 0.000
- 0.305
- 0.221 (72.5%)
- 0.084 (27.5%)
-
- Path #11: hold slack is 0.222(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.241
- 0
- 1
- u_zoom_image/mult_image_g0/N2/gopapm/CLK
- u_zoom_image/mult_image_g1/N2/gopapm/PI[0]
-
- clk_200m
- clk_200m
- rise-rise
- 0.177
- 5.374
- 5.990
- -0.439
- 0.000
- 0.297
- 0.297 (100.0%)
- 0.000 (0.0%)
-
- Path #12: hold slack is 0.241(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.241
- 0
- 1
- u_zoom_image/mult_image_g0/N2/gopapm/CLK
- u_zoom_image/mult_image_g1/N2/gopapm/PI[1]
-
- clk_200m
- clk_200m
- rise-rise
- 0.177
- 5.374
- 5.990
- -0.439
- 0.000
- 0.297
- 0.297 (100.0%)
- 0.000 (0.0%)
-
- Path #13: hold slack is 0.241(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.241
- 0
- 1
- u_zoom_image/mult_image_g0/N2/gopapm/CLK
- u_zoom_image/mult_image_g1/N2/gopapm/PI[2]
-
- clk_200m
- clk_200m
- rise-rise
- 0.177
- 5.374
- 5.990
- -0.439
- 0.000
- 0.297
- 0.297 (100.0%)
- 0.000 (0.0%)
-
- Path #14: hold slack is 0.241(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.252
- 0
- 1
- image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK
- image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D
-
- clk_50m
- clk_50m
- rise-rise
- 0.000
- 5.378
- 5.873
- -0.495
- 0.000
- 0.305
- 0.221 (72.5%)
- 0.084 (27.5%)
-
- Path #15: hold slack is 0.252(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.313
- 0
- 1
- adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK
- adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- 0.029
- 8.831
- 9.434
- -0.574
- 0.000
- 0.308
- 0.224 (72.7%)
- 0.084 (27.3%)
-
- Path #16: hold slack is 0.313(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.314
- 0
- 1
- adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK
- adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- 0.029
- 8.831
- 9.434
- -0.574
- 0.000
- 0.308
- 0.224 (72.7%)
- 0.084 (27.3%)
-
- Path #17: hold slack is 0.314(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.314
- 0
- 2
- ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK
- ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D
-
- clk_10m
- clk_10m
- rise-rise
- 0.029
- 5.378
- 5.873
- -0.466
- 0.000
- 0.329
- 0.226 (68.7%)
- 0.103 (31.3%)
-
- Path #18: hold slack is 0.314(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.314
- 0
- 2
- udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK
- udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- 0.029
- 8.831
- 9.434
- -0.574
- 0.000
- 0.309
- 0.224 (72.5%)
- 0.085 (27.5%)
-
- Path #19: hold slack is 0.314(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.331
- 0
- 3
- ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK
- ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADB0[9]
-
- clk_10m
- clk_10m
- rise-rise
- 0.036
- 5.378
- 5.873
- -0.459
- 0.000
- 0.446
- 0.226 (50.7%)
- 0.220 (49.3%)
-
- Path #20: hold slack is 0.331(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.340
- 0
- 3
- ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK
- ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9]
-
- clk_10m
- clk_10m
- rise-rise
- 0.036
- 5.378
- 5.873
- -0.459
- 0.000
- 0.537
- 0.222 (41.3%)
- 0.315 (58.7%)
-
- Path #21: hold slack is 0.340(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.376
- 0
- 6
- u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
- u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5]
-
- clk_20k
- clk_20k
- rise-rise
- 0.036
- 9.247
- 10.099
- -0.816
- 0.000
- 0.573
- 0.222 (38.7%)
- 0.351 (61.3%)
-
- Path #22: hold slack is 0.376(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.378
- 0
- 6
- u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
- u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5]
-
- clk_20k
- clk_20k
- rise-rise
- 0.036
- 9.014
- 9.812
- -0.762
- 0.000
- 0.575
- 0.222 (38.6%)
- 0.353 (61.4%)
-
- Path #23: hold slack is 0.378(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.381
- 0
- 5
- udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK
- udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/A3
-
- eth_rxc
- eth_rxc
- rise-rise
- 0.000
- 8.446
- 10.030
- -1.584
- 0.000
- 0.312
- 0.224 (71.8%)
- 0.088 (28.2%)
-
- Path #24: hold slack is 0.381(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.386
- 0
- 2
- udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/CLK
- udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/Cin
-
- eth_rxc
- eth_rxc
- rise-rise
- 0.029
- 8.446
- 10.030
- -1.555
- 0.000
- 0.544
- 0.357 (65.6%)
- 0.187 (34.4%)
-
- Path #25: hold slack is 0.386(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.391
- 0
- 1
- param_manager_inst/modify_H_flags_ff1/opit_0/CLK
- param_manager_inst/modify_H_load/opit_0_L5Q_perm/L2
-
- eth_rxc
- eth_rxc
- rise-rise
- 0.000
- 8.446
- 10.030
- -1.584
- 0.000
- 0.370
- 0.284 (76.8%)
- 0.086 (23.2%)
-
- Path #26: hold slack is 0.391(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.401
- 0
- 2
- u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/CLK
- u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/L0
-
- clk_20k
- clk_20k
- rise-rise
- 0.000
- 9.014
- 9.812
- -0.798
- 0.000
- 0.307
- 0.222 (72.3%)
- 0.085 (27.7%)
-
- Path #27: hold slack is 0.401(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.415
- 0
- 5
- u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK
- u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CE
-
- cmos2_pclk
- cmos2_pclk
- rise-rise
- 0.036
- 5.551
- 6.202
- -0.615
- 0.000
- 0.431
- 0.222 (51.5%)
- 0.209 (48.5%)
-
- Path #28: hold slack is 0.415(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.419
- 0
- 5
- u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK
- u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/L2
-
- cmos2_pclk
- cmos2_pclk
- rise-rise
- 0.029
- 5.551
- 6.202
- -0.622
- 0.000
- 0.413
- 0.221 (53.5%)
- 0.192 (46.5%)
-
- Path #29: hold slack is 0.419(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.424
- 0
- 5
- u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK
- u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/L2
-
- cmos2_pclk
- cmos2_pclk
- rise-rise
- 0.029
- 5.551
- 6.202
- -0.622
- 0.000
- 0.418
- 0.224 (53.6%)
- 0.194 (46.4%)
-
- Path #30: hold slack is 0.424(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.450
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
-
- ioclk1
- ioclk1
- rise-rise
- 0.035
- 7.041
- 7.712
- -0.636
- 0.000
- 0.421
- 0.421 (100.0%)
- 0.000 (0.0%)
-
- Path #31: hold slack is 0.450(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.450
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
-
- ioclk1
- ioclk1
- rise-rise
- 0.035
- 7.041
- 7.712
- -0.636
- 0.000
- 0.421
- 0.421 (100.0%)
- 0.000 (0.0%)
-
- Path #32: hold slack is 0.450(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.450
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
-
- ioclk1
- ioclk1
- rise-rise
- 0.035
- 7.041
- 7.712
- -0.636
- 0.000
- 0.421
- 0.421 (100.0%)
- 0.000 (0.0%)
-
- Path #33: hold slack is 0.450(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.450
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
-
- ioclk0
- ioclk0
- rise-rise
- 0.035
- 7.041
- 7.712
- -0.636
- 0.000
- 0.421
- 0.421 (100.0%)
- 0.000 (0.0%)
-
- Path #34: hold slack is 0.450(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.450
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
-
- ioclk0
- ioclk0
- rise-rise
- 0.035
- 7.041
- 7.712
- -0.636
- 0.000
- 0.421
- 0.421 (100.0%)
- 0.000 (0.0%)
-
- Path #35: hold slack is 0.450(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.450
- 0
- 8
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
-
- ioclk0
- ioclk0
- rise-rise
- 0.035
- 7.041
- 7.712
- -0.636
- 0.000
- 0.421
- 0.421 (100.0%)
- 0.000 (0.0%)
-
- Path #36: hold slack is 0.450(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.575
- 0
- 3
- u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
- u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
-
- clk_25m
- clk_25m
- rise-rise
- 0.000
- 5.383
- 5.877
- -0.494
- 0.000
- 0.561
- 0.229 (40.8%)
- 0.332 (59.2%)
-
- Path #37: hold slack is 0.575(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.711
- 0
- 3
- u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK
- u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
-
- clk_25m
- clk_25m
- rise-rise
- 0.000
- 5.383
- 5.877
- -0.494
- 0.000
- 0.697
- 0.229 (32.9%)
- 0.468 (67.1%)
-
- Path #38: hold slack is 0.711(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.742
- 1
- 2
- u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK
- u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D
-
- clk_25m
- clk_25m
- rise-rise
- 0.000
- 5.383
- 5.877
- -0.494
- 0.000
- 0.795
- 0.516 (64.9%)
- 0.279 (35.1%)
-
- Path #39: hold slack is 0.742(MET)
-
-
-
-
-
-
-
-
-
-
-
-
-
- 1.103
- 0
- 686
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS
-
- clk_200m
- clk_200m
- rise-rise
- -0.054
- 5.867
- 5.374
- 0.439
- 5.000
- 3.076
- 0.289 (9.4%)
- 2.787 (90.6%)
-
- Path #2: recovery slack is 1.103(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.191
- 0
- 131
- u_zoom_rst/rst/opit_0_L5Q_perm/CLK
- u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0]
-
- clk_200m
- clk_200m
- rise-rise
- 0.067
- 5.867
- 5.495
- 0.439
- 5.000
- 3.611
- 0.287 (7.9%)
- 3.324 (92.1%)
-
- Path #3: recovery slack is 1.191(MET)
-
-
-
-
-
-
-
-
-
-
-
- 5.474
- 17
- 619
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS
-
- ddrphy_clkin
- ddrphy_clkin
- rise-rise
- 0.067
- 11.394
- 10.786
- 0.675
- 10.000
- 4.443
- 2.788 (62.8%)
- 1.655 (37.2%)
-
- Path #4: recovery slack is 5.474(MET)
-
-
-
-
-
-
-
-
-
-
-
- 5.474
- 17
- 619
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS
-
- ddrphy_clkin
- ddrphy_clkin
- rise-rise
- 0.067
- 11.394
- 10.786
- 0.675
- 10.000
- 4.443
- 2.788 (62.8%)
- 1.655 (37.2%)
-
- Path #5: recovery slack is 5.474(MET)
-
-
-
-
-
-
-
-
-
-
-
- 5.474
- 17
- 619
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS
-
- ddrphy_clkin
- ddrphy_clkin
- rise-rise
- 0.067
- 11.394
- 10.786
- 0.675
- 10.000
- 4.443
- 2.788 (62.8%)
- 1.655 (37.2%)
-
- Path #6: recovery slack is 5.474(MET)
-
-
-
-
-
-
-
-
-
-
-
- 8.580
- 10
- 1066
- sync_vg_100m/opit_0_inv_L5Q_perm/CLK
- adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- -0.054
- 9.434
- 8.831
- 0.549
- 13.473
- 4.689
- 1.757 (37.5%)
- 2.932 (62.5%)
-
- Path #7: recovery slack is 8.580(MET)
-
-
-
-
-
-
-
-
-
-
-
- 8.580
- 10
- 1066
- sync_vg_100m/opit_0_inv_L5Q_perm/CLK
- adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- -0.054
- 9.434
- 8.831
- 0.549
- 13.473
- 4.689
- 1.757 (37.5%)
- 2.932 (62.5%)
-
- Path #8: recovery slack is 8.580(MET)
-
-
-
-
-
-
-
-
-
-
-
- 8.580
- 10
- 1066
- sync_vg_100m/opit_0_inv_L5Q_perm/CLK
- adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- -0.054
- 9.434
- 8.831
- 0.549
- 13.473
- 4.689
- 1.757 (37.5%)
- 2.932 (62.5%)
-
- Path #9: recovery slack is 8.580(MET)
-
-
-
-
-
-
-
-
-
-
-
- 16.039
- 7
- 573
- u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
- u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS
-
- clk_50m
- clk_50m
- rise-rise
- -0.054
- 5.873
- 5.378
- 0.441
- 20.000
- 3.757
- 1.316 (35.0%)
- 2.441 (65.0%)
-
- Path #10: recovery slack is 16.039(MET)
-
-
-
-
-
-
-
-
-
-
-
- 16.039
- 7
- 573
- u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
- u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS
-
- clk_50m
- clk_50m
- rise-rise
- -0.054
- 5.873
- 5.378
- 0.441
- 20.000
- 3.757
- 1.316 (35.0%)
- 2.441 (65.0%)
-
- Path #11: recovery slack is 16.039(MET)
-
-
-
-
-
-
-
-
-
-
-
- 16.039
- 7
- 573
- u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
- u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS
-
- clk_50m
- clk_50m
- rise-rise
- -0.054
- 5.873
- 5.378
- 0.441
- 20.000
- 3.757
- 1.316 (35.0%)
- 2.441 (65.0%)
-
- Path #12: recovery slack is 16.039(MET)
-
-
-
-
-
-
-
-
-
-
-
- 97.793
- 0
- 3
- rstn_out1/opit_0_inv/CLK
- ms72xx_ctl/rstn_temp1/opit_0_inv/RS
-
- clk_10m
- clk_10m
- rise-rise
- -0.036
- 5.873
- 5.378
- 0.459
- 100.000
- 1.404
- 0.286 (20.4%)
- 1.118 (79.6%)
-
- Path #13: recovery slack is 97.793(MET)
-
-
-
-
-
-
-
-
-
-
-
-
-
- 0.554
- 0
- 2
- u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS
-
- clk_200m
- clk_200m
- rise-rise
- 0.067
- 5.374
- 5.867
- -0.426
- 0.000
- 0.401
- 0.222 (55.4%)
- 0.179 (44.6%)
-
- Path #2: removal slack is 0.554(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.555
- 0
- 37
- image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
- image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
-
- clk_50m
- clk_50m
- rise-rise
- 0.036
- 5.378
- 5.873
- -0.459
- 0.000
- 0.569
- 0.222 (39.0%)
- 0.347 (61.0%)
-
- Path #3: removal slack is 0.555(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.579
- 0
- 37
- image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
- image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0]
-
- clk_50m
- clk_50m
- rise-rise
- 0.036
- 5.378
- 5.873
- -0.459
- 0.000
- 0.569
- 0.222 (39.0%)
- 0.347 (61.0%)
-
- Path #4: removal slack is 0.579(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.734
- 1
- 14
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS
-
- clk_200m
- clk_200m
- rise-rise
- 0.036
- 5.374
- 5.867
- -0.457
- 0.000
- 0.770
- 0.327 (42.5%)
- 0.443 (57.5%)
-
- Path #5: removal slack is 0.734(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.760
- 1
- 37
- image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
- image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS
-
- clk_50m
- clk_50m
- rise-rise
- 0.036
- 5.378
- 5.873
- -0.459
- 0.000
- 0.796
- 0.331 (41.6%)
- 0.465 (58.4%)
-
- Path #6: removal slack is 0.760(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.779
- 1
- 619
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS
-
- ddrphy_clkin
- ddrphy_clkin
- rise-rise
- 0.036
- 10.665
- 11.394
- -0.693
- 0.000
- 0.815
- 0.327 (40.1%)
- 0.488 (59.9%)
-
- Path #7: removal slack is 0.779(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.779
- 1
- 619
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS
-
- ddrphy_clkin
- ddrphy_clkin
- rise-rise
- 0.036
- 10.665
- 11.394
- -0.693
- 0.000
- 0.815
- 0.327 (40.1%)
- 0.488 (59.9%)
-
- Path #8: removal slack is 0.779(MET)
-
-
-
-
-
-
-
-
-
-
-
- 0.779
- 1
- 619
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
- u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS
-
- ddrphy_clkin
- ddrphy_clkin
- rise-rise
- 0.036
- 10.665
- 11.394
- -0.693
- 0.000
- 0.815
- 0.327 (40.1%)
- 0.488 (59.9%)
-
- Path #9: removal slack is 0.779(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.244
- 0
- 163
- u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
- u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0]
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- 0.036
- 8.831
- 9.434
- -0.567
- 0.000
- 1.203
- 0.226 (18.8%)
- 0.977 (81.2%)
-
- Path #10: removal slack is 1.244(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.312
- 0
- 3
- rstn_out1/opit_0_inv/CLK
- ms72xx_ctl/rstn_temp1/opit_0_inv/RS
-
- clk_10m
- clk_10m
- rise-rise
- 0.036
- 5.378
- 5.873
- -0.459
- 0.000
- 1.122
- 0.226 (20.1%)
- 0.896 (79.9%)
-
- Path #11: removal slack is 1.312(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.355
- 0
- 163
- u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
- u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- 0.054
- 8.831
- 9.434
- -0.549
- 0.000
- 1.332
- 0.226 (17.0%)
- 1.106 (83.0%)
-
- Path #12: removal slack is 1.355(MET)
-
-
-
-
-
-
-
-
-
-
-
- 1.377
- 0
- 163
- u_hdmi_rst/rst/opit_0_L5Q_perm/CLK
- u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[15]/opit_0/RS
-
- clk_720p60Hz
- clk_720p60Hz
- rise-rise
- 0.054
- 8.831
- 9.434
- -0.549
- 0.000
- 1.205
- 0.226 (18.8%)
- 0.979 (81.2%)
-
- Path #13: removal slack is 1.377(MET)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+ 1.030
+ 7
+ 187
+ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE
+
+ eth_rxc
+ eth_rxc
+ rise-rise
+ -0.036
+ 10.153
+ 8.567
+ 1.550
+ 8.000
+ 5.955
+ 1.785 (30.0%)
+ 4.170 (70.0%)
+
+ Path #2: setup slack is 1.030(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.030
+ 7
+ 187
+ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK
+ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE
+
+ eth_rxc
+ eth_rxc
+ rise-rise
+ -0.036
+ 10.153
+ 8.567
+ 1.550
+ 8.000
+ 5.955
+ 1.785 (30.0%)
+ 4.170 (70.0%)
+
+ Path #3: setup slack is 1.030(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.083
+ 0
+ 3
+ u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+ u_zoom_image/mult_image_g1_0/N2/gopapm/X[3]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ -0.177
+ 9.563
+ 8.835
+ 0.551
+ 6.736
+ 3.083
+ 1.067 (34.6%)
+ 2.016 (65.4%)
+
+ Path #4: setup slack is 1.083(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.099
+ 0
+ 3
+ u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+ u_zoom_image/mult_image_g1_0/N2/gopapm/X[0]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ -0.177
+ 9.563
+ 8.835
+ 0.551
+ 6.736
+ 3.067
+ 1.067 (34.8%)
+ 2.000 (65.2%)
+
+ Path #5: setup slack is 1.099(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.121
+ 5
+ 11
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CE
+
+ clk_200m
+ clk_200m
+ rise-rise
+ 0.000
+ 5.867
+ 5.374
+ 0.493
+ 5.000
+ 3.000
+ 1.911 (63.7%)
+ 1.089 (36.3%)
+
+ Path #6: setup slack is 1.121(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.121
+ 5
+ 11
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE
+
+ clk_200m
+ clk_200m
+ rise-rise
+ 0.000
+ 5.867
+ 5.374
+ 0.493
+ 5.000
+ 3.000
+ 1.911 (63.7%)
+ 1.089 (36.3%)
+
+ Path #7: setup slack is 1.121(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.121
+ 5
+ 11
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE
+
+ clk_200m
+ clk_200m
+ rise-rise
+ 0.000
+ 5.867
+ 5.374
+ 0.493
+ 5.000
+ 3.000
+ 1.911 (63.7%)
+ 1.089 (36.3%)
+
+ Path #8: setup slack is 1.121(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.131
+ 0
+ 3
+ u_zoom_image/mult_fra0_0/N2/gopapm/CLK
+ u_zoom_image/mult_image_g0_0/N2/gopapm/X[1]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ -0.177
+ 9.563
+ 8.835
+ 0.551
+ 6.736
+ 3.035
+ 1.067 (35.2%)
+ 1.968 (64.8%)
+
+ Path #9: setup slack is 1.131(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.692
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
+
+ ioclk1
+ ioclk1
+ rise-rise
+ 0.006
+ 7.692
+ 7.062
+ 0.636
+ 2.500
+ 0.528
+ 0.528 (100.0%)
+ 0.000 (0.0%)
+
+ Path #10: setup slack is 1.692(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.692
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
+
+ ioclk1
+ ioclk1
+ rise-rise
+ 0.006
+ 7.692
+ 7.062
+ 0.636
+ 2.500
+ 0.528
+ 0.528 (100.0%)
+ 0.000 (0.0%)
+
+ Path #11: setup slack is 1.692(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.692
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
+
+ ioclk1
+ ioclk1
+ rise-rise
+ 0.006
+ 7.692
+ 7.062
+ 0.636
+ 2.500
+ 0.528
+ 0.528 (100.0%)
+ 0.000 (0.0%)
+
+ Path #12: setup slack is 1.692(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.692
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
+
+ ioclk0
+ ioclk0
+ rise-rise
+ 0.006
+ 7.692
+ 7.062
+ 0.636
+ 2.500
+ 0.528
+ 0.528 (100.0%)
+ 0.000 (0.0%)
+
+ Path #13: setup slack is 1.692(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.692
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
+
+ ioclk0
+ ioclk0
+ rise-rise
+ 0.006
+ 7.692
+ 7.062
+ 0.636
+ 2.500
+ 0.528
+ 0.528 (100.0%)
+ 0.000 (0.0%)
+
+ Path #14: setup slack is 1.692(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.692
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
+
+ ioclk0
+ ioclk0
+ rise-rise
+ 0.006
+ 7.692
+ 7.062
+ 0.636
+ 2.500
+ 0.528
+ 0.528 (100.0%)
+ 0.000 (0.0%)
+
+ Path #15: setup slack is 1.692(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.839
+ 5
+ 4
+ u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
+ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4
+
+ hdmi_in_clk
+ hdmi_in_clk
+ rise-rise
+ -0.036
+ 6.435
+ 5.951
+ 0.448
+ 6.666
+ 4.418
+ 2.352 (53.2%)
+ 2.066 (46.8%)
+
+ Path #16: setup slack is 1.839(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 2.472
+ 7
+ 40
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ -0.036
+ 11.394
+ 10.665
+ 0.693
+ 10.000
+ 6.944
+ 3.399 (48.9%)
+ 3.545 (51.1%)
+
+ Path #17: setup slack is 2.472(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 2.514
+ 7
+ 56
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/I2
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ -0.036
+ 11.394
+ 10.665
+ 0.693
+ 10.000
+ 6.909
+ 3.131 (45.3%)
+ 3.778 (54.7%)
+
+ Path #18: setup slack is 2.514(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 2.527
+ 7
+ 56
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/I2
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ -0.036
+ 11.394
+ 10.665
+ 0.693
+ 10.000
+ 6.899
+ 3.140 (45.5%)
+ 3.759 (54.5%)
+
+ Path #19: setup slack is 2.527(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 3.545
+ 2
+ 4
+ u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
+ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2
+
+ hdmi_in_clk
+ hdmi_in_clk
+ rise-rise
+ -0.036
+ 6.435
+ 5.951
+ 0.448
+ 6.666
+ 2.467
+ 0.964 (39.1%)
+ 1.503 (60.9%)
+
+ Path #20: setup slack is 3.545(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 3.657
+ 3
+ 4
+ u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK
+ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1
+
+ hdmi_in_clk
+ hdmi_in_clk
+ rise-rise
+ -0.036
+ 6.435
+ 5.951
+ 0.448
+ 6.666
+ 2.489
+ 1.310 (52.6%)
+ 1.179 (47.4%)
+
+ Path #21: setup slack is 3.657(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 4.347
+ 2
+ 1
+ cmos2_data[6]
+ u_ov5640/cmos2_d_d0[6]/opit_0/D
+
+ cmos2_pclk
+ cmos2_pclk
+ rise-rise
+ 5.548
+ 0.000
+ 5.548
+ 0.000
+ 11.900
+ 11.763
+ 1.640 (13.9%)
+ 10.123 (86.1%)
+
+ Path #22: setup slack is 4.347(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 4.366
+ 3
+ 1
+ cmos2_data[5]
+ u_ov5640/cmos2_d_d0[5]/opit_0/D
+
+ cmos2_pclk
+ cmos2_pclk
+ rise-rise
+ 5.548
+ 0.000
+ 5.548
+ 0.000
+ 11.900
+ 11.744
+ 1.774 (15.1%)
+ 9.970 (84.9%)
+
+ Path #23: setup slack is 4.366(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 4.403
+ 4
+ 1
+ cmos2_href
+ u_ov5640/cmos2_href_d0/opit_0/D
+
+ cmos2_pclk
+ cmos2_pclk
+ rise-rise
+ 5.595
+ 0.000
+ 5.595
+ 0.000
+ 11.900
+ 11.871
+ 1.760 (14.8%)
+ 10.111 (85.2%)
+
+ Path #24: setup slack is 4.403(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 5.305
+ 2
+ 1
+ cmos1_href
+ u_ov5640/cmos1_href_d0/opit_0/D
+
+ cmos1_pclk
+ cmos1_pclk
+ rise-rise
+ 5.188
+ 0.000
+ 5.188
+ 0.000
+ 11.900
+ 10.445
+ 1.494 (14.3%)
+ 8.951 (85.7%)
+
+ Path #25: setup slack is 5.305(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 5.924
+ 2
+ 1
+ cmos1_data[6]
+ u_ov5640/cmos1_d_d0[6]/opit_0/D
+
+ cmos1_pclk
+ cmos1_pclk
+ rise-rise
+ 5.188
+ 0.000
+ 5.188
+ 0.000
+ 11.900
+ 9.835
+ 2.292 (23.3%)
+ 7.543 (76.7%)
+
+ Path #26: setup slack is 5.924(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 5.988
+ 7
+ 15
+ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK
+ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ -0.036
+ 9.557
+ 8.952
+ 0.569
+ 13.473
+ 6.942
+ 3.294 (47.5%)
+ 3.648 (52.5%)
+
+ Path #27: setup slack is 5.988(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 6.037
+ 2
+ 1
+ cmos1_data[0]
+ u_ov5640/cmos1_d_d0[0]/opit_0/D
+
+ cmos1_pclk
+ cmos1_pclk
+ rise-rise
+ 5.188
+ 0.000
+ 5.188
+ 0.000
+ 11.900
+ 9.830
+ 2.292 (23.3%)
+ 7.538 (76.7%)
+
+ Path #28: setup slack is 6.037(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 6.184
+ 9
+ 12
+ u_sync_vg/pos_x[2]/opit_0/CLK
+ udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ -0.036
+ 9.557
+ 8.952
+ 0.569
+ 13.473
+ 6.374
+ 2.619 (41.1%)
+ 3.755 (58.9%)
+
+ Path #29: setup slack is 6.184(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 6.184
+ 9
+ 12
+ u_sync_vg/pos_x[2]/opit_0/CLK
+ udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ -0.036
+ 9.557
+ 8.952
+ 0.569
+ 13.473
+ 6.374
+ 2.619 (41.1%)
+ 3.755 (58.9%)
+
+ Path #30: setup slack is 6.184(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 10.354
+ 6
+ 6
+ u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
+ u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
+
+ clk_50m
+ clk_50m
+ rise-rise
+ -0.058
+ 5.909
+ 5.392
+ 0.459
+ 20.000
+ 9.315
+ 5.094 (54.7%)
+ 4.221 (45.3%)
+
+ Path #31: setup slack is 10.354(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 10.942
+ 5
+ 6
+ u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB
+ u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
+
+ clk_50m
+ clk_50m
+ rise-rise
+ -0.061
+ 5.909
+ 5.389
+ 0.459
+ 20.000
+ 8.490
+ 4.596 (54.1%)
+ 3.894 (45.9%)
+
+ Path #32: setup slack is 10.942(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 10.957
+ 9
+ 5
+ image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK
+ image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
+
+ clk_50m
+ clk_50m
+ rise-rise
+ -0.036
+ 5.996
+ 5.499
+ 0.461
+ 20.000
+ 8.734
+ 4.330 (49.6%)
+ 4.404 (50.4%)
+
+ Path #33: setup slack is 10.957(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 35.501
+ 4
+ 13
+ u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
+ u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D
+
+ clk_25m
+ clk_25m
+ rise-rise
+ -0.029
+ 5.877
+ 5.383
+ 0.465
+ 40.000
+ 4.241
+ 2.002 (47.2%)
+ 2.239 (52.8%)
+
+ Path #34: setup slack is 35.501(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 35.513
+ 3
+ 13
+ u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
+ u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D
+
+ clk_25m
+ clk_25m
+ rise-rise
+ -0.029
+ 5.877
+ 5.383
+ 0.465
+ 40.000
+ 4.229
+ 1.947 (46.0%)
+ 2.282 (54.0%)
+
+ Path #35: setup slack is 35.513(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 35.717
+ 4
+ 13
+ u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK
+ u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D
+
+ clk_25m
+ clk_25m
+ rise-rise
+ -0.029
+ 5.877
+ 5.383
+ 0.465
+ 40.000
+ 4.016
+ 1.771 (44.1%)
+ 2.245 (55.9%)
+
+ Path #36: setup slack is 35.717(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 94.588
+ 6
+ 15
+ ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+ ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE
+
+ clk_10m
+ clk_10m
+ rise-rise
+ -0.036
+ 5.996
+ 5.499
+ 0.461
+ 100.000
+ 4.497
+ 1.885 (41.9%)
+ 2.612 (58.1%)
+
+ Path #37: setup slack is 94.588(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 94.588
+ 6
+ 15
+ ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+ ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE
+
+ clk_10m
+ clk_10m
+ rise-rise
+ -0.036
+ 5.996
+ 5.499
+ 0.461
+ 100.000
+ 4.497
+ 1.885 (41.9%)
+ 2.612 (58.1%)
+
+ Path #38: setup slack is 94.588(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 94.588
+ 6
+ 15
+ ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK
+ ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE
+
+ clk_10m
+ clk_10m
+ rise-rise
+ -0.036
+ 5.996
+ 5.499
+ 0.461
+ 100.000
+ 4.497
+ 1.885 (41.9%)
+ 2.612 (58.1%)
+
+ Path #39: setup slack is 94.588(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 49994.611
+ 3
+ 1
+ u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
+ u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
+
+ clk_20k
+ clk_20k
+ rise-rise
+ -0.036
+ 10.251
+ 9.367
+ 0.848
+ 50000.000
+ 5.107
+ 3.251 (63.7%)
+ 1.856 (36.3%)
+
+ Path #40: setup slack is 49994.611(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 49994.893
+ 3
+ 1
+ u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0]
+ u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4
+
+ clk_20k
+ clk_20k
+ rise-rise
+ -0.093
+ 10.167
+ 9.258
+ 0.816
+ 50000.000
+ 4.843
+ 3.215 (66.4%)
+ 1.628 (33.6%)
+
+ Path #41: setup slack is 49994.893(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 49995.537
+ 1
+ 1
+ u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
+ u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3
+
+ clk_20k
+ clk_20k
+ rise-rise
+ -0.036
+ 10.251
+ 9.367
+ 0.848
+ 50000.000
+ 4.183
+ 2.934 (70.1%)
+ 1.249 (29.9%)
+
+ Path #42: setup slack is 49995.537(MET)
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 0.161
+ 0
+ 2
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WD
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ 0.036
+ 10.665
+ 11.394
+ -0.693
+ 0.000
+ 0.577
+ 0.222 (38.5%)
+ 0.355 (61.5%)
+
+ Path #2: hold slack is 0.161(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.164
+ 0
+ 2
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WD
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ 0.022
+ 10.721
+ 11.436
+ -0.693
+ 0.000
+ 0.566
+ 0.224 (39.6%)
+ 0.342 (60.4%)
+
+ Path #3: hold slack is 0.164(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.172
+ 0
+ 44
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ 0.062
+ 10.691
+ 11.446
+ -0.693
+ 0.000
+ 0.614
+ 0.222 (36.2%)
+ 0.392 (63.8%)
+
+ Path #4: hold slack is 0.172(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.175
+ 0
+ 5
+ u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK
+ u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0
+
+ cmos1_pclk
+ cmos1_pclk
+ rise-rise
+ 0.029
+ 5.188
+ 5.521
+ -0.304
+ 0.000
+ 0.310
+ 0.222 (71.6%)
+ 0.088 (28.4%)
+
+ Path #5: hold slack is 0.175(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.177
+ 0
+ 5
+ u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK
+ u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0
+
+ cmos1_pclk
+ cmos1_pclk
+ rise-rise
+ 0.029
+ 5.188
+ 5.521
+ -0.304
+ 0.000
+ 0.313
+ 0.224 (71.6%)
+ 0.089 (28.4%)
+
+ Path #6: hold slack is 0.177(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.189
+ 0
+ 3
+ u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK
+ u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0
+
+ hdmi_in_clk
+ hdmi_in_clk
+ rise-rise
+ 0.000
+ 5.951
+ 6.435
+ -0.484
+ 0.000
+ 0.310
+ 0.224 (72.3%)
+ 0.086 (27.7%)
+
+ Path #7: hold slack is 0.189(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.190
+ 0
+ 6
+ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK
+ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L1
+
+ hdmi_in_clk
+ hdmi_in_clk
+ rise-rise
+ 0.029
+ 5.951
+ 6.435
+ -0.455
+ 0.000
+ 0.313
+ 0.224 (71.6%)
+ 0.089 (28.4%)
+
+ Path #8: hold slack is 0.190(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.192
+ 0
+ 5
+ u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK
+ u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0
+
+ hdmi_in_clk
+ hdmi_in_clk
+ rise-rise
+ 0.000
+ 5.951
+ 6.435
+ -0.484
+ 0.000
+ 0.313
+ 0.224 (71.6%)
+ 0.089 (28.4%)
+
+ Path #9: hold slack is 0.192(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.193
+ 0
+ 1
+ u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK
+ u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D
+
+ cmos1_pclk
+ cmos1_pclk
+ rise-rise
+ 0.029
+ 5.188
+ 5.521
+ -0.304
+ 0.000
+ 0.475
+ 0.284 (59.8%)
+ 0.191 (40.2%)
+
+ Path #10: hold slack is 0.193(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.201
+ 0
+ 5
+ u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK
+ u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10]
+
+ clk_50m
+ clk_50m
+ rise-rise
+ 0.036
+ 5.378
+ 5.873
+ -0.459
+ 0.000
+ 0.447
+ 0.222 (49.7%)
+ 0.225 (50.3%)
+
+ Path #11: hold slack is 0.201(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.212
+ 0
+ 3
+ u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK
+ u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ 0.036
+ 8.835
+ 9.440
+ -0.569
+ 0.000
+ 0.458
+ 0.224 (48.9%)
+ 0.234 (51.1%)
+
+ Path #12: hold slack is 0.212(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.226
+ 0
+ 1
+ u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK
+ u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/D
+
+ clk_50m
+ clk_50m
+ rise-rise
+ 0.029
+ 5.378
+ 5.873
+ -0.466
+ 0.000
+ 0.308
+ 0.224 (72.7%)
+ 0.084 (27.3%)
+
+ Path #13: hold slack is 0.226(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.231
+ 0
+ 4
+ u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK
+ u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2]
+
+ clk_50m
+ clk_50m
+ rise-rise
+ 0.023
+ 5.421
+ 5.903
+ -0.459
+ 0.000
+ 0.440
+ 0.222 (50.5%)
+ 0.218 (49.5%)
+
+ Path #14: hold slack is 0.231(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.248
+ 0
+ 6
+ u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK
+ u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ 0.036
+ 8.835
+ 9.440
+ -0.569
+ 0.000
+ 0.445
+ 0.224 (50.3%)
+ 0.221 (49.7%)
+
+ Path #15: hold slack is 0.248(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.252
+ 0
+ 1
+ u_zoom_image/image_valid[2][1]/opit_0/CLK
+ u_zoom_image/image_valid[3][1]/opit_0/D
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ 0.000
+ 8.835
+ 9.440
+ -0.605
+ 0.000
+ 0.305
+ 0.221 (72.5%)
+ 0.084 (27.5%)
+
+ Path #16: hold slack is 0.252(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.287
+ 0
+ 2
+ ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK
+ ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D
+
+ clk_10m
+ clk_10m
+ rise-rise
+ 0.029
+ 5.499
+ 5.996
+ -0.468
+ 0.000
+ 0.369
+ 0.284 (77.0%)
+ 0.085 (23.0%)
+
+ Path #17: hold slack is 0.287(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.314
+ 0
+ 1
+ adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK
+ adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ 0.029
+ 8.831
+ 9.434
+ -0.574
+ 0.000
+ 0.308
+ 0.224 (72.7%)
+ 0.084 (27.3%)
+
+ Path #18: hold slack is 0.314(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.314
+ 0
+ 2
+ ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK
+ ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D
+
+ clk_10m
+ clk_10m
+ rise-rise
+ 0.029
+ 5.499
+ 5.996
+ -0.468
+ 0.000
+ 0.329
+ 0.226 (68.7%)
+ 0.103 (31.3%)
+
+ Path #19: hold slack is 0.314(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.314
+ 0
+ 2
+ udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK
+ udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ 0.029
+ 8.952
+ 9.557
+ -0.576
+ 0.000
+ 0.309
+ 0.224 (72.5%)
+ 0.085 (27.5%)
+
+ Path #20: hold slack is 0.314(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.315
+ 0
+ 3
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D
+
+ clk_200m
+ clk_200m
+ rise-rise
+ 0.029
+ 5.374
+ 5.867
+ -0.464
+ 0.000
+ 0.330
+ 0.226 (68.5%)
+ 0.104 (31.5%)
+
+ Path #21: hold slack is 0.315(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.318
+ 0
+ 7
+ u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK
+ u_sync_vg/pos_y[4]/opit_0_A2Q21/I04
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ 0.029
+ 8.952
+ 9.557
+ -0.576
+ 0.000
+ 0.313
+ 0.224 (71.6%)
+ 0.089 (28.4%)
+
+ Path #22: hold slack is 0.318(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.334
+ 0
+ 1
+ ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/CLK
+ ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/D
+
+ clk_10m
+ clk_10m
+ rise-rise
+ 0.029
+ 5.499
+ 5.996
+ -0.468
+ 0.000
+ 0.416
+ 0.224 (53.8%)
+ 0.192 (46.2%)
+
+ Path #23: hold slack is 0.334(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.342
+ 0
+ 3
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4
+
+ clk_200m
+ clk_200m
+ rise-rise
+ 0.000
+ 5.374
+ 5.867
+ -0.493
+ 0.000
+ 0.308
+ 0.221 (71.8%)
+ 0.087 (28.2%)
+
+ Path #24: hold slack is 0.342(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.344
+ 0
+ 4
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4
+
+ clk_200m
+ clk_200m
+ rise-rise
+ 0.000
+ 5.374
+ 5.867
+ -0.493
+ 0.000
+ 0.309
+ 0.222 (71.8%)
+ 0.087 (28.2%)
+
+ Path #25: hold slack is 0.344(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.372
+ 0
+ 6
+ u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
+ u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21/I00
+
+ clk_20k
+ clk_20k
+ rise-rise
+ 0.031
+ 9.293
+ 10.147
+ -0.823
+ 0.000
+ 0.309
+ 0.222 (71.8%)
+ 0.087 (28.2%)
+
+ Path #26: hold slack is 0.372(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.383
+ 1
+ 3
+ param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/CLK
+ param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/Cin
+
+ eth_rxc
+ eth_rxc
+ rise-rise
+ 0.029
+ 8.446
+ 10.030
+ -1.555
+ 0.000
+ 0.527
+ 0.339 (64.3%)
+ 0.188 (35.7%)
+
+ Path #27: hold slack is 0.383(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.384
+ 0
+ 6
+ u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK
+ u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5]
+
+ clk_20k
+ clk_20k
+ rise-rise
+ 0.036
+ 9.367
+ 10.251
+ -0.848
+ 0.000
+ 0.581
+ 0.222 (38.2%)
+ 0.359 (61.8%)
+
+ Path #28: hold slack is 0.384(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.397
+ 0
+ 3
+ udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/CLK
+ udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/Cin
+
+ eth_rxc
+ eth_rxc
+ rise-rise
+ 0.029
+ 8.446
+ 10.030
+ -1.555
+ 0.000
+ 0.544
+ 0.458 (84.2%)
+ 0.086 (15.8%)
+
+ Path #29: hold slack is 0.397(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.402
+ 0
+ 3
+ u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/CLK
+ u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/L0
+
+ clk_20k
+ clk_20k
+ rise-rise
+ 0.000
+ 9.367
+ 10.251
+ -0.884
+ 0.000
+ 0.308
+ 0.222 (72.1%)
+ 0.086 (27.9%)
+
+ Path #30: hold slack is 0.402(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.407
+ 0
+ 3
+ u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK
+ u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L3
+
+ cmos2_pclk
+ cmos2_pclk
+ rise-rise
+ 0.000
+ 5.548
+ 6.200
+ -0.652
+ 0.000
+ 0.369
+ 0.284 (77.0%)
+ 0.085 (23.0%)
+
+ Path #31: hold slack is 0.407(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.425
+ 0
+ 5
+ u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK
+ u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CE
+
+ cmos2_pclk
+ cmos2_pclk
+ rise-rise
+ 0.029
+ 5.548
+ 6.200
+ -0.623
+ 0.000
+ 0.434
+ 0.224 (51.6%)
+ 0.210 (48.4%)
+
+ Path #32: hold slack is 0.425(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.425
+ 0
+ 5
+ u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK
+ u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CE
+
+ cmos2_pclk
+ cmos2_pclk
+ rise-rise
+ 0.029
+ 5.548
+ 6.200
+ -0.623
+ 0.000
+ 0.434
+ 0.224 (51.6%)
+ 0.210 (48.4%)
+
+ Path #33: hold slack is 0.425(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.450
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
+
+ ioclk1
+ ioclk1
+ rise-rise
+ 0.035
+ 7.041
+ 7.712
+ -0.636
+ 0.000
+ 0.421
+ 0.421 (100.0%)
+ 0.000 (0.0%)
+
+ Path #34: hold slack is 0.450(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.450
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
+
+ ioclk1
+ ioclk1
+ rise-rise
+ 0.035
+ 7.041
+ 7.712
+ -0.636
+ 0.000
+ 0.421
+ 0.421 (100.0%)
+ 0.000 (0.0%)
+
+ Path #35: hold slack is 0.450(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.450
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
+
+ ioclk1
+ ioclk1
+ rise-rise
+ 0.035
+ 7.041
+ 7.712
+ -0.636
+ 0.000
+ 0.421
+ 0.421 (100.0%)
+ 0.000 (0.0%)
+
+ Path #36: hold slack is 0.450(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.450
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
+
+ ioclk0
+ ioclk0
+ rise-rise
+ 0.035
+ 7.041
+ 7.712
+ -0.636
+ 0.000
+ 0.421
+ 0.421 (100.0%)
+ 0.000 (0.0%)
+
+ Path #37: hold slack is 0.450(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.450
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
+
+ ioclk0
+ ioclk0
+ rise-rise
+ 0.035
+ 7.041
+ 7.712
+ -0.636
+ 0.000
+ 0.421
+ 0.421 (100.0%)
+ 0.000 (0.0%)
+
+ Path #38: hold slack is 0.450(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.450
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
+
+ ioclk0
+ ioclk0
+ rise-rise
+ 0.035
+ 7.041
+ 7.712
+ -0.636
+ 0.000
+ 0.421
+ 0.421 (100.0%)
+ 0.000 (0.0%)
+
+ Path #39: hold slack is 0.450(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.550
+ 0
+ 3
+ u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+ u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
+
+ clk_25m
+ clk_25m
+ rise-rise
+ 0.000
+ 5.383
+ 5.877
+ -0.494
+ 0.000
+ 0.526
+ 0.224 (42.6%)
+ 0.302 (57.4%)
+
+ Path #40: hold slack is 0.550(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.581
+ 0
+ 3
+ u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK
+ u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
+
+ clk_25m
+ clk_25m
+ rise-rise
+ 0.000
+ 5.383
+ 5.877
+ -0.494
+ 0.000
+ 0.567
+ 0.229 (40.4%)
+ 0.338 (59.6%)
+
+ Path #41: hold slack is 0.581(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.655
+ 1
+ 3
+ u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK
+ u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D
+
+ clk_25m
+ clk_25m
+ rise-rise
+ 0.000
+ 5.383
+ 5.877
+ -0.494
+ 0.000
+ 0.641
+ 0.451 (70.4%)
+ 0.190 (29.6%)
+
+ Path #42: hold slack is 0.655(MET)
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1.493
+ 0
+ 687
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS
+
+ clk_200m
+ clk_200m
+ rise-rise
+ -0.177
+ 5.990
+ 5.374
+ 0.439
+ 5.000
+ 2.563
+ 0.289 (11.3%)
+ 2.274 (88.7%)
+
+ Path #2: recovery slack is 1.493(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.493
+ 0
+ 687
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS
+
+ clk_200m
+ clk_200m
+ rise-rise
+ -0.177
+ 5.990
+ 5.374
+ 0.439
+ 5.000
+ 2.563
+ 0.289 (11.3%)
+ 2.274 (88.7%)
+
+ Path #3: recovery slack is 1.493(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 3.268
+ 0
+ 114
+ u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ 0.067
+ 9.440
+ 8.956
+ 0.551
+ 6.736
+ 3.270
+ 0.287 (8.8%)
+ 2.983 (91.2%)
+
+ Path #4: recovery slack is 3.268(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 3.320
+ 0
+ 114
+ u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ 0.067
+ 9.440
+ 8.956
+ 0.551
+ 6.736
+ 3.218
+ 0.287 (8.9%)
+ 2.931 (91.1%)
+
+ Path #5: recovery slack is 3.320(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 3.423
+ 0
+ 114
+ u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ 0.067
+ 9.440
+ 8.956
+ 0.551
+ 6.736
+ 3.115
+ 0.287 (9.2%)
+ 2.828 (90.8%)
+
+ Path #6: recovery slack is 3.423(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 5.676
+ 16
+ 729
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ -0.036
+ 11.394
+ 10.665
+ 0.693
+ 10.000
+ 4.138
+ 2.641 (63.8%)
+ 1.497 (36.2%)
+
+ Path #7: recovery slack is 5.676(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 5.676
+ 16
+ 729
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ -0.036
+ 11.394
+ 10.665
+ 0.693
+ 10.000
+ 4.138
+ 2.641 (63.8%)
+ 1.497 (36.2%)
+
+ Path #8: recovery slack is 5.676(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 5.676
+ 16
+ 729
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ -0.036
+ 11.394
+ 10.665
+ 0.693
+ 10.000
+ 4.138
+ 2.641 (63.8%)
+ 1.497 (36.2%)
+
+ Path #9: recovery slack is 5.676(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 8.940
+ 14
+ 911
+ sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ -0.056
+ 9.557
+ 8.952
+ 0.549
+ 13.473
+ 4.327
+ 2.345 (54.2%)
+ 1.982 (45.8%)
+
+ Path #10: recovery slack is 8.940(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 8.940
+ 14
+ 911
+ sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ -0.056
+ 9.557
+ 8.952
+ 0.549
+ 13.473
+ 4.327
+ 2.345 (54.2%)
+ 1.982 (45.8%)
+
+ Path #11: recovery slack is 8.940(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 8.940
+ 14
+ 911
+ sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ -0.056
+ 9.557
+ 8.952
+ 0.549
+ 13.473
+ 4.327
+ 2.345 (54.2%)
+ 1.982 (45.8%)
+
+ Path #12: recovery slack is 8.940(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 15.776
+ 0
+ 589
+ u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
+ u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS
+
+ clk_50m
+ clk_50m
+ rise-rise
+ -0.040
+ 5.873
+ 5.392
+ 0.441
+ 20.000
+ 3.417
+ 0.287 (8.4%)
+ 3.130 (91.6%)
+
+ Path #13: recovery slack is 15.776(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 15.952
+ 0
+ 589
+ u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
+ u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS
+
+ clk_50m
+ clk_50m
+ rise-rise
+ -0.029
+ 5.873
+ 5.403
+ 0.441
+ 20.000
+ 3.252
+ 0.287 (8.8%)
+ 2.965 (91.2%)
+
+ Path #14: recovery slack is 15.952(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 15.952
+ 0
+ 589
+ u_clk50m_rst/rst/opit_0_L5Q_perm/CLK
+ u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS
+
+ clk_50m
+ clk_50m
+ rise-rise
+ -0.029
+ 5.873
+ 5.403
+ 0.441
+ 20.000
+ 3.252
+ 0.287 (8.8%)
+ 2.965 (91.2%)
+
+ Path #15: recovery slack is 15.952(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 97.797
+ 0
+ 3
+ rstn_out1/opit_0_inv/CLK
+ ms72xx_ctl/rstn_temp1/opit_0_inv/RS
+
+ clk_10m
+ clk_10m
+ rise-rise
+ 0.067
+ 5.873
+ 5.499
+ 0.441
+ 100.000
+ 1.503
+ 0.286 (19.0%)
+ 1.217 (81.0%)
+
+ Path #16: recovery slack is 97.797(MET)
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 0.555
+ 0
+ 2
+ u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS
+
+ clk_200m
+ clk_200m
+ rise-rise
+ 0.069
+ 5.495
+ 5.990
+ -0.426
+ 0.000
+ 0.404
+ 0.222 (55.0%)
+ 0.182 (45.0%)
+
+ Path #2: removal slack is 0.555(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.610
+ 0
+ 40
+ image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+ image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+
+ clk_50m
+ clk_50m
+ rise-rise
+ 0.036
+ 5.499
+ 5.996
+ -0.461
+ 0.000
+ 0.624
+ 0.222 (35.6%)
+ 0.402 (64.4%)
+
+ Path #3: removal slack is 0.610(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.619
+ 1
+ 40
+ image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+ image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS
+
+ clk_50m
+ clk_50m
+ rise-rise
+ 0.036
+ 5.499
+ 5.996
+ -0.461
+ 0.000
+ 0.655
+ 0.337 (51.5%)
+ 0.318 (48.5%)
+
+ Path #4: removal slack is 0.619(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.619
+ 1
+ 40
+ image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK
+ image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS
+
+ clk_50m
+ clk_50m
+ rise-rise
+ 0.036
+ 5.499
+ 5.996
+ -0.461
+ 0.000
+ 0.655
+ 0.337 (51.5%)
+ 0.318 (48.5%)
+
+ Path #5: removal slack is 0.619(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.637
+ 1
+ 729
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ 0.036
+ 10.665
+ 11.394
+ -0.693
+ 0.000
+ 0.673
+ 0.327 (48.6%)
+ 0.346 (51.4%)
+
+ Path #6: removal slack is 0.637(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.637
+ 1
+ 729
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ 0.036
+ 10.665
+ 11.394
+ -0.693
+ 0.000
+ 0.673
+ 0.327 (48.6%)
+ 0.346 (51.4%)
+
+ Path #7: removal slack is 0.637(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.637
+ 1
+ 729
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS
+
+ ddrphy_clkin
+ ddrphy_clkin
+ rise-rise
+ 0.036
+ 10.665
+ 11.394
+ -0.693
+ 0.000
+ 0.673
+ 0.327 (48.6%)
+ 0.346 (51.4%)
+
+ Path #8: removal slack is 0.637(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.891
+ 0
+ 22
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/RS
+
+ clk_200m
+ clk_200m
+ rise-rise
+ 0.036
+ 5.374
+ 5.867
+ -0.457
+ 0.000
+ 0.707
+ 0.222 (31.4%)
+ 0.485 (68.6%)
+
+ Path #9: removal slack is 0.891(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 0.984
+ 0
+ 911
+ sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ 0.056
+ 8.952
+ 9.557
+ -0.549
+ 0.000
+ 1.018
+ 0.222 (21.8%)
+ 0.796 (78.2%)
+
+ Path #10: removal slack is 0.984(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.249
+ 0
+ 114
+ u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ 0.054
+ 8.835
+ 9.440
+ -0.551
+ 0.000
+ 1.230
+ 0.226 (18.4%)
+ 1.004 (81.6%)
+
+ Path #11: removal slack is 1.249(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.263
+ 0
+ 3
+ rstn_out1/opit_0_inv/CLK
+ ms72xx_ctl/rstn_temp1/opit_0_inv/RS
+
+ clk_10m
+ clk_10m
+ rise-rise
+ 0.177
+ 5.378
+ 5.996
+ -0.441
+ 0.000
+ 1.214
+ 0.226 (18.6%)
+ 0.988 (81.4%)
+
+ Path #12: removal slack is 1.263(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.286
+ 3
+ 911
+ sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ 0.056
+ 8.952
+ 9.557
+ -0.549
+ 0.000
+ 1.342
+ 0.541 (40.3%)
+ 0.801 (59.7%)
+
+ Path #13: removal slack is 1.286(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.286
+ 3
+ 911
+ sync_vg_100m/opit_0_inv_L5Q_perm/CLK
+ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS
+
+ clk_720p60Hz
+ clk_720p60Hz
+ rise-rise
+ 0.056
+ 8.952
+ 9.557
+ -0.549
+ 0.000
+ 1.342
+ 0.541 (40.3%)
+ 0.801 (59.7%)
+
+ Path #14: removal slack is 1.286(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.303
+ 0
+ 114
+ u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ 0.036
+ 8.835
+ 9.440
+ -0.569
+ 0.000
+ 1.266
+ 0.226 (17.9%)
+ 1.040 (82.1%)
+
+ Path #15: removal slack is 1.303(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.383
+ 0
+ 114
+ u_zoom_rst/rst/opit_0_L5Q_perm/CLK
+ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ 0.036
+ 8.835
+ 9.440
+ -0.569
+ 0.000
+ 1.346
+ 0.226 (16.8%)
+ 1.120 (83.2%)
+
+ Path #16: removal slack is 1.383(MET)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1.834
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
+
+ ioclk1
+ ioclk1
+ rise-rise
+ -0.003
+ 4.916
+ 4.519
+ 0.394
+ 2.500
+ 0.408
+ 0.408 (100.0%)
+ 0.000 (0.0%)
+
+ Path #2: setup slack is 1.834(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.834
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
+
+ ioclk1
+ ioclk1
+ rise-rise
+ -0.003
+ 4.916
+ 4.519
+ 0.394
+ 2.500
+ 0.408
+ 0.408 (100.0%)
+ 0.000 (0.0%)
+
+ Path #3: setup slack is 1.834(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.834
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
+
+ ioclk0
+ ioclk0
+ rise-rise
+ -0.003
+ 4.916
+ 4.519
+ 0.394
+ 2.500
+ 0.408
+ 0.408 (100.0%)
+ 0.000 (0.0%)
+
+ Path #4: setup slack is 1.834(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.834
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
+
+ ioclk0
+ ioclk0
+ rise-rise
+ -0.003
+ 4.916
+ 4.519
+ 0.394
+ 2.500
+ 0.408
+ 0.408 (100.0%)
+ 0.000 (0.0%)
+
+ Path #5: setup slack is 1.834(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 1.834
+ 0
+ 8
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
+
+ ioclk0
+ ioclk0
+ rise-rise
+ -0.003
+ 4.916
+ 4.519
+ 0.394
+ 2.500
+ 0.408
+ 0.408 (100.0%)
+ 0.000 (0.0%)
+
+ Path #6: setup slack is 1.834(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 2.129
+ 5
+ 11
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE
+
+ clk_200m
+ clk_200m
+ rise-rise
+ -0.001
+ 3.732
+ 3.432
+ 0.299
+ 5.000
+ 2.144
+ 1.464 (68.3%)
+ 0.680 (31.7%)
+
+ Path #7: setup slack is 2.129(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 2.129
+ 5
+ 11
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE
+
+ clk_200m
+ clk_200m
+ rise-rise
+ -0.001
+ 3.732
+ 3.432
+ 0.299
+ 5.000
+ 2.144
+ 1.464 (68.3%)
+ 0.680 (31.7%)
+
+ Path #8: setup slack is 2.129(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 2.129
+ 5
+ 11
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK
+ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CE
+
+ clk_200m
+ clk_200m
+ rise-rise
+ -0.001
+ 3.732
+ 3.432
+ 0.299
+ 5.000
+ 2.144
+ 1.464 (68.3%)
+ 0.680 (31.7%)
+
+ Path #9: setup slack is 2.129(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 2.488
+ 0
+ 3
+ u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+ u_zoom_image/mult_image_g1_0/N2/gopapm/X[3]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ -0.142
+ 5.994
+ 5.520
+ 0.332
+ 6.736
+ 2.225
+ 0.822 (36.9%)
+ 1.403 (63.1%)
+
+ Path #10: setup slack is 2.488(MET)
+
+
+
+
+
+
+
+
+
+
+
+ 2.493
+ 0
+ 3
+ u_zoom_image/mult_fra1_0/N2/gopapm/CLK
+ u_zoom_image/mult_image_g1_0/N2/gopapm/X[0]
+
+ clk_1080p60Hz
+ clk_1080p60Hz
+ rise-rise
+ -0.142
+ 5.994
+ 5.520
+ 0.332
+ 6.736
+ 2.220
+ 0.822 (37.0%)
+ 1.398 (63.0%)
+
+ Path #11: setup slack is 2.493(MET)
+
+
+
+
+
+
+
+
+
-
-
-
Entity: zoom_image_v1
-
+
- File: zoom_image_v1.v +
Diagram
+Generics
+| Generic name | +Type | +Value | +Description | +
|---|---|---|---|
| IMAGE_SIZE | ++ | 11 | ++ |
| FRA_WIDTH | ++ | 7 | ++ |
| IMAGE_W | ++ | 1920 | ++ |
| IMAGE_H | ++ | 1080 | ++ |
Ports
+| Port name | +Direction | +Type | +Description | +
|---|---|---|---|
| clk | +input | ++ | 时钟 | +
| rst | +input | ++ | 复位 | +
| zoom_en | +input | ++ | 缩放使能 | +
| hdmi_out_en | +input | ++ | HDMI输出使能 | +
| data_half_en | +input | ++ | 数据减半使能 | +
| fifo_full | +input | ++ | 输出端FIFO 满信号 | +
| zoom_num | +input | +[3+FRA_WIDTH-1:0] | +缩放系数 | +
| data_in_valid | +input | ++ | 数据输入-有效 | +
| data_in | +input | +[15:0] | +数据输入-数据 | +
| data_out_valid | +output | ++ | 数据输出-有效 | +
| data_out | +output | +[15:0] | +数据输出-数据 | +
| imag_addr_valid | +output | ++ | 数据读取地址-有效 | +
| imag_addr | +output | +[IMAGE_SIZE-1:0] | +数据读取地址-地址 | +
| zoom_done | +output | ++ | 一帧画面缩放完成 | +
Signals
+| Name | +Type | +Description | +
|---|---|---|
| zoom_sta | +reg [6:0] | ++ |
| cnt_w | +reg signed [IMAGE_SIZE-1:0] | ++ |
| cnt_h | +reg signed [IMAGE_SIZE-1:0] | ++ |
| mult_cnt_h | +reg signed [IMAGE_SIZE-1:0] | ++ |
| judge_cnt_h | +reg signed [IMAGE_SIZE+3-1:0] | ++ |
| judge_cnt_h_valid | +reg | ++ |
| ram_idle | +reg | ++ |
| no_need_rd_ddr | +reg | ++ |
| no_one_need_rd_ddr | +reg | ++ |
| record_ram[0:3] | +reg | ++ |
| delay_cnt | +reg [2:0] | ++ |
| param_delay | +reg [3:0] | ++ |
| cnt_record_ram | +reg [2:0] | ++ |
| record_ram_valid | +reg | ++ |
| data_in0 | +reg [15:0] | ++ |
| data_in1 | +reg [15:0] | ++ |
| data_in2 | +reg [15:0] | ++ |
| data_in3 | +reg [15:0] | ++ |
| coe_valid | +reg [6:0] | ++ |
| data_in_valid0 | +reg | ++ |
| data_in_valid1 | +reg | ++ |
| data_in_valid2 | +reg | ++ |
| data_in_valid3 | +reg | ++ |
| rd_one_ram | +reg | ++ |
| fifo_full0 | +reg | ++ |
| mult_w | +wire [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| mult_h | +wire [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| store_mult_h | +reg signed [IMAGE_SIZE+3-1:0] | ++ |
| store_mult_h0 | +reg signed [IMAGE_SIZE+3-1:0] | ++ |
| ram_idle0 | +reg | ++ |
| ram_idle1 | +reg | ++ |
| zoom_sta_param | +reg | ++ |
| ram_ch | +reg [1:0] | ++ |
| zoom_num0 | +reg [3+FRA_WIDTH-1:0] | ++ |
| wr_ram_done | +reg | ++ |
| wr_addr0 | +reg [IMAGE_SIZE - 1:0] | ++ |
| wr_addr1 | +reg [IMAGE_SIZE - 1:0] | ++ |
| wr_addr2 | +reg [IMAGE_SIZE - 1:0] | ++ |
| wr_addr3 | +reg [IMAGE_SIZE - 1:0] | ++ |
| rd_addr | +reg [IMAGE_SIZE - 1:0] | ++ |
| rd_addr0 | +reg [IMAGE_SIZE - 1:0] | ++ |
| rd_addr1 | +reg [IMAGE_SIZE - 1:0] | ++ |
| rd_addr2 | +reg [IMAGE_SIZE - 1:0] | ++ |
| rd_addr3 | +reg [IMAGE_SIZE - 1:0] | ++ |
| doutb0 | +wire [15:0] | ++ |
| doutb0_0 | +wire [15:0] | ++ |
| doutb1 | +wire [15:0] | ++ |
| doutb1_0 | +wire [15:0] | ++ |
| doutb2 | +wire [15:0] | ++ |
| doutb2_0 | +wire [15:0] | ++ |
| doutb3 | +wire [15:0] | ++ |
| doutb3_0 | +wire [15:0] | ++ |
| ram_sta | +reg [3:0] | ++ |
| data_half_valid | +reg | ++ |
| data_half_valid0 | +reg | ++ |
| data_half_valid1 | +reg | ++ |
| imag_addr_valid0 | +reg | ++ |
| imag_addr_valid1 | +reg | ++ |
| imag_addr0 | +reg signed [IMAGE_SIZE+FRA_WIDTH-1:0] | ++ |
| mult_h1 | +wire [IMAGE_SIZE-1:0] | ++ |
| mult_h2 | +wire [IMAGE_SIZE+3-1:0] | ++ |
| store_addr_add_one | +wire [IMAGE_SIZE+3-1:0] | ++ |
| store_addr | +reg signed [IMAGE_SIZE+3-1:0] | ++ |
| mult_h0 | +reg signed [IMAGE_SIZE+3-1:0] | ++ |
| zoom_sta_param0 | +reg | ++ |
| zoom_sta_param1 | +reg | ++ |
| addr_sta | +reg [4:0] | ++ |
| data_half_en0 | +reg | ++ |
| imag_addr1 | +reg signed [IMAGE_SIZE-1:0] | ++ |
| add_imag_addr = IMAGE_H / 2 | +wire [IMAGE_SIZE-1:0] | ++ |
| image_w0 | +reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| image_w1 | +reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| image_w2 | +reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| image_h0 | +reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| image_h1 | +reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| image_h2 | +reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| image_w2_unsigned | +wire [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| image_h2_unsigned | +wire [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| zoom_num1 | +reg [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| add_image_w | +wire [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| add_image_h | +wire [IMAGE_SIZE+FRA_WIDTH+3-1:0] | ++ |
| ram_ch0 | +reg [1:0] | ++ |
| ram_ch1 | +reg [1:0] | ++ |
| ram_ch2 | +reg [1:0] | ++ |
| rd_data | +reg [16*2-1:0] | ++ |
| rd_data0 | +reg [16*2-1:0] | ++ |
| rd_data_0 | +reg [16*2-1:0] | ++ |
| rd_data0_0 | +reg [16*2-1:0] | ++ |
| image_w2_coe | +reg [6:0] | ++ |
| image_w2_coe0 | +reg [6:0] | ++ |
| image_w2_coe1 | +reg [6:0] | ++ |
| image_w2_coe2 | +reg [6:0] | ++ |
| image_w2_coe3 | +reg [6:0] | ++ |
| image_h2_coe | +reg [6:0] | ++ |
| image_h2_coe0 | +reg [6:0] | ++ |
| image_h2_coe1 | +reg [6:0] | ++ |
| image_h2_coe2 | +reg [6:0] | ++ |
| coe0 | +reg [7:0] | ++ |
| coe1 | +reg [7:0] | ++ |
| coe2 | +reg [7:0] | ++ |
| coe3 | +reg [7:0] | ++ |
| coe0_0 | +reg [7:0] | ++ |
| coe1_0 | +reg [7:0] | ++ |
| coe2_0 | +reg [7:0] | ++ |
| coe3_0 | +reg [7:0] | ++ |
| image_valid[7:0] | +reg [2:0] | ++ |
| image_w_valid | +reg [1:0] | ++ |
| image_h_valid | +reg [1:0] | ++ |
| image_blank_valid | +reg | ++ |
| coe_mult_p0 | +wire [15:0] | ++ |
| coe_mult_p1 | +wire [15:0] | ++ |
| coe_mult_p0_0 | +wire [15:0] | ++ |
| coe_mult_p1_0 | +wire [15:0] | ++ |
| mult_image0 [5:0] | +wire [14:0] | ++ |
| mult_image0_0[5:0] | +wire [14:0] | ++ |
| mult_image1 [2:0] | +reg [15:0] | ++ |
| mult_image2 [2:0] | +reg [15:0] | ++ |
| mult_image1_0[2:0] | +reg [15:0] | ++ |
| data_out0 | +wire [15:0] | ++ |
| data_out1 | +reg [15:0] | ++ |
| data_out_valid1 | +reg | ++ |
| data_out2 | +reg [15:0] | ++ |
| data_out_valid2 | +reg | ++ |
| hdmi_out_en0 | +reg | ++ |
| cnt_ww | +reg [IMAGE_SIZE-1:0] | ++ |
| cnt_hh | +reg [IMAGE_SIZE-1:0] | ++ |
| hdmi_out_en1 | +reg | ++ |
Constants
+| Name | +Type | +Value | +Description | +
|---|---|---|---|
| IDLE | ++ | 7'b000_0001 | ++ |
| JUDGE | ++ | 7'b000_0010 | ++ |
| PARAM | ++ | 7'b000_0100 | ++ |
| WAIT0 | ++ | 7'b000_1000 | ++ |
| WAIT1 | ++ | 7'b001_0000 | ++ |
| ZOOM | ++ | 7'b010_0000 | ++ |
| BLANK | ++ | 7'b100_0000 | ++ |
| FraWidthPower | ++ | 1 << FRA_WIDTH | ++ |
| MultDelay | ++ | 1 | ++ |
Processes
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
-
+
- unnamed: ( @(posedge clk) ) +
Type: always
Instantiations
-
+
- u_image_w_mult: mult_image_w +
-
+
- u_image_h_mult: mult_image_w +
-
+
- zoom_ram0: zoom_ram +
-
+
- zoom_ram1: zoom_ram +
-
+
- zoom_ram2: zoom_ram +
-
+
- zoom_ram3: zoom_ram +
-
+
- zoom_ram0_0: zoom_ram +
-
+
- zoom_ram1_0: zoom_ram +
-
+
- zoom_ram2_0: zoom_ram +
-
+
- zoom_ram3_0: zoom_ram +
-
+
- mult_fra0: mult_fra0 +
-
+
- mult_fra1: mult_fra0 +
-
+
- mult_fra0_0: mult_fra0 +
-
+
- mult_fra1_0: mult_fra0 +
State machines
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + + \ No newline at end of file diff --git a/project/compile/cmr.db b/project/compile/cmr.db index ddbe5f4..c2aad20 100644 --- a/project/compile/cmr.db +++ b/project/compile/cmr.db @@ -413,9 +413,9 @@ RAM(GB)