-
Notifications
You must be signed in to change notification settings - Fork 67
/
core.h
262 lines (226 loc) · 8 KB
/
core.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
/*****************************************************************************
* McPAT
* SOFTWARE LICENSE AGREEMENT
* Copyright 2012 Hewlett-Packard Development Company, L.P.
* All Rights Reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
*
***************************************************************************/
#ifndef CORE_H_
#define CORE_H_
#include "XML_Parse.h"
#include "logic.h"
#include "parameter.h"
#include "array.h"
#include "interconnect.h"
#include "basic_components.h"
#include "sharedcache.h"
class BranchPredictor :public Component {
public:
ParseXML *XML;
int ithCore;
InputParameter interface_ip;
CoreDynParam coredynp;
double clockRate,executionTime;
double scktRatio, chip_PR_overhead, macro_PR_overhead;
ArrayST * globalBPT;
ArrayST * localBPT;
ArrayST * L1_localBPT;
ArrayST * L2_localBPT;
ArrayST * chooser;
ArrayST * RAS;
bool exist;
BranchPredictor(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exsit=true);
void computeEnergy(bool is_tdp=true);
void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
~BranchPredictor();
};
class InstFetchU :public Component {
public:
ParseXML *XML;
int ithCore;
InputParameter interface_ip;
CoreDynParam coredynp;
double clockRate,executionTime;
double scktRatio, chip_PR_overhead, macro_PR_overhead;
enum Cache_policy cache_p;
InstCache icache;
ArrayST * IB;
ArrayST * BTB;
BranchPredictor * BPT;
inst_decoder * ID_inst;
inst_decoder * ID_operand;
inst_decoder * ID_misc;
bool exist;
InstFetchU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exsit=true);
void computeEnergy(bool is_tdp=true);
void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
~InstFetchU();
};
class SchedulerU :public Component {
public:
ParseXML *XML;
int ithCore;
InputParameter interface_ip;
CoreDynParam coredynp;
double clockRate,executionTime;
double scktRatio, chip_PR_overhead, macro_PR_overhead;
double Iw_height, fp_Iw_height,ROB_height;
ArrayST * int_inst_window;
ArrayST * fp_inst_window;
ArrayST * ROB;
selection_logic * instruction_selection;
bool exist;
SchedulerU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
void computeEnergy(bool is_tdp=true);
void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
~SchedulerU();
};
class RENAMINGU :public Component {
public:
ParseXML *XML;
int ithCore;
InputParameter interface_ip;
double clockRate,executionTime;
CoreDynParam coredynp;
ArrayST * iFRAT;
ArrayST * fFRAT;
ArrayST * iRRAT;
ArrayST * fRRAT;
ArrayST * ifreeL;
ArrayST * ffreeL;
dep_resource_conflict_check * idcl;
dep_resource_conflict_check * fdcl;
ArrayST * RAHT;//register alias history table Used to store GC
bool exist;
RENAMINGU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, const CoreDynParam & dyn_p_, bool exist_=true);
void computeEnergy(bool is_tdp=true);
void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
~RENAMINGU();
};
class LoadStoreU :public Component {
public:
ParseXML *XML;
int ithCore;
InputParameter interface_ip;
CoreDynParam coredynp;
enum Cache_policy cache_p;
double clockRate,executionTime;
double scktRatio, chip_PR_overhead, macro_PR_overhead;
double lsq_height;
DataCache dcache;
ArrayST * LSQ;//it is actually the store queue but for inorder processors it serves as both loadQ and StoreQ
ArrayST * LoadQ;
bool exist;
LoadStoreU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
void computeEnergy(bool is_tdp=true);
void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
~LoadStoreU();
};
class MemManU :public Component {
public:
ParseXML *XML;
int ithCore;
InputParameter interface_ip;
CoreDynParam coredynp;
double clockRate,executionTime;
double scktRatio, chip_PR_overhead, macro_PR_overhead;
ArrayST * itlb;
ArrayST * dtlb;
bool exist;
MemManU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
void computeEnergy(bool is_tdp=true);
void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
~MemManU();
};
class RegFU :public Component {
public:
ParseXML *XML;
int ithCore;
InputParameter interface_ip;
CoreDynParam coredynp;
double clockRate,executionTime;
double scktRatio, chip_PR_overhead, macro_PR_overhead;
double int_regfile_height, fp_regfile_height;
ArrayST * IRF;
ArrayST * FRF;
ArrayST * RFWIN;
bool exist;
RegFU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_,const CoreDynParam & dyn_p_, bool exist_=true);
void computeEnergy(bool is_tdp=true);
void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
~RegFU();
};
class EXECU :public Component {
public:
ParseXML *XML;
int ithCore;
InputParameter interface_ip;
double clockRate,executionTime;
double scktRatio, chip_PR_overhead, macro_PR_overhead;
double lsq_height;
CoreDynParam coredynp;
RegFU * rfu;
SchedulerU * scheu;
FunctionalUnit * fp_u;
FunctionalUnit * exeu;
FunctionalUnit * mul;
interconnect * int_bypass;
interconnect * intTagBypass;
interconnect * int_mul_bypass;
interconnect * intTag_mul_Bypass;
interconnect * fp_bypass;
interconnect * fpTagBypass;
Component bypass;
bool exist;
EXECU(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_, double lsq_height_,const CoreDynParam & dyn_p_, bool exist_=true);
void computeEnergy(bool is_tdp=true);
void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
~EXECU();
};
class Core :public Component {
public:
ParseXML *XML;
int ithCore;
InputParameter interface_ip;
double clockRate,executionTime;
double scktRatio, chip_PR_overhead, macro_PR_overhead;
InstFetchU * ifu;
LoadStoreU * lsu;
MemManU * mmu;
EXECU * exu;
RENAMINGU * rnu;
Pipeline * corepipe;
UndiffCore * undiffCore;
SharedCache * l2cache;
CoreDynParam coredynp;
//full_decoder inst_decoder;
//clock_network clockNetwork;
Core(ParseXML *XML_interface, int ithCore_, InputParameter* interface_ip_);
void set_core_param();
void computeEnergy(bool is_tdp=true);
void displayEnergy(uint32_t indent = 0,int plevel = 100, bool is_tdp=true);
~Core();
};
#endif /* CORE_H_ */