Wrong compilation order when using VHDL configuration inside VHDL configuration.

[aabraathen]

The MC8051 free software MCU uses configuration inside configuration. Ex:

addsub_core_struc_cfg.vhd:

configuration addsub_core_struc_cfg of addsub_core is
  for struc 
    for gen_smorequ_four
      for addsub_ovcy_1 : addsub_ovcy
        use configuration work.addsub_ovcy_rtl_cfg;
      end for;
    end for;
    for gen_greater_four
      for gen_addsub
        for gen_nibble_addsub
  	  for all : addsub_cy
            use configuration work.addsub_cy_rtl_cfg;
          end for;
        end for;
        for gen_last_addsub
  	  for all : addsub_ovcy
            use configuration work.addsub_ovcy_rtl_cfg;
          end for;
        end for;
      end for;
    end for;
  end for;
end addsub_core_struc_cfg;

addsub_cy_rtl_cfg

configuration addsub_ovcy_rtl_cfg of addsub_ovcy is

  for rtl
    
  end for;

end addsub_ovcy_rtl_cfg;

The compilation order HDLregression makes is not correct.
line 274 | |--- C:\Users\mrbra\Git\Remrent\verification\design\coca\lib-RR\buildingblocks\modules\mc8051\src\addsub_core_struc_cfg.vhd (rc)
line 292 | |--- C:\Users\mrbra\Git\Remrent\verification\design\coca\lib-RR\buildingblocks\modules\mc8051\src\addsub_cy_rtl_cfg.vhd (rc)

If I run multiple times without using -c the the compilation works the second time, because the compilation from the previous run is used, when compiling the addsub_core_struc_cfg.

[aabraathen]

Is there any way to force compilation order as a temporary fix?