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Add panlee-zw3d95ce01s-tr
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fvanroie committed Sep 13, 2023
1 parent c053421 commit da1305d
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Showing 2 changed files with 13 additions and 7 deletions.
2 changes: 1 addition & 1 deletion .github/workflows/build.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ jobs:
- out: makerfabs
env: "makerfabs-tft35-cap_4MB -e makerfabs-tft35-cap_16MB -e makerfabs-s3-tft35-spi -e makerfabs-s3-tft40-rgb -e makerfabs-s3-tft43-rgb"
- out: panlee
env: "panlee-zw3d95ce01s-ar-4848_16MB -e panlee-zw3d95ce01s-ur-4848_16MB"
env: "panlee-zw3d95ce01s-ar-4848_16MB -e panlee-zw3d95ce01s-ur-4848_16MB -e panlee-zw3d95ce01s-tr-4848_16MB"
- out: seeed-studios
env: "sensecap-indicator-d1_8MB"
- out: sunton
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18 changes: 12 additions & 6 deletions user_setups/esp32s3/zw3d95ce01s_ar.ini
Original file line number Diff line number Diff line change
Expand Up @@ -23,13 +23,7 @@ build_flags =
-D TFT_WIDTH=480
-D TFT_HEIGHT=480
-D TFT_HSYNC_POLARITY=1
-D TFT_HSYNC_FRONT_PORCH=10
-D TFT_HSYNC_PULSE_WIDTH=8
-D TFT_HSYNC_BACK_PORCH=50
-D TFT_VSYNC_POLARITY=1
-D TFT_VSYNC_FRONT_PORCH=10
-D TFT_VSYNC_PULSE_WIDTH=8
-D TFT_VSYNC_BACK_PORCH=20
;-D TFT_PCLK_ACTIVE_NEG=1
;-D TFT_PREFER_SPEED=9000000
-D TFT_AUTO_FLUSH=1
Expand Down Expand Up @@ -81,6 +75,12 @@ build_flags =
-D TFT_R3=46 ; LCD RGB interface D14
-D TFT_R4=9 ; LCD RGB interface D15
-D TFT_BCKL=4 ; LCD backlight control, high level enable
-D TFT_HSYNC_FRONT_PORCH=10
-D TFT_HSYNC_PULSE_WIDTH=8
-D TFT_HSYNC_BACK_PORCH=50
-D TFT_VSYNC_FRONT_PORCH=10
-D TFT_VSYNC_PULSE_WIDTH=8
-D TFT_VSYNC_BACK_PORCH=20

[env:panlee-zw3d95ce01s-ar-4848_16MB]
extends = panlee-zw3d95ce01s, flash_16mb
Expand Down Expand Up @@ -118,6 +118,12 @@ build_flags =
-D TFT_R3=1 ; LCD RGB interface D14
-D TFT_R4=15 ; LCD RGB interface D15
-D TFT_BCKL=45 ; LCD backlight control, high level enable
-D TFT_HSYNC_FRONT_PORCH=10
-D TFT_HSYNC_PULSE_WIDTH=8
-D TFT_HSYNC_BACK_PORCH=50
-D TFT_VSYNC_FRONT_PORCH=10
-D TFT_VSYNC_PULSE_WIDTH=8
-D TFT_VSYNC_BACK_PORCH=20
-D I2S_MCLK=38 ; I2S bus MCLK
-D I2S_SCLK=48 ; I2S bus SCLK
-D I2S_LRCK=47 ; I2S bus LRCK
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