JTAG interface

[aviator00]

I want to test the project on a ZedBoard. How can work if the JTAG signals are all 0? where is defined DMIDirectTAP? How can I modify the code making JTAG external?

[GregAC]

Currently it uses the Xilinx BSCANE2 primitive, see https://github.com/GregAC/ibex_super_system/blob/main/vendor/pulp_riscv_dbg/src/dmi_bscane_tap.sv

To use an external JTAG probe you need to switch to using the normal JTAG tap (https://github.com/GregAC/ibex_super_system/blob/main/vendor/pulp_riscv_dbg/src/dmi_jtag_tap.sv). To do this alter the https://github.com/GregAC/ibex_super_system/blob/main/pulp_riscv_dbg.core fusesoc core file to use dmi_jtag_tap.sv rather than dmi_bscane_tap.sv.

This is the line to alter:

ibex_super_system/pulp_riscv_dbg.core

Line 22 in 3ae1363

- vendor/pulp_riscv_dbg/src/dmi_bscane_tap.sv

Then the TAP instantiation in dm_top:

ibex_super_system/rtl/system/dm_top.sv

Lines 235 to 258 in 3ae1363

	dmi_jtag #(
	.IdcodeValue (IdcodeValue)
	) dap (
	.clk_i (clk_i),
	.rst_ni (rst_ni),
	.testmode_i (testmode_i),
	.dmi_rst_no (dmi_rst_n),
	.dmi_req_o (dmi_req),
	.dmi_req_valid_o (dmi_req_valid),
	.dmi_req_ready_i (dmi_req_ready),
	.dmi_resp_i (dmi_rsp ),
	.dmi_resp_ready_o (dmi_rsp_ready),
	.dmi_resp_valid_i (dmi_rsp_valid),
	//JTAG
	.tck_i (1'b0),
	.tms_i (1'b0),
	.trst_ni (1'b0),
	.td_i (1'b0),
	.td_o (),
	.tdo_oe_o ()
	);

needs it's JTAG signals wiring out to the top level so they can be connected up appropriately (don't forget synchronizers for external inputs).

I don't think DMIDirectTAP is defined anywhere. It's just a left over bit of code as I copied the DM setup out of OpenTitan.

[aviator00]

Thank you, very clear. I tried successfully with Xilinx BSCANE2 primitive present also on the Zedboard at the moment, because it's easier, copying some openocd configurations from others.