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This repository has been archived by the owner on Sep 6, 2024. It is now read-only.

Create stream down converter #14

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rowanG077 opened this issue Feb 29, 2024 · 0 comments · Fixed by #15
Closed

Create stream down converter #14

rowanG077 opened this issue Feb 29, 2024 · 0 comments · Fixed by #15
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@Akribes @JLaumen
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Clock domains We want to be able to use FPGA internal clock with ethernet

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@rowanG077
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Feature description
We want to make a converter that is able to translate an n*8-bit data stream to a 8-bit data stream.

Expected behaviour

Expected steps
Implement the comments in the review of rowanG077/clash-ethernet#27
This is a big pull request, cherry-pick the needed parts

Additional Context
@Akribes Akribes mentioned this issue Feb 29, 2024
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@Akribes Akribes linked a pull request Feb 29, 2024 that will close this issue
Create stream down converter #15
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@JLaumen JLaumen self-assigned this Mar 1, 2024
@Baublesaurus Baublesaurus added the Clock domains We want to be able to use FPGA internal clock with ethernet label Mar 1, 2024
This was referenced Mar 22, 2024
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@Akribes Akribes

@JLaumen JLaumen

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Clock domains We want to be able to use FPGA internal clock with ethernet
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Successfully merging a pull request may close this issue.

Create stream down converter GiPHouse/qbaylogic-clash-based-macipudp-stack-spring24
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@rowanG077 @Akribes @Baublesaurus @JLaumen