diff --git a/lgc/elfLinker/FetchShader.cpp b/lgc/elfLinker/FetchShader.cpp
index 8d3cb1f025..0a6c8ec277 100644
--- a/lgc/elfLinker/FetchShader.cpp
+++ b/lgc/elfLinker/FetchShader.cpp
@@ -296,8 +296,12 @@ Function *FetchShader::createFetchFunc() {
   // Create the function. Mark SGPR inputs as "inreg".
   Function *func = Function::Create(funcTy, GlobalValue::ExternalLinkage, getGlueShaderName(), module);
   func->setCallingConv(m_vsEntryRegInfo.callingConv);
-  for (unsigned i = 0; i != m_vsEntryRegInfo.sgprCount; ++i)
-    func->getArg(i)->addAttr(Attribute::InReg);
+  for (unsigned i = 0; i != m_vsEntryRegInfo.sgprCount + m_vsEntryRegInfo.vgprCount; ++i) {
+    Argument *arg = func->getArg(i);
+    if (i < m_vsEntryRegInfo.sgprCount)
+      arg->addAttr(Attribute::InReg);
+    arg->addAttr(Attribute::NoUndef);
+  }
 
   // Add mnemonic names to input args.
   if (m_vsEntryRegInfo.callingConv == CallingConv::AMDGPU_HS)
diff --git a/lgc/include/lgc/state/ShaderStage.h b/lgc/include/lgc/state/ShaderStage.h
index 5ee55b12b2..9c2d30d084 100644
--- a/lgc/include/lgc/state/ShaderStage.h
+++ b/lgc/include/lgc/state/ShaderStage.h
@@ -77,6 +77,11 @@ bool isShaderEntryPoint(const llvm::Function *func);
 // Gets name string of the abbreviation for the specified shader stage
 const char *getShaderStageAbbreviation(ShaderStage shaderStage);
 
+enum AddFunctionArgsFlag : unsigned {
+  AddFunctionArgsAppend = 0x1,
+  AddFunctionArgsMaybeUndef = 0x2,
+};
+
 // Add args to a function. This creates a new function with the added args, then moves everything from the old function
 // across to it.
 // If this changes the return type, then all the return instructions will be invalid.
@@ -89,7 +94,7 @@ const char *getShaderStageAbbreviation(ShaderStage shaderStage);
 // @param append : Append new arguments if true, prepend new arguments if false
 // @returns : The new function
 llvm::Function *addFunctionArgs(llvm::Function *oldFunc, llvm::Type *retTy, llvm::ArrayRef<llvm::Type *> argTys,
-                                llvm::ArrayRef<std::string> argNames, uint64_t inRegMask = 0, bool append = false);
+                                llvm::ArrayRef<std::string> argNames, uint64_t inRegMask = 0, unsigned flags = 0);
 
 // Get the ABI-mandated entry-point name for a shader stage
 //
diff --git a/lgc/patch/MeshTaskShader.cpp b/lgc/patch/MeshTaskShader.cpp
index d0fd411c7c..93ba2bb0b4 100644
--- a/lgc/patch/MeshTaskShader.cpp
+++ b/lgc/patch/MeshTaskShader.cpp
@@ -1632,7 +1632,7 @@ Function *MeshTaskShader::mutateMeshShaderEntryPoint(Function *entryPoint) {
 
     entryPoint = newEntryPoint;
     newEntryPoint = addFunctionArgs(entryPoint, nullptr, {int32Ty, int32Ty, int32Ty, int32Ty, int32Ty, int32Ty},
-                                    VgprInputNames, 0, true);
+                                    VgprInputNames, 0, AddFunctionArgsAppend);
 
     assert(entryPoint->use_empty());
     entryPoint->eraseFromParent();
@@ -1649,7 +1649,7 @@ Function *MeshTaskShader::mutateMeshShaderEntryPoint(Function *entryPoint) {
   //   +-----------------------+-----------------------+-----------------------+
   if (m_gfxIp.major >= 11) {
     entryPoint = newEntryPoint;
-    newEntryPoint = addFunctionArgs(entryPoint, nullptr, int32Ty, {"localInvocationId"}, 0, true);
+    newEntryPoint = addFunctionArgs(entryPoint, nullptr, int32Ty, {"localInvocationId"}, 0, AddFunctionArgsAppend);
 
     assert(entryPoint->use_empty());
     entryPoint->eraseFromParent();
diff --git a/lgc/patch/NggPrimShader.cpp b/lgc/patch/NggPrimShader.cpp
index a0667ea4d1..fa8be62f83 100644
--- a/lgc/patch/NggPrimShader.cpp
+++ b/lgc/patch/NggPrimShader.cpp
@@ -564,6 +564,7 @@ Function *NggPrimShader::generate(Function *esMain, Function *gsMain, Function *
     auto argIdx = arg.getArgNo();
     if (inRegMask & (1ull << argIdx))
       arg.addAttr(Attribute::InReg);
+    arg.addAttr(Attribute::NoUndef);
     args.push_back(&arg);
   }
 
@@ -3514,7 +3515,8 @@ void NggPrimShader::splitEs() {
 
   // NOTE: Here, we just mutate original ES to do deferred vertex export. We add vertex position data as an additional
   // argument. This could avoid re-fetching it since we already get the data before NGG culling.
-  auto esVertexExporter = addFunctionArgs(m_esHandlers.main, nullptr, {positionTy}, {"position"});
+  auto esVertexExporter =
+      addFunctionArgs(m_esHandlers.main, nullptr, {positionTy}, {"position"}, 0, AddFunctionArgsMaybeUndef);
   esVertexExporter->setName(NggEsVertexExporter);
 
   position = esVertexExporter->getArg(0); // The first argument is vertex position data
diff --git a/lgc/patch/PatchEntryPointMutate.cpp b/lgc/patch/PatchEntryPointMutate.cpp
index 63c0783489..9a836ee2ae 100644
--- a/lgc/patch/PatchEntryPointMutate.cpp
+++ b/lgc/patch/PatchEntryPointMutate.cpp
@@ -1030,7 +1030,8 @@ void PatchEntryPointMutate::processComputeFuncs(ShaderInputs *shaderInputs, Modu
     } else {
       inRegMask = generateEntryPointArgTys(shaderInputs, origFunc, shaderInputTys, shaderInputNames,
                                            origType->getNumParams(), true);
-      newFunc = addFunctionArgs(origFunc, origType->getReturnType(), shaderInputTys, shaderInputNames, inRegMask, true);
+      newFunc = addFunctionArgs(origFunc, origType->getReturnType(), shaderInputTys, shaderInputNames, inRegMask,
+                                AddFunctionArgsAppend);
       const bool isEntryPoint = isShaderEntryPoint(newFunc);
       newFunc->setCallingConv(isEntryPoint ? CallingConv::AMDGPU_CS : CallingConv::AMDGPU_Gfx);
     }
diff --git a/lgc/patch/ShaderMerger.cpp b/lgc/patch/ShaderMerger.cpp
index 6004a678a8..9fa7155370 100644
--- a/lgc/patch/ShaderMerger.cpp
+++ b/lgc/patch/ShaderMerger.cpp
@@ -332,6 +332,7 @@ Function *ShaderMerger::generateLsHsEntryPoint(Function *lsEntryPoint, Function
     auto argIdx = arg.getArgNo();
     if (inRegMask & (1ull << argIdx))
       arg.addAttr(Attribute::InReg);
+    arg.addAttr(Attribute::NoUndef);
   }
 
   //
@@ -675,6 +676,7 @@ Function *ShaderMerger::generateEsGsEntryPoint(Function *esEntryPoint, Function
     auto argIdx = arg.getArgNo();
     if (inRegMask & (1ull << argIdx))
       arg.addAttr(Attribute::InReg);
+    arg.addAttr(Attribute::NoUndef);
   }
 
   //
diff --git a/lgc/state/ShaderStage.cpp b/lgc/state/ShaderStage.cpp
index 20e8927bf7..77d3417951 100644
--- a/lgc/state/ShaderStage.cpp
+++ b/lgc/state/ShaderStage.cpp
@@ -120,15 +120,17 @@ const char *lgc::getShaderStageAbbreviation(ShaderStage shaderStage) {
 // across to it.
 // If this changes the return type, then all the return instructions will be invalid.
 // This does not erase the old function, as the caller needs to do something with its uses (if any).
+// The added arguments are `noundef` by default.
 //
 // @param oldFunc : Original function
 // @param retTy : New return type, nullptr to use the same as in the original function
 // @param argTys : Types of new args
 // @param inRegMask : Bitmask of which args should be marked "inreg", to be passed in SGPRs
-// @param append : Append new arguments if true, prepend new arguments if false
+// @param flags : Bitwise combination of AddFunctionArgsFlags (or 0)
 // @returns : The new function
 Function *lgc::addFunctionArgs(Function *oldFunc, Type *retTy, ArrayRef<Type *> argTys, ArrayRef<std::string> argNames,
-                               uint64_t inRegMask, bool append) {
+                               uint64_t inRegMask, unsigned flags) {
+  const bool append = flags & AddFunctionArgsAppend;
   // Gather all arg types: first the new ones, then the ones from the original function.
   FunctionType *oldFuncTy = oldFunc->getFunctionType();
   SmallVector<Type *, 8> allArgTys;
@@ -170,13 +172,15 @@ Function *lgc::addFunctionArgs(Function *oldFunc, Type *retTy, ArrayRef<Type *>
   }
 
   // New arguments.
-  AttributeSet emptyAttrSet;
-  AttributeSet inRegAttrSet = emptyAttrSet.addAttribute(oldFunc->getContext(), Attribute::InReg);
+  AttributeSet defaultAttrSet;
+  if (!(flags & AddFunctionArgsMaybeUndef))
+    defaultAttrSet = defaultAttrSet.addAttribute(oldFunc->getContext(), Attribute::NoUndef);
+  AttributeSet inRegAttrSet = defaultAttrSet.addAttribute(oldFunc->getContext(), Attribute::InReg);
   for (unsigned idx = 0; idx != argTys.size(); ++idx)
-    argAttrs.push_back((inRegMask >> idx) & 1 ? inRegAttrSet : emptyAttrSet);
+    argAttrs.push_back((inRegMask >> idx) & 1 ? inRegAttrSet : defaultAttrSet);
   if (!append) {
     // Old arguments.
-    for (unsigned idx = 0; idx != argTys.size(); ++idx)
+    for (unsigned idx = 0; idx != oldFuncTy->getNumParams(); ++idx)
       argAttrs.push_back(oldAttrList.getParamAttrs(idx));
   }
   // Construct new AttributeList and set it on the new function.
@@ -193,20 +197,12 @@ Function *lgc::addFunctionArgs(Function *oldFunc, Type *retTy, ArrayRef<Type *>
   for (unsigned idx = 0; idx != argTys.size(); ++idx) {
     Argument *arg = newFunc->getArg(append ? idx + oldFuncTy->getNumParams() : idx);
     arg->setName(argNames[idx]);
-    if ((inRegMask >> idx) & 1)
-      arg->addAttr(Attribute::InReg);
-    else if (!oldFuncTy->params().empty())
-      arg->removeAttr(Attribute::AttrKind::InReg);
   }
   for (unsigned idx = 0; idx != oldFuncTy->params().size(); ++idx) {
     Argument *arg = newFunc->getArg(append ? idx : idx + argTys.size());
     Argument *oldArg = oldFunc->getArg(idx);
     arg->setName(oldArg->getName());
     oldArg->replaceAllUsesWith(arg);
-    if (oldArg->hasInRegAttr())
-      arg->addAttr(Attribute::InReg);
-    else
-      arg->removeAttr(Attribute::AttrKind::InReg);
   }
 
   return newFunc;
diff --git a/lgc/test/CallLibFromCs-indirect.lgc b/lgc/test/CallLibFromCs-indirect.lgc
index 7eeb691b13..6c1e564ff7 100644
--- a/lgc/test/CallLibFromCs-indirect.lgc
+++ b/lgc/test/CallLibFromCs-indirect.lgc
@@ -2,7 +2,7 @@
 
 ; RUN: lgc -mcpu=gfx1010 -print-after=lgc-patch-entry-point-mutate -o /dev/null 2>&1 - <%s | FileCheck --check-prefixes=CHECK %s
 ; CHECK: IR Dump After Patch LLVM for entry-point mutation
-; CHECK: define dllexport amdgpu_cs void @lgc.shader.CS.main(i32 inreg %globalTable, ptr addrspace(4) inreg %numWorkgroupsPtr, i32 inreg %userdata0, i32 inreg %userdata1, i32 inreg %userdata2, i32 inreg %userdata3, i32 inreg %userdata4, i32 inreg %userdata5, i32 inreg %userdata6, i32 inreg %userdata7, i32 inreg %userdata8, i32 inreg %userdata9, i32 inreg %userdata10, i32 inreg %userdata11, i32 inreg %spillTable, <3 x i32> inreg %WorkgroupId, i32 inreg %MultiDispatchInfo, <3 x i32> %LocalInvocationId) #0 !lgc.shaderstage !7 {
+; CHECK: define dllexport amdgpu_cs void @lgc.shader.CS.main(i32 inreg noundef %globalTable, ptr addrspace(4) inreg noundef %numWorkgroupsPtr, i32 inreg noundef %userdata0, i32 inreg noundef %userdata1, i32 inreg noundef %userdata2, i32 inreg noundef %userdata3, i32 inreg noundef %userdata4, i32 inreg noundef %userdata5, i32 inreg noundef %userdata6, i32 inreg noundef %userdata7, i32 inreg noundef %userdata8, i32 inreg noundef %userdata9, i32 inreg noundef %userdata10, i32 inreg noundef %userdata11, i32 inreg noundef %spillTable, <3 x i32> inreg noundef %WorkgroupId, i32 inreg noundef %MultiDispatchInfo, <3 x i32> noundef %LocalInvocationId) #0 !lgc.shaderstage !7 {
 ; CHECK: call amdgpu_gfx i32 %func_ptr(i32 inreg %globalTable, ptr addrspace(4) inreg %numWorkgroupsPtr, i32 inreg %userdata0, i32 inreg %userdata1, i32 inreg %userdata2, i32 inreg %userdata3, i32 inreg %userdata4, i32 inreg %userdata5, i32 inreg %userdata6, i32 inreg %userdata7, i32 inreg %userdata8, i32 inreg %userdata9, i32 inreg %userdata10, i32 inreg %userdata11, i32 inreg %spillTable, <3 x i32> inreg %WorkgroupId, i32 inreg %MultiDispatchInfo, <3 x i32> %LocalInvocationId)
 ; CHECK: !7 = !{i32 7}
 
diff --git a/lgc/test/CallLibFromCs.lgc b/lgc/test/CallLibFromCs.lgc
index 4ae70ee130..e19d181170 100644
--- a/lgc/test/CallLibFromCs.lgc
+++ b/lgc/test/CallLibFromCs.lgc
@@ -3,7 +3,7 @@
 ; RUN: lgc -mcpu=gfx1010 -print-after=lgc-patch-entry-point-mutate -o /dev/null 2>&1 - <%s | FileCheck --check-prefixes=CHECK %s
 ; CHECK: IR Dump After Patch LLVM for entry-point mutation
 ; CHECK: declare amdgpu_gfx i32 @compute_library_func() #0
-; CHECK: define dllexport amdgpu_cs void @lgc.shader.CS.main(i32 inreg %globalTable, ptr addrspace(4) inreg %numWorkgroupsPtr, i32 inreg %userdata0, i32 inreg %userdata1, i32 inreg %userdata2, i32 inreg %userdata3, i32 inreg %userdata4, i32 inreg %userdata5, i32 inreg %userdata6, i32 inreg %userdata7, i32 inreg %userdata8, i32 inreg %userdata9, i32 inreg %userdata10, i32 inreg %userdata11, i32 inreg %spillTable, <3 x i32> inreg %WorkgroupId, i32 inreg %MultiDispatchInfo, <3 x i32> %LocalInvocationId) #1 !lgc.shaderstage !7 {
+; CHECK: define dllexport amdgpu_cs void @lgc.shader.CS.main(i32 inreg noundef %globalTable, ptr addrspace(4) inreg noundef %numWorkgroupsPtr, i32 inreg noundef %userdata0, i32 inreg noundef %userdata1, i32 inreg noundef %userdata2, i32 inreg noundef %userdata3, i32 inreg noundef %userdata4, i32 inreg noundef %userdata5, i32 inreg noundef %userdata6, i32 inreg noundef %userdata7, i32 inreg noundef %userdata8, i32 inreg noundef %userdata9, i32 inreg noundef %userdata10, i32 inreg noundef %userdata11, i32 inreg noundef %spillTable, <3 x i32> inreg noundef %WorkgroupId, i32 inreg noundef %MultiDispatchInfo, <3 x i32> noundef %LocalInvocationId) #1 !lgc.shaderstage !7 {
 ; CHECK: call amdgpu_gfx i32 @compute_library_func(i32 inreg %globalTable, ptr addrspace(4) inreg %numWorkgroupsPtr, i32 inreg %userdata0, i32 inreg %userdata1, i32 inreg %userdata2, i32 inreg %userdata3, i32 inreg %userdata4, i32 inreg %userdata5, i32 inreg %userdata6, i32 inreg %userdata7, i32 inreg %userdata8, i32 inreg %userdata9, i32 inreg %userdata10, i32 inreg %userdata11, i32 inreg %spillTable, <3 x i32> inreg %WorkgroupId, i32 inreg %MultiDispatchInfo, <3 x i32> %LocalInvocationId)
 ; CHECK: !7 = !{i32 7}
 
diff --git a/lgc/test/CsComputeLibrary.lgc b/lgc/test/CsComputeLibrary.lgc
index 628aec321e..7d81b2f06c 100644
--- a/lgc/test/CsComputeLibrary.lgc
+++ b/lgc/test/CsComputeLibrary.lgc
@@ -2,10 +2,10 @@
 
 ; RUN: lgc -mcpu=gfx1010 -print-after=lgc-patch-entry-point-mutate -print-after=lgc-patch-prepare-pipeline-abi -print-after=lgc-patch-setup-target-features -o /dev/null 2>&1 - <%s | FileCheck --check-prefixes=CHECK %s
 ; CHECK: IR Dump After Patch LLVM for entry-point mutation
-; CHECK: define amdgpu_gfx void @func(i32 inreg %globalTable, ptr addrspace(4) inreg %numWorkgroupsPtr, i32 inreg %userdata0, i32 inreg %userdata1, i32 inreg %userdata2, i32 inreg %userdata3, i32 inreg %userdata4, i32 inreg %userdata5, i32 inreg %userdata6, i32 inreg %userdata7, i32 inreg %userdata8, i32 inreg %userdata9, i32 inreg %userdata10, i32 inreg %userdata11, i32 inreg %spillTable, <3 x i32> inreg %WorkgroupId, i32 inreg %MultiDispatchInfo, <3 x i32> %LocalInvocationId) #0 !lgc.shaderstage !7 {
+; CHECK: define amdgpu_gfx void @func(i32 inreg noundef %globalTable, ptr addrspace(4) inreg noundef %numWorkgroupsPtr, i32 inreg noundef %userdata0, i32 inreg noundef %userdata1, i32 inreg noundef %userdata2, i32 inreg noundef %userdata3, i32 inreg noundef %userdata4, i32 inreg noundef %userdata5, i32 inreg noundef %userdata6, i32 inreg noundef %userdata7, i32 inreg noundef %userdata8, i32 inreg noundef %userdata9, i32 inreg noundef %userdata10, i32 inreg noundef %userdata11, i32 inreg noundef %spillTable, <3 x i32> inreg noundef %WorkgroupId, i32 inreg noundef %MultiDispatchInfo, <3 x i32> noundef %LocalInvocationId) #0 !lgc.shaderstage !7 {
 ; CHECK: !7 = !{i32 7}
 ; CHECK: IR Dump After Patch LLVM for preparing pipeline ABI
-; CHECK: define amdgpu_gfx void @func(i32 inreg %globalTable, ptr addrspace(4) inreg %numWorkgroupsPtr, i32 inreg %userdata0, i32 inreg %userdata1, i32 inreg %userdata2, i32 inreg %userdata3, i32 inreg %userdata4, i32 inreg %userdata5, i32 inreg %userdata6, i32 inreg %userdata7, i32 inreg %userdata8, i32 inreg %userdata9, i32 inreg %userdata10, i32 inreg %userdata11, i32 inreg %spillTable, <3 x i32> inreg %WorkgroupId, i32 inreg %MultiDispatchInfo, <3 x i32> %LocalInvocationId) #0 !lgc.shaderstage !7 {
+; CHECK: define amdgpu_gfx void @func(i32 inreg noundef %globalTable, ptr addrspace(4) inreg noundef %numWorkgroupsPtr, i32 inreg noundef %userdata0, i32 inreg noundef %userdata1, i32 inreg noundef %userdata2, i32 inreg noundef %userdata3, i32 inreg noundef %userdata4, i32 inreg noundef %userdata5, i32 inreg noundef %userdata6, i32 inreg noundef %userdata7, i32 inreg noundef %userdata8, i32 inreg noundef %userdata9, i32 inreg noundef %userdata10, i32 inreg noundef %userdata11, i32 inreg noundef %spillTable, <3 x i32> inreg noundef %WorkgroupId, i32 inreg noundef %MultiDispatchInfo, <3 x i32> noundef %LocalInvocationId) #0 !lgc.shaderstage !7 {
 
 ; CHECK: IR Dump After Patch LLVM to set up target features
 ; CHECK: attributes #0 = { nounwind {{.*}}"amdgpu-flat-work-group-size"="6,6"
diff --git a/lgc/test/TaskShaderEntryArgs.lgc b/lgc/test/TaskShaderEntryArgs.lgc
index 3b7be2f345..47eeb896ed 100644
--- a/lgc/test/TaskShaderEntryArgs.lgc
+++ b/lgc/test/TaskShaderEntryArgs.lgc
@@ -6,7 +6,7 @@
 ; arguments should be present in order: meshTaskDispatchDims, meshTaskRingIndex, meshPipeStatsBuf.
 ;
 ; CHECK-LABEL: _amdgpu_cs_main
-; CHECK: <3 x i32> inreg %meshTaskDispatchDims, i32 inreg %meshTaskRingIndex, i32 inreg %meshPipeStatsBuf
+; CHECK: <3 x i32> inreg noundef %meshTaskDispatchDims, i32 inreg noundef %meshTaskRingIndex, i32 inreg noundef %meshPipeStatsBuf
 
 ; ModuleID = 'lgcPipeline'
 source_filename = "llpctask1"
diff --git a/lgc/test/Transforms/CpsLowering/cps-entry-point.lgc b/lgc/test/Transforms/CpsLowering/cps-entry-point.lgc
index bec0822026..9b1b1207c9 100644
--- a/lgc/test/Transforms/CpsLowering/cps-entry-point.lgc
+++ b/lgc/test/Transforms/CpsLowering/cps-entry-point.lgc
@@ -47,7 +47,7 @@ attributes #5 = { nounwind willreturn memory(none) }
 !2 = !{i32 8, i32 4, i32 1}
 !3 = !{i32 7}
 ; CHECK-LABEL: define {{[^@]+}}@lgc.shader.CS.main
-; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[USERDATA0:%.*]], i32 inreg [[USERDATA1:%.*]], i32 inreg [[USERDATA2:%.*]], i32 inreg [[USERDATA3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], <3 x i32> inreg [[WORKGROUPID:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]]) #[[ATTR3:[0-9]+]] !lgc.shaderstage !4 {
+; CHECK-SAME: (i32 inreg noundef [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg noundef [[NUMWORKGROUPSPTR:%.*]], i32 inreg noundef [[USERDATA0:%.*]], i32 inreg noundef [[USERDATA1:%.*]], i32 inreg noundef [[USERDATA2:%.*]], i32 inreg noundef [[USERDATA3:%.*]], i32 inreg noundef [[PAD4:%.*]], i32 inreg noundef [[PAD5:%.*]], i32 inreg noundef [[PAD6:%.*]], i32 inreg noundef [[PAD7:%.*]], i32 inreg noundef [[PAD8:%.*]], i32 inreg noundef [[PAD9:%.*]], i32 inreg noundef [[PAD10:%.*]], i32 inreg noundef [[PAD11:%.*]], i32 inreg noundef [[SPILLTABLE:%.*]], <3 x i32> inreg noundef [[WORKGROUPID:%.*]], i32 inreg noundef [[MULTIDISPATCHINFO:%.*]], <3 x i32> noundef [[LOCALINVOCATIONID:%.*]]) #[[ATTR3:[0-9]+]] !lgc.shaderstage !4 {
 ; CHECK-NEXT:  .entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.amdgcn.s.getpc()
diff --git a/lgc/test/UnlinkedTessFetches.lgc b/lgc/test/UnlinkedTessFetches.lgc
index 32a0e0fff4..850386de4f 100644
--- a/lgc/test/UnlinkedTessFetches.lgc
+++ b/lgc/test/UnlinkedTessFetches.lgc
@@ -4,9 +4,9 @@
 
 ; Find the second run of Patch LLVM for preparing pipeline ABI
 ; CHECK: IR Dump After Patch LLVM for preparing pipeline ABI
-; CHECK: define dllexport amdgpu_hs void @_amdgpu_hs_main_fetchless({{.*}}, <4 x float> [[vertInput:%[0-9]*]])
+; CHECK: define dllexport amdgpu_hs void @_amdgpu_hs_main_fetchless({{.*}}, <4 x float> noundef [[vertInput:%[0-9]*]])
 ; CHECK: call amdgpu_ls void @_amdgpu_ls_main_fetchless({{.*}}, <4 x float> [[vertInput]])
-; CHECK: define internal{{.*}} amdgpu_ls void @_amdgpu_ls_main_fetchless({{.*}}, <4 x float> %vertex{{[0-9]*.[0-9]*}})
+; CHECK: define internal{{.*}} amdgpu_ls void @_amdgpu_ls_main_fetchless({{.*}}, <4 x float> noundef %vertex{{[0-9]*.[0-9]*}})
 
 ; ModuleID = 'lgcPipeline'
 source_filename = "lgcPipeline"
diff --git a/lgc/test/UnlinkedVsGsInputs.lgc b/lgc/test/UnlinkedVsGsInputs.lgc
index 5ae33191d9..d3e79e787f 100644
--- a/lgc/test/UnlinkedVsGsInputs.lgc
+++ b/lgc/test/UnlinkedVsGsInputs.lgc
@@ -2,9 +2,9 @@
 ; to the vertex shader, which expects it as the last parameter.
 ; RUN: lgc -mcpu=gfx900 %s -o /dev/null -print-after=lgc-patch-prepare-pipeline-abi 2>&1 | FileCheck --check-prefixes=CHECK %s
 ; CHECK: IR Dump After Patch LLVM for preparing pipeline ABI on [module]
-; CHECK: define dllexport amdgpu_gs void @_amdgpu_gs_main_fetchless({{.*}}, <2 x float> [[vertInput:%[0-9]*]])
+; CHECK: define dllexport amdgpu_gs void @_amdgpu_gs_main_fetchless({{.*}}, <2 x float> noundef [[vertInput:%[0-9]*]])
 ; CHECK: call amdgpu_es void @_amdgpu_es_main_fetchless({{.*}}, <2 x float> [[vertInput]])
-; CHECK: define internal{{.*}} amdgpu_es void @_amdgpu_es_main_fetchless({{.*}}, <2 x float> %vertex0.0)
+; CHECK: define internal{{.*}} amdgpu_es void @_amdgpu_es_main_fetchless({{.*}}, <2 x float> noundef %vertex0.0)
 
 ; ModuleID = 'lgcPipeline'
 source_filename = "lgcPipeline"
diff --git a/llpc/test/shaderdb/general/PipelineCs_TestMultiEntryPoint_lit.pipe b/llpc/test/shaderdb/general/PipelineCs_TestMultiEntryPoint_lit.pipe
index b2d8041943..df89f353fb 100644
--- a/llpc/test/shaderdb/general/PipelineCs_TestMultiEntryPoint_lit.pipe
+++ b/llpc/test/shaderdb/general/PipelineCs_TestMultiEntryPoint_lit.pipe
@@ -6,7 +6,7 @@
 ; SHADERTEST: !llpc.compute.mode = !{![[COMPUTEMODE:[0-9]+]]}
 ; SHADERTEST: ![[COMPUTEMODE]] = !{i32 1, i32 1, i32 1}
 ; SHADERTEST-LABEL: {{^// LLPC}} pipeline patching results
-; SHADERTEST: define {{.*}} void @_amdgpu_cs_main(i32 inreg %globalTable, i32 inreg %userdata0, <3 x i32> inreg %WorkgroupId, i32 inreg %MultiDispatchInfo, <3 x i32> %LocalInvocationId)
+; SHADERTEST: define {{.*}} void @_amdgpu_cs_main(i32 inreg noundef %globalTable, i32 inreg noundef %userdata0, <3 x i32> inreg noundef %WorkgroupId, i32 inreg noundef %MultiDispatchInfo, <3 x i32> noundef %LocalInvocationId)
 ; SHADERTEST: AMDLLPC SUCCESS
 ; END_SHADERTEST
 
diff --git a/llpc/test/shaderdb/general/PipelineVsFs_TestBarycentric_line_list.pipe b/llpc/test/shaderdb/general/PipelineVsFs_TestBarycentric_line_list.pipe
index 7b0cbde9e4..cc1b9c4d81 100644
--- a/llpc/test/shaderdb/general/PipelineVsFs_TestBarycentric_line_list.pipe
+++ b/llpc/test/shaderdb/general/PipelineVsFs_TestBarycentric_line_list.pipe
@@ -3,7 +3,7 @@
 ; BEGIN_SHADERTEST
 ; RUN: amdllpc -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
 // barycentric coordinate: (1 - i - j, i + j, 0)
-; SHADERTEST-LABEL: define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 inreg %globalTable,
+; SHADERTEST-LABEL: define dllexport amdgpu_ps void @_amdgpu_ps_main(
 ; SHADERTEST: %[[jCoord:[^,]*]] = extractelement <2 x float> %PerspInterpCenter, i64 1
 ; SHADERTEST: %[[iCoord:[^,]*]] = extractelement <2 x float> %PerspInterpCenter, i64 0
 ; SHADERTEST: %[[subICoord:[0-9]*]] = fsub float 1.000000e+00, %[[iCoord]]
diff --git a/llpc/test/shaderdb/general/PipelineVsFs_TestBarycentric_tri_list.pipe b/llpc/test/shaderdb/general/PipelineVsFs_TestBarycentric_tri_list.pipe
index 1cf7fe5dd7..f189e520fe 100644
--- a/llpc/test/shaderdb/general/PipelineVsFs_TestBarycentric_tri_list.pipe
+++ b/llpc/test/shaderdb/general/PipelineVsFs_TestBarycentric_tri_list.pipe
@@ -3,7 +3,7 @@
 ; BEGIN_SHADERTEST
 ; RUN: amdllpc -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
 // barycentric coordinate: (i ,j , 1 - i - j)
-; SHADERTEST-LABEL: define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 inreg %globalTable,
+; SHADERTEST-LABEL: define dllexport amdgpu_ps void @_amdgpu_ps_main(
 ; SHADERTEST: %[[jCoord:[^,]*]] = extractelement <2 x float> %PerspInterpCenter, i64 1
 ; SHADERTEST: %[[iCoord:[^,]*]] = extractelement <2 x float> %PerspInterpCenter, i64 0
 ; SHADERTEST: %[[subICoord:[0-9]*]] = fsub float 1.000000e+00, %[[iCoord]]
diff --git a/llpc/test/shaderdb/general/PipelineVsFs_TestIndirectResourceLayout.pipe b/llpc/test/shaderdb/general/PipelineVsFs_TestIndirectResourceLayout.pipe
index 519d70313e..fe25aa2885 100644
--- a/llpc/test/shaderdb/general/PipelineVsFs_TestIndirectResourceLayout.pipe
+++ b/llpc/test/shaderdb/general/PipelineVsFs_TestIndirectResourceLayout.pipe
@@ -16,7 +16,7 @@
 ; SHADERTEST: call void @lgc.output.export.generic.i32.i32.v4f32(i32 0, i32 0, <4 x float> [[Value]])
 
 ; SHADERTEST-LABEL: {{^// LLPC}} pipeline patching results
-; SHADERTEST: define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 inreg %{{[^,]*}}, i32 inreg %userdata1,
+; SHADERTEST: define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 inreg noundef %{{[^,]*}}, i32 inreg noundef %userdata1,
 ; SHADERTEST: [[Addr0:%[0-9]*]] = zext i32 %userdata1 to i64
 ; SHADERTEST: [[Addr1:%[0-9]*]] = or i64 %{{[0-9]*}}, [[Addr0]]
 ; SHADERTEST: [[Addr2:%[0-9]*]] = inttoptr i64 [[Addr1]] to ptr addrspace(4)
diff --git a/llpc/test/shaderdb/general/PipelineVsFs_TestPrimitiveID_First.pipe b/llpc/test/shaderdb/general/PipelineVsFs_TestPrimitiveID_First.pipe
index 53d37ebb90..0ec61475ed 100644
--- a/llpc/test/shaderdb/general/PipelineVsFs_TestPrimitiveID_First.pipe
+++ b/llpc/test/shaderdb/general/PipelineVsFs_TestPrimitiveID_First.pipe
@@ -4,7 +4,7 @@
 ; RUN: amdllpc -v --gfxip=10.1.0 %s | FileCheck -check-prefix=SHADERTEST %s
 ; SHADERTEST-LABEL: {{^// LLPC}} pipeline patching results
 ; SHADERTEST: @[[LDS:[^ ]*]] = external addrspace(3) global [{{[0-9]*}} x i32], align 4
-; SHADERTEST: define dllexport amdgpu_gs void @_amdgpu_gs_main({{.*}}, i32 %esGsOffsets01, i32 %esGsOffsets23, i32 %primitiveId,
+; SHADERTEST: define dllexport amdgpu_gs void @_amdgpu_gs_main({{.*}}, i32 noundef %esGsOffsets01, i32 noundef %esGsOffsets23, i32 noundef %primitiveId,
 ; Extract bits 0 to 8 from %esGsOffsets01. These bit encode the thread ID in sub-group which will be used to
 ; calculate the address at which to store the provoking vertex.
 ; SHADERTEST: [[offset:%[0-9]*]] = and i32 %esGsOffsets01, 511
diff --git a/llpc/test/shaderdb/general/PipelineVsFs_TestPrimitiveID_Last.pipe b/llpc/test/shaderdb/general/PipelineVsFs_TestPrimitiveID_Last.pipe
index e8a7ad7d90..5efb58af40 100644
--- a/llpc/test/shaderdb/general/PipelineVsFs_TestPrimitiveID_Last.pipe
+++ b/llpc/test/shaderdb/general/PipelineVsFs_TestPrimitiveID_Last.pipe
@@ -4,7 +4,7 @@
 ; RUN: amdllpc -v --gfxip=10.1.0 %s | FileCheck -check-prefix=SHADERTEST %s
 ; SHADERTEST-LABEL: {{^// LLPC}} pipeline patching results
 ; SHADERTEST: @[[LDS:[^ ]*]] = external addrspace(3) global [{{[0-9]*}} x i32], align 4
-; SHADERTEST: define dllexport amdgpu_gs void @_amdgpu_gs_main({{.*}}, i32 %esGsOffsets01, i32 %esGsOffsets23, i32 %primitiveId,
+; SHADERTEST: define dllexport amdgpu_gs void @_amdgpu_gs_main({{.*}}, i32 noundef %esGsOffsets01, i32 noundef %esGsOffsets23, i32 noundef %primitiveId,
 ; Extract bits 20 to 28 from %esGsOffsets01. These bit encode the thread ID in sub-group which will be used to
 ; calculate the address at which to store the provoking vertex.
 ; SHADERTEST: [[offset1:%[0-9]*]] = lshr i32 %esGsOffsets01, 20
diff --git a/llpc/test/shaderdb/general/TestWorkgroupIdOpt.comp b/llpc/test/shaderdb/general/TestWorkgroupIdOpt.comp
index e5f6107908..f200fa8c58 100644
--- a/llpc/test/shaderdb/general/TestWorkgroupIdOpt.comp
+++ b/llpc/test/shaderdb/general/TestWorkgroupIdOpt.comp
@@ -16,7 +16,7 @@ void main()
     test = gl_WorkGroupID.x;
 }
 // CHECK-LABEL: define {{[^@]+}}@_amdgpu_cs_main
-// CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], i32 inreg [[USERDATA0:%.*]], i32 inreg [[WORKGROUPID1:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]]) #[[ATTR0:[0-9]+]] !lgc.shaderstage !5 {
+// CHECK-SAME: (i32 inreg noundef [[GLOBALTABLE:%.*]], i32 inreg noundef [[USERDATA0:%.*]], i32 inreg noundef [[WORKGROUPID1:%.*]], i32 inreg noundef [[MULTIDISPATCHINFO:%.*]], <3 x i32> noundef [[LOCALINVOCATIONID:%.*]]) #[[ATTR0:[0-9]+]] !lgc.shaderstage !5 {
 // CHECK-NEXT:  .entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.amdgcn.s.getpc()
 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], -4294967296
diff --git a/llpc/test/shaderdb/gfx9/PipelineVsFs_TestFetchSingleInput.pipe b/llpc/test/shaderdb/gfx9/PipelineVsFs_TestFetchSingleInput.pipe
index 642213640a..d33887af1c 100644
--- a/llpc/test/shaderdb/gfx9/PipelineVsFs_TestFetchSingleInput.pipe
+++ b/llpc/test/shaderdb/gfx9/PipelineVsFs_TestFetchSingleInput.pipe
@@ -5,13 +5,13 @@
 ; Skip to the patching results for the fetch shader
 ; SHADERTEST-LABEL: LLPC pipeline patching results
 ; Check the inputs to the vertex shader.  This should be all of the regular inputs.  There is one vertex attribute being passed in: The vector at the end.
-; SHADERTEST: define dllexport amdgpu_vs void @_amdgpu_vs_main_fetchless(i32 inreg %globalTable, i32 inreg %userdata0, i32 inreg %vertexBufferTable, i32 inreg %baseVertex, i32 inreg %baseInstance, i32 %VertexId, i32 %RelVertexId, i32 %PrimitiveId, i32 %InstanceId, <4 x float> %vertex0.0)
+; SHADERTEST: define dllexport amdgpu_vs void @_amdgpu_vs_main_fetchless(i32 inreg noundef %globalTable, i32 inreg noundef %userdata0, i32 inreg noundef %vertexBufferTable, i32 inreg noundef %baseVertex, i32 inreg noundef %baseInstance, i32 noundef %VertexId, i32 noundef %RelVertexId, i32 noundef %PrimitiveId, i32 noundef %InstanceId, <4 x float> noundef %vertex0.0)
 ; SHADERTEST-LABEL: LGC glue shader results
 ; Check the inputs to the fetch shader.  This should match the vertex shader except:
 ; - there are extra inreg inputs because its determination of how many SGPR inputs
 ;   are conservative;
 ; - there is no VGPR input for the vertex input that the fetch shader generates.
-; SHADERTEST: define amdgpu_vs { i32,{{.*}}, i32, float, float, float, float, <4 x float> } @_amdgpu_vs_main(i32 inreg %0, i32 inreg %1, i32 inreg %VertexBufferTable, i32 inreg %BaseVertex, i32 inreg %BaseInstance, {{.*}}, i32 inreg %{{.*}}, float %VertexId, float %{{.*}}, float %{{.*}}, float %InstanceId)
+; SHADERTEST: define amdgpu_vs { i32,{{.*}}, i32, float, float, float, float, <4 x float> } @_amdgpu_vs_main(i32 inreg noundef %0, i32 inreg noundef %1, i32 inreg noundef %VertexBufferTable, i32 inreg noundef %BaseVertex, i32 inreg noundef %BaseInstance, {{.*}}, i32 inreg noundef %{{.*}}, float noundef %VertexId, float noundef %{{.*}}, float noundef %{{.*}}, float noundef %InstanceId)
 ; Check that the attribute is loaded.
 ; SHADERTEST:  [[f0:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[addr:%[0-9]*]], i32 %VertexIndex, i32 0, i32 0, i32 immarg 116, i32 immarg 0)
 ; SHADERTEST:  [[f1:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[addr:%[0-9]*]], i32 %VertexIndex, i32 4, i32 0, i32 immarg 116, i32 immarg 0)
diff --git a/llpc/test/shaderdb/relocatable_shaders/PipelineGsTess_AllStagesReloc.pipe b/llpc/test/shaderdb/relocatable_shaders/PipelineGsTess_AllStagesReloc.pipe
index 464f3d0768..d84cb9fa8e 100644
--- a/llpc/test/shaderdb/relocatable_shaders/PipelineGsTess_AllStagesReloc.pipe
+++ b/llpc/test/shaderdb/relocatable_shaders/PipelineGsTess_AllStagesReloc.pipe
@@ -7,7 +7,7 @@
 ; SHADERTEST: {{^//}} LLPC pipeline patching results
 
 ; Make sure the hs shader comes first and has the vertex attribute as its last parameter.
-; SHADERTEST: define dllexport amdgpu_hs void @_amdgpu_hs_main_fetchless({{.*}}, <4 x float> [[vert_attrib:%[0-9]*]])
+; SHADERTEST: define dllexport amdgpu_hs void @_amdgpu_hs_main_fetchless({{.*}}, <4 x float> noundef [[vert_attrib:%[0-9]*]])
 
 ; Call the original vertex shader passing in the attribute
 ; SHADERTEST: call amdgpu_ls void @_amdgpu_ls_main_fetchless({{.*}}, <4 x float> [[vert_attrib]])
@@ -17,14 +17,14 @@
 
 ; Make sure that the GS shader does not have the vertex attribute.  It is not needed if it does not call the original
 ; vertex shader.
-; SHADERTEST: define dllexport amdgpu_gs void @_amdgpu_gs_main({{.*}}, i32 {{%[0-9]*}})
+; SHADERTEST: define dllexport amdgpu_gs void @_amdgpu_gs_main({{.*}}, i32 noundef {{%[0-9]*}})
 
 ; SHADERTEST: {{^//}} LLPC final pipeline module info
 
 ; Test that the vertex input is correctly loaded.  For GFX9, if the HS has no vertecies, then the first two vgpr inputs are dropped.  This must be accounted for.
 ; SHADERTEST: {{^//}} LGC glue shader results
 ; Fist identify the vgpr input in the function parameters.  We want to make sure we get the vertex id and the vgpr 2 place before it.
-; SHADERTEST: define amdgpu_hs { {{.*}} } @_amdgpu_hs_main({{(i32 inreg %[a-zA-Z0-9]+, )+}}float [[vgpr0:%[a-zA-Z0-9]+]], float [[vgpr1:%[a-zA-Z0-9]+]], float %VertexId, float [[vgpr3:%[a-zA-Z0-9]+]], float [[vgpr4:%[a-zA-Z0-9]+]], float %InstanceId)
+; SHADERTEST: define amdgpu_hs { {{.*}} } @_amdgpu_hs_main({{(i32 inreg noundef %[a-zA-Z0-9]+, )+}}float noundef [[vgpr0:%[a-zA-Z0-9]+]], float noundef [[vgpr1:%[a-zA-Z0-9]+]], float noundef %VertexId, float noundef [[vgpr3:%[a-zA-Z0-9]+]], float noundef [[vgpr4:%[a-zA-Z0-9]+]], float noundef %InstanceId)
 ;
 ; Make sure that the code picks the vgpr that actually contains the vertex id by checking if the HS has any vertices.
 ; SHADERTEST: [[hsVertexCount:%[0-9]+]] = and i32 %MergedWaveInfo, 65280
@@ -45,7 +45,7 @@
 
 ; Test that the vertex input is correctly loaded.  GFX10 does not have to issue mentioned above.  Make sure that %VertexId is used.
 ; SHADERTEST_GFX10: {{^//}} LGC glue shader results
-; SHADERTEST_GFX10: define amdgpu_hs { {{.*}} } @_amdgpu_hs_main({{.*}}, float %VertexId
+; SHADERTEST_GFX10: define amdgpu_hs { {{.*}} } @_amdgpu_hs_main({{.*}}, float noundef %VertexId
 ; SHADERTEST_GFX10: [[vgprAsInt:%[0-9]+]] = bitcast float %VertexId to i32
 ; SHADERTEST_GFX10: %VertexIndex = add i32 [[vgprAsInt]], %BaseVertex
 ; SHADERTEST_GFX10: @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> {{%[0-9]+}}, i32 %VertexIndex,
diff --git a/llpc/test/shaderdb/relocatable_shaders/PipelineGs_VertAttributeShort.pipe b/llpc/test/shaderdb/relocatable_shaders/PipelineGs_VertAttributeShort.pipe
index 7af5cf0b91..dc222ee861 100644
--- a/llpc/test/shaderdb/relocatable_shaders/PipelineGs_VertAttributeShort.pipe
+++ b/llpc/test/shaderdb/relocatable_shaders/PipelineGs_VertAttributeShort.pipe
@@ -5,7 +5,7 @@
 ; SHADERTEST: {{^//}} LLPC pipeline patching results
 
 ; The i16vec4 fetch comes in as a <2 x float>, and passed on to the vertex shader.
-; SHADERTEST: define dllexport amdgpu_gs void @_amdgpu_gs_main_fetchless({{.*}}, <2 x float> [[fetch:%[0-9]*]])
+; SHADERTEST: define dllexport amdgpu_gs void @_amdgpu_gs_main_fetchless({{.*}}, <2 x float> noundef [[fetch:%[0-9]*]])
 ; SHADERTEST: call amdgpu_es void @_amdgpu_es_main_fetchless({{.*}}, <2 x float> [[fetch]])
 ; SHADERTEST: =====  AMDLLPC SUCCESS  =====
 ; END_SHADERTEST
diff --git a/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_16BitInput.pipe b/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_16BitInput.pipe
index f80096404c..167f27a687 100644
--- a/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_16BitInput.pipe
+++ b/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_16BitInput.pipe
@@ -7,7 +7,7 @@
 
 ; Make sure the vertex shader truncates the first 16-bits before using the input.
 ; SHADERTEST: // LLPC pipeline patching results
-; SHADERTEST: define dllexport amdgpu_vs void @_amdgpu_vs_main_fetchless({{.*}}, float [[input:%[0-9]*]]) #0 !lgc.shaderstage !1 {
+; SHADERTEST: define dllexport amdgpu_vs void @_amdgpu_vs_main_fetchless({{.*}}, float noundef [[input:%[0-9]*]]) #0 !lgc.shaderstage !1 {
 ; SHADERTEST:  [[cast:%[0-9]+]] = bitcast float [[input]] to <2 x half>
 ; SHADERTEST:  [[value:%[.a-zA-Z0-9]+]] = extractelement <2 x half> [[cast]], i64 0
 
diff --git a/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_MultiDwordPushConst.pipe b/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_MultiDwordPushConst.pipe
index bbdb465124..f6b43d8a0f 100644
--- a/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_MultiDwordPushConst.pipe
+++ b/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_MultiDwordPushConst.pipe
@@ -6,7 +6,7 @@
 
 ; Check that the llvm-ir gets the push constant values from as a parameter.
 ; SHADERTEST: // LLPC pipeline patching results
-; SHADERTEST: define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_main({{.*}}, i32 inreg %userdata3, i32 inreg %userdata4, {{.*}})
+; SHADERTEST: define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_main({{.*}}, i32 inreg noundef %userdata3, i32 inreg noundef %userdata4, {{.*}})
 ; SHADERTEST: [[pushConst0:%[.a-zA-Z0-9]+]] = bitcast i32 %userdata3 to float
 ; SHADERTEST: [[pushConst1:%[.a-zA-Z0-9]+]] = bitcast i32 %userdata4 to float
 ; SHADERTEST: @llvm.amdgcn.image.gather4.lz.2d.sl_v4f32i32s.f32({{.*}}, float [[pushConst0]], float [[pushConst1]], {{.*}})
diff --git a/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_VertexFetchDouble.pipe b/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_VertexFetchDouble.pipe
index 66c28af4a7..3450258aac 100644
--- a/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_VertexFetchDouble.pipe
+++ b/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_VertexFetchDouble.pipe
@@ -4,7 +4,7 @@
 ; RUN: amdllpc -enable-relocatable-shader-elf -o %t.elf %gfxip %s -v | FileCheck -check-prefix=SHADERTEST %s
 ; SHADERTEST: {{^}}// LLPC pipeline patching results
 ; Check that the last input parameter is a float2.
-; SHADERTEST: define dllexport amdgpu_vs void @_amdgpu_vs_main_fetchless({{.*}}, <2 x float> %0)
+; SHADERTEST: define dllexport amdgpu_vs void @_amdgpu_vs_main_fetchless({{.*}}, <2 x float> noundef %0)
 ; SHADERTEST: {{^//}} LGC glue shader results
 ; SHADERTEST: {{^;}} ModuleID = 'fetchShader'
 ; Check that the last element in the return type is a float2.