From cd21416e925ff34ca0df9d112cc4419a2370d9f9 Mon Sep 17 00:00:00 2001 From: Shenwei Wang Date: Wed, 2 Aug 2023 14:54:11 -0500 Subject: [PATCH] LF-9716 arm64: dts: imx93-14x14-evk: correct the GPIO pins for usdhc3 According to SPF-55129 A2, the reset pin is #12 from pcal6524, and the WiFi regulator(M2_nDIS1) is #20 from pcal6524. Both indexes start from 0 here. Signed-off-by: Shenwei Wang Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts index 25181858031913..7c4822f25f43a0 100644 --- a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts @@ -163,7 +163,16 @@ usdhc3_pwrseq: usdhc3_pwrseq { compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; + + reg_usdhc3_vmmc: usdhc3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "M2_WiFi_ON"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + enable-active-high; }; reg_dvdd_sel: regulator-dvdd_sel { @@ -617,7 +626,7 @@ pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; mmc-pwrseq = <&usdhc3_pwrseq>; - pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc3_vmmc>; bus-width = <4>; keep-power-in-suspend; non-removable;