From 28fa88ff39e08f27c0991ce42cf8d68c26ba2f6a Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 29 Apr 2024 08:46:36 -0400 Subject: [PATCH 1/4] OpcodeDispatcher: fix 8/16-bit adc/sbc flags Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp index faea27af32..33e0a4e046 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp @@ -344,6 +344,9 @@ OrderedNode* OpDispatchBuilder::CalculateFlags_ADC(uint8_t SrcSize, OrderedNode* Res = _Adc(OpSize, Src1, Src2); Res = _Bfe(OpSize, SrcSize * 8, 0, Res); + // Need to zero-extend for correct comparisons below + Src2 = _Bfe(OpSize, SrcSize * 8, 0, Src2); + auto SelectOpLT = _Select(FEXCore::IR::COND_ULT, Res, Src2, One, Zero); auto SelectOpLE = _Select(FEXCore::IR::COND_ULE, Res, Src2, One, Zero); auto SelectCF = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT); @@ -379,6 +382,9 @@ OrderedNode* OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode* Res = _Sub(OpSize, Src1, _Add(OpSize, Src2, CF)); Res = _Bfe(OpSize, SrcSize * 8, 0, Res); + // Need to zero-extend for correct comparisons below + Src1 = _Bfe(OpSize, SrcSize * 8, 0, Src1); + auto SelectOpLT = _Select(FEXCore::IR::COND_UGT, Res, Src1, One, Zero); auto SelectOpLE = _Select(FEXCore::IR::COND_UGE, Res, Src1, One, Zero); auto SelectCF = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT); From 76b5ca4bcc21a5166813244c48243bc4fbad4ef1 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 29 Apr 2024 09:06:35 -0400 Subject: [PATCH 2/4] OpcodeDispatcher: optimize 8/16-bit adc Signed-off-by: Alyssa Rosenzweig --- .../Interface/Core/OpcodeDispatcher/Flags.cpp | 30 +++++++++++-------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp index 33e0a4e046..915e5aa732 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp @@ -340,16 +340,19 @@ OrderedNode* OpDispatchBuilder::CalculateFlags_ADC(uint8_t SrcSize, OrderedNode* HandleNZCV_RMW(); Res = _AdcWithFlags(OpSize, Src1, Src2); } else { - auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC); - Res = _Adc(OpSize, Src1, Src2); - Res = _Bfe(OpSize, SrcSize * 8, 0, Res); - // Need to zero-extend for correct comparisons below Src2 = _Bfe(OpSize, SrcSize * 8, 0, Src2); - auto SelectOpLT = _Select(FEXCore::IR::COND_ULT, Res, Src2, One, Zero); - auto SelectOpLE = _Select(FEXCore::IR::COND_ULE, Res, Src2, One, Zero); - auto SelectCF = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT); + // Note that we do not extend Src2PlusCF, since we depend on proper + // 32-bit arithmetic to correctly handle the Src2 = 0xffff case. + OrderedNode* Src2PlusCF = _Adc(OpSize, _Constant(0), Src2); + + // Need to zero-extend for the comparison. + Res = _Add(OpSize, Src1, Src2PlusCF); + Res = _Bfe(OpSize, SrcSize * 8, 0, Res); + + // TODO: We can fold that second Bfe in (cmp uxth). + auto SelectCF = _Select(FEXCore::IR::COND_ULT, Res, Src2PlusCF, One, Zero); SetNZ_ZeroCV(SrcSize, Res); SetRFLAG(SelectCF); @@ -378,16 +381,17 @@ OrderedNode* OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode* // Rectify output carry CarryInvert(); } else { + // Zero extend for correct comparison behaviour with Src1 = 0xffff. + Src1 = _Bfe(OpSize, SrcSize * 8, 0, Src1); + auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC); - Res = _Sub(OpSize, Src1, _Add(OpSize, Src2, CF)); + auto Src1MinusCF = _Sub(OpSize, Src1, CF); + + Res = _Sub(OpSize, Src1MinusCF, Src2); Res = _Bfe(OpSize, SrcSize * 8, 0, Res); // Need to zero-extend for correct comparisons below - Src1 = _Bfe(OpSize, SrcSize * 8, 0, Src1); - - auto SelectOpLT = _Select(FEXCore::IR::COND_UGT, Res, Src1, One, Zero); - auto SelectOpLE = _Select(FEXCore::IR::COND_UGE, Res, Src1, One, Zero); - auto SelectCF = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT); + auto SelectCF = _Select(FEXCore::IR::COND_ULT, Src1MinusCF, Res, One, Zero); SetNZ_ZeroCV(SrcSize, Res); SetRFLAG(SelectCF); From 640e911af4a0ca6a3e02d56ec0668e7b5275be4c Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sun, 28 Apr 2024 21:16:37 -0700 Subject: [PATCH 3/4] Adds unit tests for ADC/SBB garbage upper data bug Reproduces broken rendering in Final Fantasy 7 (SteamID 39140) --- unittests/ASM/FEX_bugs/add_sub_carry.asm | 29 ++++ unittests/ASM/FEX_bugs/add_sub_carry_2.asm | 167 +++++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 unittests/ASM/FEX_bugs/add_sub_carry.asm create mode 100644 unittests/ASM/FEX_bugs/add_sub_carry_2.asm diff --git a/unittests/ASM/FEX_bugs/add_sub_carry.asm b/unittests/ASM/FEX_bugs/add_sub_carry.asm new file mode 100644 index 0000000000..54205249b7 --- /dev/null +++ b/unittests/ASM/FEX_bugs/add_sub_carry.asm @@ -0,0 +1,29 @@ +%ifdef CONFIG +{ + "RegData": { + "RAX": "0xaeadacac9a9a41e5", + "RBX": "0x6162636520238df8" + } +} +%endif + +; FEX had a bug with smaller than 32-bit operations corrupting sbb and adc results. +; A small test that tests both sbb and adc to ensure it returns data correctly. +; This was noticed in Final Fantasy 7 (steamid 39140) having broken rendering on the title screen. +mov rax, 0x4142434445464748 +mov rbx, 0x5152535455565758 +mov rcx, 0x6162636465666768 + +clc +sbb al, bl +sbb ax, bx +sbb eax, ebx +sbb rax, rbx + +clc +adc bl, cl +adc bx, cx +adc ebx, ecx +adc rbx, rcx + +hlt diff --git a/unittests/ASM/FEX_bugs/add_sub_carry_2.asm b/unittests/ASM/FEX_bugs/add_sub_carry_2.asm new file mode 100644 index 0000000000..902ac7a820 --- /dev/null +++ b/unittests/ASM/FEX_bugs/add_sub_carry_2.asm @@ -0,0 +1,167 @@ +%ifdef CONFIG +{ + "RegData": { + "RAX": "0xedededee26260e6c", + "RBX": "0x121212129498c16d" + } +} +%endif + +; FEX had a bug with smaller than 32-bit operations corrupting sbb and adc results. +; A small test that tests both sbb and adc to ensure it returns data correctly. +; This was noticed in Final Fantasy 7 (steamid 39140) having broken rendering on the title screen. +mov rax, 0x4142434445464748 +mov rbx, 0x5152535455565758 +mov rcx, 0x6162636465666768 + +clc +sbb al, bl +sbb ax, bx +sbb eax, ebx +sbb rax, rbx + +%assign i 0 +%rep 256 +sbb al, [rel .data1 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +sbb ax, [rel .data2 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +sbb eax, [rel .data4 + i] +%assign i i+1 +%endrep + + +%assign i 0 +%rep 256 +sbb rax, [rel .data8 + i] +%assign i i+1 +%endrep + +stc +%assign i 0 +%rep 256 +sbb al, [rel .data1 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +sbb ax, [rel .data2 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +sbb eax, [rel .data4 + i] +%assign i i+1 +%endrep + + +%assign i 0 +%rep 256 +sbb rax, [rel .data8 + i] +%assign i i+1 +%endrep + + + + +clc +adc bl, cl +adc bx, cx +adc ebx, ecx +adc rbx, rcx + + +%assign i 0 +%rep 256 +adc bl, [rel .data1 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +adc bx, [rel .data2 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +adc ebx, [rel .data4 + i] +%assign i i+1 +%endrep + + +%assign i 0 +%rep 256 +adc rbx, [rel .data8 + i] +%assign i i+1 +%endrep + + +stc +%assign i 0 +%rep 256 +adc bl, [rel .data1 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +adc bx, [rel .data2 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +adc ebx, [rel .data4 + i] +%assign i i+1 +%endrep + + +%assign i 0 +%rep 256 +adc rbx, [rel .data8 + i] +%assign i i+1 +%endrep + + + + +hlt + +.data1: +%assign i 0 +%rep 256 +db i +%assign i i+1 +%endrep + +.data2: +%assign i 0 +%rep 256 +dw i +%assign i i+1 +%endrep + +.data4: +%assign i 0 +%rep 256 +dd i +%assign i i+1 +%endrep + +.data8: +%assign i 0 +%rep 256 +dq i +%assign i i+1 +%endrep From bfb06b2d55c1a1d9826da5fc03df5c0341b5a061 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 29 Apr 2024 19:53:14 -0400 Subject: [PATCH 4/4] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- unittests/InstructionCountCI/Atomics.json | 358 +++++++-------- .../InstructionCountCI/FlagM/Atomics.json | 316 ++++++------- .../InstructionCountCI/FlagM/Primary.json | 349 +++++++------- .../FlagM/PrimaryGroup.json | 84 ++-- unittests/InstructionCountCI/Primary.json | 427 ++++++++---------- .../InstructionCountCI/PrimaryGroup.json | 96 ++-- 6 files changed, 724 insertions(+), 906 deletions(-) diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index 9936778c38..0cc6c1aa46 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -69,56 +69,50 @@ ] }, "lock adc byte [rax], cl": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Comment": "0x10", "ExpectedArm64ASM": [ "adc w20, wzr, w5", "ldaddalb w20, w20, [x4]", "eor w27, w20, w5", - "cset w21, hs", - "adc w22, w20, w5", - "uxtb w26, w22", - "cmp x26, x5", + "uxtb w21, w5", + "adc w22, wzr, w21", + "add w23, w20, w22", + "uxtb w26, w23", + "cmp w26, w22", "cset x22, lo", - "cmp x26, x5", - "cset x23, ls", - "cmp x21, #0x1 (1)", - "csel x21, x23, x22, eq", "cmn wzr, w26, lsl #24", - "mrs x22, nzcv", - "orr w21, w22, w21, lsl #29", - "eor w22, w20, w5", + "mrs x23, nzcv", + "orr w22, w23, w22, lsl #29", + "eor w21, w20, w21", "eor w20, w26, w20", - "bic w20, w20, w22", + "bic w20, w20, w21", "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "lock adc word [rax], cx": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Comment": "0x11", "ExpectedArm64ASM": [ "adc w20, wzr, w5", "ldaddalh w20, w20, [x4]", "eor w27, w20, w5", - "cset w21, hs", - "adc w22, w20, w5", - "uxth w26, w22", - "cmp x26, x5", + "uxth w21, w5", + "adc w22, wzr, w21", + "add w23, w20, w22", + "uxth w26, w23", + "cmp w26, w22", "cset x22, lo", - "cmp x26, x5", - "cset x23, ls", - "cmp x21, #0x1 (1)", - "csel x21, x23, x22, eq", "cmn wzr, w26, lsl #16", - "mrs x22, nzcv", - "orr w21, w22, w21, lsl #29", - "eor w22, w20, w5", + "mrs x23, nzcv", + "orr w22, w23, w22, lsl #29", + "eor w21, w20, w21", "eor w20, w26, w20", - "bic w20, w20, w22", + "bic w20, w20, w21", "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, @@ -133,23 +127,20 @@ ] }, "lock sbb byte [rax], cl": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 20, "Comment": "0x18", "ExpectedArm64ASM": [ "adc w20, wzr, w5", "neg w1, w20", "ldaddalb w1, w20, [x4]", "eor w27, w20, w5", + "uxtb w20, w20", "cset w21, hs", - "add w22, w5, w21", - "sub w22, w20, w22", + "sub w21, w20, w21", + "sub w22, w21, w5", "uxtb w26, w22", - "cmp w26, w20", - "cset x22, hi", - "cmp w26, w20", - "cset x23, hs", - "cmp x21, #0x1 (1)", - "csel x21, x23, x22, eq", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -162,23 +153,20 @@ ] }, "lock sbb word [rax], cx": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 20, "Comment": "0x19", "ExpectedArm64ASM": [ "adc w20, wzr, w5", "neg w1, w20", "ldaddalh w1, w20, [x4]", "eor w27, w20, w5", + "uxth w20, w20", "cset w21, hs", - "add w22, w5, w21", - "sub w22, w20, w22", + "sub w21, w20, w21", + "sub w22, w21, w5", "uxth w26, w22", - "cmp w26, w20", - "cset x22, hi", - "cmp w26, w20", - "cset x23, hs", - "cmp x21, #0x1 (1)", - "csel x21, x23, x22, eq", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -614,104 +602,100 @@ ] }, "lock adc byte [rax], 1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", - "ldaddalb w21, w27, [x4]", - "cset w21, hs", - "adc w20, w27, w20", - "uxtb w26, w20", - "cmp w26, #0x1 (1)", + "adc w20, wzr, w20", + "ldaddalb w20, w27, [x4]", + "mov w20, #0x1", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxtb w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x1 (1)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "bic w21, w26, w27", + "eor w21, w27, #0x1", + "eor w22, w26, w27", + "bic w21, w22, w21", "ubfx x21, x21, #7, #1", "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock adc byte [rax], 0xFF": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0xff", - "adc w21, wzr, w20", - "ldaddalb w21, w21, [x4]", - "mvn w27, w21", - "cset w22, hs", - "adc w20, w21, w20", - "uxtb w26, w20", - "cmp w26, #0xff (255)", - "cset x20, lo", - "cmp w26, #0xff (255)", - "cset x23, ls", - "cmp x22, #0x1 (1)", - "csel x20, x23, x20, eq", + "adc w20, wzr, w20", + "ldaddalb w20, w20, [x4]", + "mvn w27, w20", + "mov w21, #0xff", + "adc w21, wzr, w21", + "add w22, w20, w21", + "uxtb w26, w22", + "cmp w26, w21", + "cset x21, lo", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "bic w21, w21, w26", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "orr w21, w22, w21, lsl #29", + "eor w22, w20, #0xff", + "eor w20, w26, w20", + "bic w20, w20, w22", + "ubfx x20, x20, #7, #1", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "lock adc word [rax], 0x100": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w21, wzr, w20", - "ldaddalh w21, w27, [x4]", - "cset w21, hs", - "adc w20, w27, w20", - "uxth w26, w20", - "cmp w26, #0x100 (256)", + "adc w20, wzr, w20", + "ldaddalh w20, w27, [x4]", + "mov w20, #0x100", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxth w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x100 (256)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "bic w21, w26, w27", + "eor w21, w27, #0x100", + "eor w22, w26, w27", + "bic w21, w22, w21", "ubfx x21, x21, #15, #1", "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock adc word [rax], 0xFFFF": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "adc w21, wzr, w20", - "ldaddalh w21, w21, [x4]", - "mvn w27, w21", - "cset w22, hs", - "adc w23, w21, w20", - "uxth w26, w23", - "cmp w26, w20", - "cset x23, lo", - "cmp w26, w20", - "cset x20, ls", - "cmp x22, #0x1 (1)", - "csel x20, x20, x23, eq", + "adc w20, wzr, w20", + "ldaddalh w20, w20, [x4]", + "mvn w27, w20", + "mov w21, #0xffff", + "adc w21, wzr, w21", + "add w22, w20, w21", + "uxth w26, w22", + "cmp w26, w21", + "cset x21, lo", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "bic w21, w21, w26", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", + "orr w21, w22, w21, lsl #29", + "eor w22, w20, #0xffff", + "eor w20, w26, w20", + "bic w20, w20, w22", + "ubfx x20, x20, #15, #1", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, @@ -757,25 +741,24 @@ ] }, "lock adc word [rax], 1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", - "ldaddalh w21, w27, [x4]", - "cset w21, hs", - "adc w20, w27, w20", - "uxth w26, w20", - "cmp w26, #0x1 (1)", + "adc w20, wzr, w20", + "ldaddalh w20, w27, [x4]", + "mov w20, #0x1", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxth w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x1 (1)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "bic w21, w26, w27", + "eor w21, w27, #0x1", + "eor w22, w26, w27", + "bic w21, w22, w21", "ubfx x21, x21, #15, #1", "orr w20, w20, w21, lsl #28", "msr nzcv, x20" @@ -802,89 +785,80 @@ ] }, "lock sbb byte [rax], 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", - "neg w1, w21", + "adc w20, wzr, w20", + "neg w1, w20", "ldaddalb w1, w27, [x4]", + "uxtb w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxtb w26, w20", - "cmp w26, w27", - "cset x20, hi", - "cmp w26, w27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x1 (1)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "bic w21, w27, w26", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "bic w20, w20, w26", + "ubfx x20, x20, #7, #1", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "lock sbb byte [rax], 0xFF": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0xff", - "adc w21, wzr, w20", - "neg w1, w21", - "ldaddalb w1, w21, [x4]", - "mvn w27, w21", - "cset w22, hs", - "add w20, w20, w22", - "sub w20, w21, w20", - "uxtb w26, w20", - "cmp w26, w21", - "cset x20, hi", - "cmp w26, w21", - "cset x23, hs", - "cmp x22, #0x1 (1)", - "csel x20, x23, x20, eq", + "adc w20, wzr, w20", + "neg w1, w20", + "ldaddalb w1, w20, [x4]", + "mvn w27, w20", + "uxtb w20, w20", + "cset w21, hs", + "sub w21, w20, w21", + "sub w22, w21, #0xff (255)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "bic w21, w26, w21", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "orr w21, w22, w21, lsl #29", + "bic w20, w26, w20", + "ubfx x20, x20, #7, #1", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "lock sbb word [rax], 0x100": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w21, wzr, w20", - "neg w1, w21", + "adc w20, wzr, w20", + "neg w1, w20", "ldaddalh w1, w27, [x4]", + "uxth w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxth w26, w20", - "cmp w26, w27", - "cset x20, hi", - "cmp w26, w27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x100 (256)", + "uxth w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "bic w21, w27, w26", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "bic w20, w20, w26", + "ubfx x20, x20, #15, #1", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "lock sbb word [rax], 0xFFFF": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -892,16 +866,13 @@ "neg w1, w21", "ldaddalh w1, w21, [x4]", "mvn w27, w21", + "uxth w21, w21", "cset w22, hs", - "add w20, w20, w22", - "sub w20, w21, w20", + "sub w22, w21, w22", + "sub w20, w22, w20", "uxth w26, w20", - "cmp w26, w21", - "cset x20, hi", - "cmp w26, w21", - "cset x23, hs", - "cmp x22, #0x1 (1)", - "csel x20, x23, x20, eq", + "cmp w22, w26", + "cset x20, lo", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", "orr w20, w22, w20, lsl #29", @@ -981,29 +952,26 @@ ] }, "lock sbb word [rax], 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", - "neg w1, w21", + "adc w20, wzr, w20", + "neg w1, w20", "ldaddalh w1, w27, [x4]", + "uxth w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxth w26, w20", - "cmp w26, w27", - "cset x20, hi", - "cmp w26, w27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x1 (1)", + "uxth w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "bic w21, w27, w26", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "bic w20, w20, w26", + "ubfx x20, x20, #15, #1", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index d535a3386d..1f5f2406d5 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -70,48 +70,42 @@ ] }, "lock adc byte [rax], cl": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 15, "Comment": "0x10", "ExpectedArm64ASM": [ "adc w20, wzr, w5", "ldaddalb w20, w20, [x4]", "eor w27, w20, w5", - "cset w21, hs", - "adc w22, w20, w5", - "uxtb w26, w22", - "cmp x26, x5", + "uxtb w21, w5", + "adc w22, wzr, w21", + "add w23, w20, w22", + "uxtb w26, w23", + "cmp w26, w22", "cset x22, lo", - "cmp x26, x5", - "cset x23, ls", - "cmp x21, #0x1 (1)", - "csel x21, x23, x22, eq", "cmn wzr, w26, lsl #24", - "rmif x21, #63, #nzCv", - "eor w21, w20, w5", + "rmif x22, #63, #nzCv", + "eor w21, w20, w21", "eor w20, w26, w20", "bic w20, w20, w21", "rmif x20, #7, #nzcV" ] }, "lock adc word [rax], cx": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 15, "Comment": "0x11", "ExpectedArm64ASM": [ "adc w20, wzr, w5", "ldaddalh w20, w20, [x4]", "eor w27, w20, w5", - "cset w21, hs", - "adc w22, w20, w5", - "uxth w26, w22", - "cmp x26, x5", + "uxth w21, w5", + "adc w22, wzr, w21", + "add w23, w20, w22", + "uxth w26, w23", + "cmp w26, w22", "cset x22, lo", - "cmp x26, x5", - "cset x23, ls", - "cmp x21, #0x1 (1)", - "csel x21, x23, x22, eq", "cmn wzr, w26, lsl #16", - "rmif x21, #63, #nzCv", - "eor w21, w20, w5", + "rmif x22, #63, #nzCv", + "eor w21, w20, w21", "eor w20, w26, w20", "bic w20, w20, w21", "rmif x20, #15, #nzcV" @@ -128,23 +122,20 @@ ] }, "lock sbb byte [rax], cl": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 17, "Comment": "0x18", "ExpectedArm64ASM": [ "adc w20, wzr, w5", "neg w1, w20", "ldaddalb w1, w20, [x4]", "eor w27, w20, w5", + "uxtb w20, w20", "cset w21, hs", - "add w22, w5, w21", - "sub w22, w20, w22", + "sub w21, w20, w21", + "sub w22, w21, w5", "uxtb w26, w22", - "cmp w26, w20", - "cset x22, hi", - "cmp w26, w20", - "cset x23, hs", - "cmp x21, #0x1 (1)", - "csel x21, x23, x22, eq", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", "rmif x21, #63, #nzCv", "eor w21, w20, w5", @@ -154,23 +145,20 @@ ] }, "lock sbb word [rax], cx": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 17, "Comment": "0x19", "ExpectedArm64ASM": [ "adc w20, wzr, w5", "neg w1, w20", "ldaddalh w1, w20, [x4]", "eor w27, w20, w5", + "uxth w20, w20", "cset w21, hs", - "add w22, w5, w21", - "sub w22, w20, w22", + "sub w21, w20, w21", + "sub w22, w21, w5", "uxth w26, w22", - "cmp w26, w20", - "cset x22, hi", - "cmp w26, w20", - "cset x23, hs", - "cmp x21, #0x1 (1)", - "csel x21, x23, x22, eq", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", "rmif x21, #63, #nzCv", "eor w21, w20, w5", @@ -563,92 +551,88 @@ ] }, "lock adc byte [rax], 1": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 15, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", - "ldaddalb w21, w27, [x4]", - "cset w21, hs", - "adc w20, w27, w20", - "uxtb w26, w20", - "cmp w26, #0x1 (1)", + "adc w20, wzr, w20", + "ldaddalb w20, w27, [x4]", + "mov w20, #0x1", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxtb w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x1 (1)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", - "bic w20, w26, w27", + "eor w20, w27, #0x1", + "eor w21, w26, w27", + "bic w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "lock adc byte [rax], 0xFF": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0xff", - "adc w21, wzr, w20", - "ldaddalb w21, w21, [x4]", - "mvn w27, w21", - "cset w22, hs", - "adc w20, w21, w20", - "uxtb w26, w20", - "cmp w26, #0xff (255)", - "cset x20, lo", - "cmp w26, #0xff (255)", - "cset x23, ls", - "cmp x22, #0x1 (1)", - "csel x20, x23, x20, eq", + "adc w20, wzr, w20", + "ldaddalb w20, w20, [x4]", + "mvn w27, w20", + "mov w21, #0xff", + "adc w21, wzr, w21", + "add w22, w20, w21", + "uxtb w26, w22", + "cmp w26, w21", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", - "bic w20, w21, w26", + "rmif x21, #63, #nzCv", + "eor w21, w20, #0xff", + "eor w20, w26, w20", + "bic w20, w20, w21", "rmif x20, #7, #nzcV" ] }, "lock adc word [rax], 0x100": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 15, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w21, wzr, w20", - "ldaddalh w21, w27, [x4]", - "cset w21, hs", - "adc w20, w27, w20", - "uxth w26, w20", - "cmp w26, #0x100 (256)", + "adc w20, wzr, w20", + "ldaddalh w20, w27, [x4]", + "mov w20, #0x100", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxth w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x100 (256)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", - "bic w20, w26, w27", + "eor w20, w27, #0x100", + "eor w21, w26, w27", + "bic w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "lock adc word [rax], 0xFFFF": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "adc w21, wzr, w20", - "ldaddalh w21, w21, [x4]", - "mvn w27, w21", - "cset w22, hs", - "adc w23, w21, w20", - "uxth w26, w23", - "cmp w26, w20", - "cset x23, lo", - "cmp w26, w20", - "cset x20, ls", - "cmp x22, #0x1 (1)", - "csel x20, x20, x23, eq", + "adc w20, wzr, w20", + "ldaddalh w20, w20, [x4]", + "mvn w27, w20", + "mov w21, #0xffff", + "adc w21, wzr, w21", + "add w22, w20, w21", + "uxth w26, w22", + "cmp w26, w21", + "cset x21, lo", "cmn wzr, w26, lsl #16", - "rmif x20, #63, #nzCv", - "bic w20, w21, w26", + "rmif x21, #63, #nzCv", + "eor w21, w20, #0xffff", + "eor w20, w26, w20", + "bic w20, w20, w21", "rmif x20, #15, #nzcV" ] }, @@ -694,24 +678,23 @@ ] }, "lock adc word [rax], 1": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 15, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", - "ldaddalh w21, w27, [x4]", - "cset w21, hs", - "adc w20, w27, w20", - "uxth w26, w20", - "cmp w26, #0x1 (1)", + "adc w20, wzr, w20", + "ldaddalh w20, w27, [x4]", + "mov w20, #0x1", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxth w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x1 (1)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", - "bic w20, w26, w27", + "eor w20, w27, #0x1", + "eor w21, w26, w27", + "bic w20, w21, w20", "rmif x20, #15, #nzcV" ] }, @@ -736,80 +719,71 @@ ] }, "lock sbb byte [rax], 1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 15, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", - "neg w1, w21", + "adc w20, wzr, w20", + "neg w1, w20", "ldaddalb w1, w27, [x4]", + "uxtb w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxtb w26, w20", - "cmp w26, w27", - "cset x20, hi", - "cmp w26, w27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x1 (1)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", - "bic w20, w27, w26", + "rmif x21, #63, #nzCv", + "bic w20, w20, w26", "rmif x20, #7, #nzcV" ] }, "lock sbb byte [rax], 0xFF": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 16, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0xff", - "adc w21, wzr, w20", - "neg w1, w21", - "ldaddalb w1, w21, [x4]", - "mvn w27, w21", - "cset w22, hs", - "add w20, w20, w22", - "sub w20, w21, w20", - "uxtb w26, w20", - "cmp w26, w21", - "cset x20, hi", - "cmp w26, w21", - "cset x23, hs", - "cmp x22, #0x1 (1)", - "csel x20, x23, x20, eq", + "adc w20, wzr, w20", + "neg w1, w20", + "ldaddalb w1, w20, [x4]", + "mvn w27, w20", + "uxtb w20, w20", + "cset w21, hs", + "sub w21, w20, w21", + "sub w22, w21, #0xff (255)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", - "bic w20, w26, w21", + "rmif x21, #63, #nzCv", + "bic w20, w26, w20", "rmif x20, #7, #nzcV" ] }, "lock sbb word [rax], 0x100": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 15, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w21, wzr, w20", - "neg w1, w21", + "adc w20, wzr, w20", + "neg w1, w20", "ldaddalh w1, w27, [x4]", + "uxth w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxth w26, w20", - "cmp w26, w27", - "cset x20, hi", - "cmp w26, w27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x100 (256)", + "uxth w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", - "rmif x20, #63, #nzCv", - "bic w20, w27, w26", + "rmif x21, #63, #nzCv", + "bic w20, w20, w26", "rmif x20, #15, #nzcV" ] }, "lock sbb word [rax], 0xFFFF": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 16, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -817,16 +791,13 @@ "neg w1, w21", "ldaddalh w1, w21, [x4]", "mvn w27, w21", + "uxth w21, w21", "cset w22, hs", - "add w20, w20, w22", - "sub w20, w21, w20", + "sub w22, w21, w22", + "sub w20, w22, w20", "uxth w26, w20", - "cmp w26, w21", - "cset x20, hi", - "cmp w26, w21", - "cset x23, hs", - "cmp x22, #0x1 (1)", - "csel x20, x23, x20, eq", + "cmp w22, w26", + "cset x20, lo", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", "bic w20, w26, w21", @@ -887,26 +858,23 @@ ] }, "lock sbb word [rax], 1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 15, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", - "neg w1, w21", + "adc w20, wzr, w20", + "neg w1, w20", "ldaddalh w1, w27, [x4]", + "uxth w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxth w26, w20", - "cmp w26, w27", - "cset x20, hi", - "cmp w26, w27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x1 (1)", + "uxth w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", - "rmif x20, #63, #nzCv", - "bic w20, w27, w26", + "rmif x21, #63, #nzCv", + "bic w20, w20, w26", "rmif x20, #15, #nzcV" ] }, diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index b34877fcb8..73bc780128 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -359,22 +359,19 @@ ] }, "adc bl, cl": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Comment": "0x10", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "cset w20, hs", - "adc w21, w7, w5", - "uxtb w26, w21", - "cmp x26, x5", + "uxtb w20, w5", + "adc w21, wzr, w20", + "add w22, w7, w21", + "uxtb w26, w22", + "cmp w26, w21", "cset x21, lo", - "cmp x26, x5", - "cset x22, ls", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", - "eor w20, w7, w5", + "rmif x21, #63, #nzCv", + "eor w20, w7, w20", "eor w21, w26, w7", "bic w20, w21, w20", "rmif x20, #7, #nzcV", @@ -382,22 +379,19 @@ ] }, "adc bx, cx": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Comment": "0x11", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "cset w20, hs", - "adc w21, w7, w5", - "uxth w26, w21", - "cmp x26, x5", + "uxth w20, w5", + "adc w21, wzr, w20", + "add w22, w7, w21", + "uxth w26, w22", + "cmp w26, w21", "cset x21, lo", - "cmp x26, x5", - "cset x22, ls", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", "cmn wzr, w26, lsl #16", - "rmif x20, #63, #nzCv", - "eor w20, w7, w5", + "rmif x21, #63, #nzCv", + "eor w20, w7, w20", "eor w21, w26, w7", "bic w20, w21, w20", "rmif x20, #15, #nzcV", @@ -423,25 +417,22 @@ ] }, "db 0x12, 0xcb": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Comment": [ "0x12", "adc bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "cset w20, hs", - "adc w21, w5, w7", - "uxtb w26, w21", - "cmp x26, x7", + "uxtb w20, w7", + "adc w21, wzr, w20", + "add w22, w5, w21", + "uxtb w26, w22", + "cmp w26, w21", "cset x21, lo", - "cmp x26, x7", - "cset x22, ls", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", - "eor w20, w5, w7", + "rmif x21, #63, #nzCv", + "eor w20, w5, w20", "eor w21, w26, w5", "bic w20, w21, w20", "rmif x20, #7, #nzcV", @@ -449,25 +440,22 @@ ] }, "db 0x66, 0x13, 0xcb": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Comment": [ "0x13", "adc bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "cset w20, hs", - "adc w21, w5, w7", - "uxth w26, w21", - "cmp x26, x7", + "uxth w20, w7", + "adc w21, wzr, w20", + "add w22, w5, w21", + "uxth w26, w22", + "cmp w26, w21", "cset x21, lo", - "cmp x26, x7", - "cset x22, ls", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", "cmn wzr, w26, lsl #16", - "rmif x20, #63, #nzCv", - "eor w20, w5, w7", + "rmif x21, #63, #nzCv", + "eor w20, w5, w20", "eor w21, w26, w5", "bic w20, w21, w20", "rmif x20, #15, #nzcV", @@ -499,46 +487,42 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x14", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", - "cset w21, hs", - "adc w20, w27, w20", - "uxtb w26, w20", - "cmp w26, #0x1 (1)", + "mov w20, #0x1", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxtb w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x1 (1)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", - "bic w20, w26, w27", + "eor w20, w27, #0x1", + "eor w21, w26, w27", + "bic w20, w21, w20", "rmif x20, #7, #nzcV", "mov x4, x27", "bfxil x4, x26, #0, #8" ] }, "adc ax, 1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x15", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", - "cset w21, hs", - "adc w20, w27, w20", - "uxth w26, w20", - "cmp w26, #0x1 (1)", + "mov w20, #0x1", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxth w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x1 (1)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", - "bic w20, w26, w27", + "eor w20, w27, #0x1", + "eor w21, w26, w27", + "bic w20, w21, w20", "rmif x20, #15, #nzcV", "mov x4, x27", "bfxil x4, x26, #0, #16" @@ -565,45 +549,41 @@ ] }, "adc al, -1": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0x14", "ExpectedArm64ASM": [ - "mov w20, #0xff", "mvn w27, w4", - "cset w21, hs", - "adc w20, w4, w20", - "uxtb w26, w20", - "cmp w26, #0xff (255)", + "mov w20, #0xff", + "adc w20, wzr, w20", + "add w21, w4, w20", + "uxtb w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0xff (255)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", - "bic w20, w4, w26", + "eor w20, w4, #0xff", + "eor w21, w26, w4", + "bic w20, w21, w20", "rmif x20, #7, #nzcV", "bfxil x4, x26, #0, #8" ] }, "adc ax, -1": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0x15", "ExpectedArm64ASM": [ - "mov w20, #0xffff", "mvn w27, w4", - "cset w21, hs", - "adc w22, w4, w20", - "uxth w26, w22", - "cmp w26, w20", - "cset x22, lo", + "mov w20, #0xffff", + "adc w20, wzr, w20", + "add w21, w4, w20", + "uxth w26, w21", "cmp w26, w20", - "cset x20, ls", - "cmp x21, #0x1 (1)", - "csel x20, x20, x22, eq", + "cset x20, lo", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", - "bic w20, w4, w26", + "eor w20, w4, #0xffff", + "eor w21, w26, w4", + "bic w20, w21, w20", "rmif x20, #15, #nzcV", "bfxil x4, x26, #0, #16" ] @@ -629,49 +609,43 @@ ] }, "sbb bl, cl": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 15, "Comment": "0x18", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "cset w20, hs", - "add w21, w5, w20", - "sub w21, w7, w21", - "uxtb w26, w21", - "cmp x26, x7", - "cset x21, hi", - "cmp x26, x7", - "cset x22, hs", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", + "uxtb w20, w7", + "cset w21, hs", + "sub w21, w20, w21", + "sub w22, w21, w5", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", - "eor w20, w7, w5", - "eor w21, w26, w7", - "and w20, w21, w20", + "rmif x21, #63, #nzCv", + "eor w21, w20, w5", + "eor w20, w26, w20", + "and w20, w20, w21", "rmif x20, #7, #nzcV", "bfxil x7, x26, #0, #8" ] }, "sbb bx, cx": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 15, "Comment": "0x19", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "cset w20, hs", - "add w21, w5, w20", - "sub w21, w7, w21", - "uxth w26, w21", - "cmp x26, x7", - "cset x21, hi", - "cmp x26, x7", - "cset x22, hs", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", + "uxth w20, w7", + "cset w21, hs", + "sub w21, w20, w21", + "sub w22, w21, w5", + "uxth w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", - "rmif x20, #63, #nzCv", - "eor w20, w7, w5", - "eor w21, w26, w7", - "and w20, w21, w20", + "rmif x21, #63, #nzCv", + "eor w21, w20, w5", + "eor w20, w26, w20", + "and w20, w20, w21", "rmif x20, #15, #nzcV", "bfxil x7, x26, #0, #16" ] @@ -699,55 +673,49 @@ ] }, "db 0x1A, 0xcb": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 15, "Comment": [ "0x1A", "sbb bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "cset w20, hs", - "add w21, w7, w20", - "sub w21, w5, w21", - "uxtb w26, w21", - "cmp x26, x5", - "cset x21, hi", - "cmp x26, x5", - "cset x22, hs", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", + "uxtb w20, w5", + "cset w21, hs", + "sub w21, w20, w21", + "sub w22, w21, w7", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", - "eor w20, w5, w7", - "eor w21, w26, w5", - "and w20, w21, w20", + "rmif x21, #63, #nzCv", + "eor w21, w20, w7", + "eor w20, w26, w20", + "and w20, w20, w21", "rmif x20, #7, #nzcV", "bfxil x5, x26, #0, #8" ] }, "db 0x66, 0x1B, 0xcb": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 15, "Comment": [ "0x1B", "sbb bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "cset w20, hs", - "add w21, w7, w20", - "sub w21, w5, w21", - "uxth w26, w21", - "cmp x26, x5", - "cset x21, hi", - "cmp x26, x5", - "cset x22, hs", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", + "uxth w20, w5", + "cset w21, hs", + "sub w21, w20, w21", + "sub w22, w21, w7", + "uxth w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", - "rmif x20, #63, #nzCv", - "eor w20, w5, w7", - "eor w21, w26, w5", - "and w20, w21, w20", + "rmif x21, #63, #nzCv", + "eor w21, w20, w7", + "eor w20, w26, w20", + "and w20, w20, w21", "rmif x20, #15, #nzcV", "bfxil x5, x26, #0, #16" ] @@ -781,48 +749,40 @@ ] }, "sbb al, 1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 14, "Comment": "0x1C", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", + "uxtb w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxtb w26, w20", - "cmp x26, x27", - "cset x20, hi", - "cmp x26, x27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x1 (1)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", - "bic w20, w27, w26", + "rmif x21, #63, #nzCv", + "bic w20, w20, w26", "rmif x20, #7, #nzcV", "mov x4, x27", "bfxil x4, x26, #0, #8" ] }, "sbb ax, 1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 14, "Comment": "0x1D", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", + "uxth w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxth w26, w20", - "cmp x26, x27", - "cset x20, hi", - "cmp x26, x27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x1 (1)", + "uxth w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", - "rmif x20, #63, #nzCv", - "bic w20, w27, w26", + "rmif x21, #63, #nzCv", + "bic w20, w20, w26", "rmif x20, #15, #nzcV", "mov x4, x27", "bfxil x4, x26, #0, #16" @@ -853,47 +813,40 @@ ] }, "sbb al, -1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 13, "Comment": "0x1C", "ExpectedArm64ASM": [ - "mov w20, #0xff", "mvn w27, w4", + "uxtb w20, w4", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w4, w20", - "uxtb w26, w20", - "cmp x26, x4", - "cset x20, hi", - "cmp x26, x4", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0xff (255)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", - "bic w20, w26, w4", + "rmif x21, #63, #nzCv", + "bic w20, w26, w20", "rmif x20, #7, #nzcV", "bfxil x4, x26, #0, #8" ] }, "sbb ax, -1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0xffff", "mvn w27, w4", - "cset w21, hs", - "add w20, w20, w21", - "sub w20, w4, w20", + "uxth w21, w4", + "cset w22, hs", + "sub w22, w21, w22", + "sub w20, w22, w20", "uxth w26, w20", - "cmp x26, x4", - "cset x20, hi", - "cmp x26, x4", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "cmp w22, w26", + "cset x20, lo", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", - "bic w20, w26, w4", + "bic w20, w26, w21", "rmif x20, #15, #nzcV", "bfxil x4, x26, #0, #16" ] diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index 6c1b652617..5a56a1b424 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -34,47 +34,41 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", - "cset w21, hs", - "adc w20, w27, w20", - "uxtb w26, w20", - "cmp w26, #0x1 (1)", + "mov w20, #0x1", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxtb w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x1 (1)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", - "bic w20, w26, w27", + "eor w20, w27, #0x1", + "eor w21, w26, w27", + "bic w20, w21, w20", "rmif x20, #7, #nzcV", "mov x4, x27", "bfxil x4, x26, #0, #8" ] }, "sbb al, 1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 14, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", + "uxtb w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxtb w26, w20", - "cmp x26, x27", - "cset x20, hi", - "cmp x26, x27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x1 (1)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", - "bic w20, w27, w26", + "rmif x21, #63, #nzCv", + "bic w20, w20, w26", "rmif x20, #7, #nzcV", "mov x4, x27", "bfxil x4, x26, #0, #8" @@ -146,46 +140,40 @@ ] }, "adc al, -1": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ - "mov w20, #0xff", "mvn w27, w4", - "cset w21, hs", - "adc w20, w4, w20", - "uxtb w26, w20", - "cmp w26, #0xff (255)", + "mov w20, #0xff", + "adc w20, wzr, w20", + "add w21, w4, w20", + "uxtb w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0xff (255)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", - "bic w20, w4, w26", + "eor w20, w4, #0xff", + "eor w21, w26, w4", + "bic w20, w21, w20", "rmif x20, #7, #nzcV", "bfxil x4, x26, #0, #8" ] }, "sbb al, -1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ - "mov w20, #0xff", "mvn w27, w4", + "uxtb w20, w4", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w4, w20", - "uxtb w26, w20", - "cmp x26, x4", - "cset x20, hi", - "cmp x26, x4", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0xff (255)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", - "bic w20, w26, w4", + "rmif x21, #63, #nzCv", + "bic w20, w26, w20", "rmif x20, #7, #nzcV", "bfxil x4, x26, #0, #8" ] diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 5fcaf32e0c..f50f1aa9c4 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -358,53 +358,47 @@ ] }, "adc bl, cl": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 17, "Comment": "0x10", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "cset w20, hs", - "adc w21, w7, w5", - "uxtb w26, w21", - "cmp x26, x5", + "uxtb w20, w5", + "adc w21, wzr, w20", + "add w22, w7, w21", + "uxtb w26, w22", + "cmp w26, w21", "cset x21, lo", - "cmp x26, x5", - "cset x22, ls", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", "cmn wzr, w26, lsl #24", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w7, w5", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor w20, w7, w20", "eor w22, w26, w7", - "bic w21, w22, w21", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "bic w20, w22, w20", + "ubfx x20, x20, #7, #1", + "orr w20, w21, w20, lsl #28", "bfxil x7, x26, #0, #8", "msr nzcv, x20" ] }, "adc bx, cx": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 17, "Comment": "0x11", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "cset w20, hs", - "adc w21, w7, w5", - "uxth w26, w21", - "cmp x26, x5", + "uxth w20, w5", + "adc w21, wzr, w20", + "add w22, w7, w21", + "uxth w26, w22", + "cmp w26, w21", "cset x21, lo", - "cmp x26, x5", - "cset x22, ls", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", "cmn wzr, w26, lsl #16", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w7, w5", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor w20, w7, w20", "eor w22, w26, w7", - "bic w21, w22, w21", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", + "bic w20, w22, w20", + "ubfx x20, x20, #15, #1", + "orr w20, w21, w20, lsl #28", "bfxil x7, x26, #0, #16", "msr nzcv, x20" ] @@ -428,59 +422,53 @@ ] }, "db 0x12, 0xcb": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 17, "Comment": [ "0x12", "adc bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "cset w20, hs", - "adc w21, w5, w7", - "uxtb w26, w21", - "cmp x26, x7", + "uxtb w20, w7", + "adc w21, wzr, w20", + "add w22, w5, w21", + "uxtb w26, w22", + "cmp w26, w21", "cset x21, lo", - "cmp x26, x7", - "cset x22, ls", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", "cmn wzr, w26, lsl #24", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w5, w7", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor w20, w5, w20", "eor w22, w26, w5", - "bic w21, w22, w21", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "bic w20, w22, w20", + "ubfx x20, x20, #7, #1", + "orr w20, w21, w20, lsl #28", "bfxil x5, x26, #0, #8", "msr nzcv, x20" ] }, "db 0x66, 0x13, 0xcb": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 17, "Comment": [ "0x13", "adc bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "cset w20, hs", - "adc w21, w5, w7", - "uxth w26, w21", - "cmp x26, x7", + "uxth w20, w7", + "adc w21, wzr, w20", + "add w22, w5, w21", + "uxth w26, w22", + "cmp w26, w21", "cset x21, lo", - "cmp x26, x7", - "cset x22, ls", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", "cmn wzr, w26, lsl #16", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w5, w7", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor w20, w5, w20", "eor w22, w26, w5", - "bic w21, w22, w21", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", + "bic w20, w22, w20", + "ubfx x20, x20, #15, #1", + "orr w20, w21, w20, lsl #28", "bfxil x5, x26, #0, #16", "msr nzcv, x20" ] @@ -510,24 +498,22 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0x14", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", - "cset w21, hs", - "adc w20, w27, w20", - "uxtb w26, w20", - "cmp w26, #0x1 (1)", + "mov w20, #0x1", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxtb w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x1 (1)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "bic w21, w26, w27", + "eor w21, w27, #0x1", + "eor w22, w26, w27", + "bic w21, w22, w21", "ubfx x21, x21, #7, #1", "orr w20, w20, w21, lsl #28", "mov x4, x27", @@ -536,24 +522,22 @@ ] }, "adc ax, 1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0x15", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", - "cset w21, hs", - "adc w20, w27, w20", - "uxth w26, w20", - "cmp w26, #0x1 (1)", + "mov w20, #0x1", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxth w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x1 (1)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "bic w21, w26, w27", + "eor w21, w27, #0x1", + "eor w22, w26, w27", + "bic w21, w22, w21", "ubfx x21, x21, #15, #1", "orr w20, w20, w21, lsl #28", "mov x4, x27", @@ -582,24 +566,22 @@ ] }, "adc al, -1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": "0x14", "ExpectedArm64ASM": [ - "mov w20, #0xff", "mvn w27, w4", - "cset w21, hs", - "adc w20, w4, w20", - "uxtb w26, w20", - "cmp w26, #0xff (255)", + "mov w20, #0xff", + "adc w20, wzr, w20", + "add w21, w4, w20", + "uxtb w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0xff (255)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "bic w21, w4, w26", + "eor w21, w4, #0xff", + "eor w22, w26, w4", + "bic w21, w22, w21", "ubfx x21, x21, #7, #1", "orr w20, w20, w21, lsl #28", "bfxil x4, x26, #0, #8", @@ -607,24 +589,22 @@ ] }, "adc ax, -1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": "0x15", "ExpectedArm64ASM": [ - "mov w20, #0xffff", "mvn w27, w4", - "cset w21, hs", - "adc w22, w4, w20", - "uxth w26, w22", - "cmp w26, w20", - "cset x22, lo", + "mov w20, #0xffff", + "adc w20, wzr, w20", + "add w21, w4, w20", + "uxth w26, w21", "cmp w26, w20", - "cset x20, ls", - "cmp x21, #0x1 (1)", - "csel x20, x20, x22, eq", + "cset x20, lo", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "bic w21, w4, w26", + "eor w21, w4, #0xffff", + "eor w22, w26, w4", + "bic w21, w22, w21", "ubfx x21, x21, #15, #1", "orr w20, w20, w21, lsl #28", "bfxil x4, x26, #0, #16", @@ -652,55 +632,49 @@ ] }, "sbb bl, cl": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Comment": "0x18", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "cset w20, hs", - "add w21, w5, w20", - "sub w21, w7, w21", - "uxtb w26, w21", - "cmp x26, x7", - "cset x21, hi", - "cmp x26, x7", - "cset x22, hs", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", + "uxtb w20, w7", + "cset w21, hs", + "sub w21, w20, w21", + "sub w22, w21, w5", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w7, w5", - "eor w22, w26, w7", - "and w21, w22, w21", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor w22, w20, w5", + "eor w20, w26, w20", + "and w20, w20, w22", + "ubfx x20, x20, #7, #1", + "orr w20, w21, w20, lsl #28", "bfxil x7, x26, #0, #8", "msr nzcv, x20" ] }, "sbb bx, cx": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Comment": "0x19", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "cset w20, hs", - "add w21, w5, w20", - "sub w21, w7, w21", - "uxth w26, w21", - "cmp x26, x7", - "cset x21, hi", - "cmp x26, x7", - "cset x22, hs", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", + "uxth w20, w7", + "cset w21, hs", + "sub w21, w20, w21", + "sub w22, w21, w5", + "uxth w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w7, w5", - "eor w22, w26, w7", - "and w21, w22, w21", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor w22, w20, w5", + "eor w20, w26, w20", + "and w20, w20, w22", + "ubfx x20, x20, #15, #1", + "orr w20, w21, w20, lsl #28", "bfxil x7, x26, #0, #16", "msr nzcv, x20" ] @@ -736,61 +710,55 @@ ] }, "db 0x1A, 0xcb": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Comment": [ "0x1A", "sbb bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "cset w20, hs", - "add w21, w7, w20", - "sub w21, w5, w21", - "uxtb w26, w21", - "cmp x26, x5", - "cset x21, hi", - "cmp x26, x5", - "cset x22, hs", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", + "uxtb w20, w5", + "cset w21, hs", + "sub w21, w20, w21", + "sub w22, w21, w7", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w5, w7", - "eor w22, w26, w5", - "and w21, w22, w21", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor w22, w20, w7", + "eor w20, w26, w20", + "and w20, w20, w22", + "ubfx x20, x20, #7, #1", + "orr w20, w21, w20, lsl #28", "bfxil x5, x26, #0, #8", "msr nzcv, x20" ] }, "db 0x66, 0x1B, 0xcb": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Comment": [ "0x1B", "sbb bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "cset w20, hs", - "add w21, w7, w20", - "sub w21, w5, w21", - "uxth w26, w21", - "cmp x26, x5", - "cset x21, hi", - "cmp x26, x5", - "cset x22, hs", - "cmp x20, #0x1 (1)", - "csel x20, x22, x21, eq", + "uxth w20, w5", + "cset w21, hs", + "sub w21, w20, w21", + "sub w22, w21, w7", + "uxth w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w5, w7", - "eor w22, w26, w5", - "and w21, w22, w21", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor w22, w20, w7", + "eor w20, w26, w20", + "and w20, w20, w22", + "ubfx x20, x20, #15, #1", + "orr w20, w21, w20, lsl #28", "bfxil x5, x26, #0, #16", "msr nzcv, x20" ] @@ -832,54 +800,46 @@ ] }, "sbb al, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 17, "Comment": "0x1C", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", + "uxtb w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxtb w26, w20", - "cmp x26, x27", - "cset x20, hi", - "cmp x26, x27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x1 (1)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "bic w21, w27, w26", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "bic w20, w20, w26", + "ubfx x20, x20, #7, #1", + "orr w20, w21, w20, lsl #28", "mov x4, x27", "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, "sbb ax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 17, "Comment": "0x1D", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", + "uxth w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxth w26, w20", - "cmp x26, x27", - "cset x20, hi", - "cmp x26, x27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x1 (1)", + "uxth w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #16", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "bic w21, w27, w26", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "bic w20, w20, w26", + "ubfx x20, x20, #15, #1", + "orr w20, w21, w20, lsl #28", "mov x4, x27", "bfxil x4, x26, #0, #16", "msr nzcv, x20" @@ -918,51 +878,44 @@ ] }, "sbb al, -1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 16, "Comment": "0x1C", "ExpectedArm64ASM": [ - "mov w20, #0xff", "mvn w27, w4", + "uxtb w20, w4", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w4, w20", - "uxtb w26, w20", - "cmp x26, x4", - "cset x20, hi", - "cmp x26, x4", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0xff (255)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "bic w21, w26, w4", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "bic w20, w26, w20", + "ubfx x20, x20, #7, #1", + "orr w20, w21, w20, lsl #28", "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, "sbb ax, -1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 17, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0xffff", "mvn w27, w4", - "cset w21, hs", - "add w20, w20, w21", - "sub w20, w4, w20", + "uxth w21, w4", + "cset w22, hs", + "sub w22, w21, w22", + "sub w20, w22, w20", "uxth w26, w20", - "cmp x26, x4", - "cset x20, hi", - "cmp x26, x4", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "cmp w22, w26", + "cset x20, lo", "cmn wzr, w26, lsl #16", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "bic w21, w26, w4", + "mrs x22, nzcv", + "orr w20, w22, w20, lsl #29", + "bic w21, w26, w21", "ubfx x21, x21, #15, #1", "orr w20, w20, w21, lsl #28", "bfxil x4, x26, #0, #16", diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 750f446f03..4e7f450da1 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -37,24 +37,22 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", - "cset w21, hs", - "adc w20, w27, w20", - "uxtb w26, w20", - "cmp w26, #0x1 (1)", + "mov w20, #0x1", + "adc w20, wzr, w20", + "add w21, w27, w20", + "uxtb w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0x1 (1)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "bic w21, w26, w27", + "eor w21, w27, #0x1", + "eor w22, w26, w27", + "bic w21, w22, w21", "ubfx x21, x21, #7, #1", "orr w20, w20, w21, lsl #28", "mov x4, x27", @@ -63,27 +61,23 @@ ] }, "sbb al, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 17, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ - "mov w20, #0x1", "mov x27, x4", + "uxtb w20, w27", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w27, w20", - "uxtb w26, w20", - "cmp x26, x27", - "cset x20, hi", - "cmp x26, x27", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0x1 (1)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "bic w21, w27, w26", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "bic w20, w20, w26", + "ubfx x20, x20, #7, #1", + "orr w20, w21, w20, lsl #28", "mov x4, x27", "bfxil x4, x26, #0, #8", "msr nzcv, x20" @@ -159,24 +153,22 @@ ] }, "adc al, -1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ - "mov w20, #0xff", "mvn w27, w4", - "cset w21, hs", - "adc w20, w4, w20", - "uxtb w26, w20", - "cmp w26, #0xff (255)", + "mov w20, #0xff", + "adc w20, wzr, w20", + "add w21, w4, w20", + "uxtb w26, w21", + "cmp w26, w20", "cset x20, lo", - "cmp w26, #0xff (255)", - "cset x22, ls", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "bic w21, w4, w26", + "eor w21, w4, #0xff", + "eor w22, w26, w4", + "bic w21, w22, w21", "ubfx x21, x21, #7, #1", "orr w20, w20, w21, lsl #28", "bfxil x4, x26, #0, #8", @@ -184,27 +176,23 @@ ] }, "sbb al, -1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 16, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ - "mov w20, #0xff", "mvn w27, w4", + "uxtb w20, w4", "cset w21, hs", - "add w20, w20, w21", - "sub w20, w4, w20", - "uxtb w26, w20", - "cmp x26, x4", - "cset x20, hi", - "cmp x26, x4", - "cset x22, hs", - "cmp x21, #0x1 (1)", - "csel x20, x22, x20, eq", + "sub w21, w20, w21", + "sub w22, w21, #0xff (255)", + "uxtb w26, w22", + "cmp w21, w26", + "cset x21, lo", "cmn wzr, w26, lsl #24", - "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "bic w21, w26, w4", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "bic w20, w26, w20", + "ubfx x20, x20, #7, #1", + "orr w20, w21, w20, lsl #28", "bfxil x4, x26, #0, #8", "msr nzcv, x20" ]