From ad0dd34412d253a408b7cf32e0b08af48dc038ff Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Sun, 31 Mar 2024 20:29:48 -0400 Subject: [PATCH] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- .../InstructionCountCI/FlagM/Primary.json | 356 +++++++++---- unittests/InstructionCountCI/Primary.json | 485 +++++++++++++----- 2 files changed, 626 insertions(+), 215 deletions(-) diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index b187d5b094..3fa39e3ba8 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -1950,16 +1950,27 @@ ] }, "repz cmpsb": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 26, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x3c", + "cbz x5, #+0x68", "ldrsb x20, [x28, #714]", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldrb w26, [x11]", "ldrb w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x1 (1)", + "add x10, x10, #0x1 (1)", + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x18", + "b #+0x20", + "ldrb w26, [x11]", + "ldrb w27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x1 (1)", + "sub x10, x10, #0x1 (1)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "mov x20, x27", @@ -1971,17 +1982,27 @@ ] }, "repz cmpsw": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x40", + "cbz x5, #+0x68", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #1", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldrh w26, [x11]", "ldrh w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x2 (2)", + "add x10, x10, #0x2 (2)", + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x18", + "b #+0x20", + "ldrh w26, [x11]", + "ldrh w27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x2 (2)", + "sub x10, x10, #0x2 (2)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "mov x20, x27", @@ -1993,17 +2014,27 @@ ] }, "repz cmpsd": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 24, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x38", + "cbz x5, #+0x60", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #2", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", + "ldr w26, [x11]", + "ldr w27, [x10]", + "subs x5, x5, #0x1 (1)", + "add x11, x11, #0x4 (4)", + "add x10, x10, #0x4 (4)", + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x18", + "b #+0x20", "ldr w26, [x11]", "ldr w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "sub x11, x11, #0x4 (4)", + "sub x10, x10, #0x4 (4)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "mov x20, x27", @@ -2013,17 +2044,27 @@ ] }, "repz cmpsq": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 24, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x38", + "cbz x5, #+0x60", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #3", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldr x26, [x11]", "ldr x27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x8 (8)", + "add x10, x10, #0x8 (8)", + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x18", + "b #+0x20", + "ldr x26, [x11]", + "ldr x27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x8 (8)", + "sub x10, x10, #0x8 (8)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "mov x20, x27", @@ -2033,16 +2074,27 @@ ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 26, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x3c", + "cbz x5, #+0x68", "ldrsb x20, [x28, #714]", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldrb w26, [x11]", "ldrb w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x1 (1)", + "add x10, x10, #0x1 (1)", + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x18", + "b #+0x20", + "ldrb w26, [x11]", + "ldrb w27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x1 (1)", + "sub x10, x10, #0x1 (1)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "mov x20, x27", @@ -2054,17 +2106,27 @@ ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x40", + "cbz x5, #+0x68", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #1", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", + "ldrh w26, [x11]", + "ldrh w27, [x10]", + "subs x5, x5, #0x1 (1)", + "add x11, x11, #0x2 (2)", + "add x10, x10, #0x2 (2)", + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x18", + "b #+0x20", "ldrh w26, [x11]", "ldrh w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "sub x11, x11, #0x2 (2)", + "sub x10, x10, #0x2 (2)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "mov x20, x27", @@ -2076,17 +2138,27 @@ ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 24, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x38", + "cbz x5, #+0x60", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #2", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldr w26, [x11]", "ldr w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x4 (4)", + "add x10, x10, #0x4 (4)", + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x18", + "b #+0x20", + "ldr w26, [x11]", + "ldr w27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x4 (4)", + "sub x10, x10, #0x4 (4)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "mov x20, x27", @@ -2096,17 +2168,27 @@ ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 24, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x38", + "cbz x5, #+0x60", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #3", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldr x26, [x11]", "ldr x27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x8 (8)", + "add x10, x10, #0x8 (8)", + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x18", + "b #+0x20", + "ldr x26, [x11]", + "ldr x27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x8 (8)", + "sub x10, x10, #0x8 (8)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "mov x20, x27", @@ -2228,136 +2310,234 @@ ] }, "repz scasb": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 25, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x30", + "cbz x5, #+0x28", + "ldrb w20, [x11]", + "eor w27, w4, w20", + "lsl w0, w4, #24", + "cmp w0, w20, lsl #24", + "sub w26, w4, w20", + "cfinv", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x1 (1)", + "b.eq #-0x24", + "b #+0x2c", "cbz x5, #+0x28", - "ldrb w21, [x11]", - "eor w27, w4, w21", + "ldrb w20, [x11]", + "eor w27, w4, w20", "lsl w0, w4, #24", - "cmp w0, w21, lsl #24", - "sub w26, w4, w21", + "cmp w0, w20, lsl #24", + "sub w26, w4, w20", "cfinv", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x1 (1)", "b.eq #-0x24" ] }, "repz scasw": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 25, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #1", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x30", "cbz x5, #+0x28", - "ldrh w21, [x11]", - "eor w27, w4, w21", + "ldrh w20, [x11]", + "eor w27, w4, w20", + "lsl w0, w4, #16", + "cmp w0, w20, lsl #16", + "sub w26, w4, w20", + "cfinv", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x2 (2)", + "b.eq #-0x24", + "b #+0x2c", + "cbz x5, #+0x28", + "ldrh w20, [x11]", + "eor w27, w4, w20", "lsl w0, w4, #16", - "cmp w0, w21, lsl #16", - "sub w26, w4, w21", + "cmp w0, w20, lsl #16", + "sub w26, w4, w20", "cfinv", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x2 (2)", "b.eq #-0x24" ] }, "repz scasd": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 21, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #2", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x28", "cbz x5, #+0x20", - "ldr w21, [x11]", - "eor w27, w4, w21", - "subs w26, w4, w21", + "ldr w20, [x11]", + "eor w27, w4, w20", + "subs w26, w4, w20", "cfinv", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "add x11, x11, #0x4 (4)", + "b.eq #-0x1c", + "b #+0x24", + "cbz x5, #+0x20", + "ldr w20, [x11]", + "eor w27, w4, w20", + "subs w26, w4, w20", + "cfinv", + "sub x5, x5, #0x1 (1)", + "sub x11, x11, #0x4 (4)", "b.eq #-0x1c" ] }, "repz scasq": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 21, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #3", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x28", + "cbz x5, #+0x20", + "ldr x20, [x11]", + "eor w27, w4, w20", + "subs x26, x4, x20", + "cfinv", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x8 (8)", + "b.eq #-0x1c", + "b #+0x24", "cbz x5, #+0x20", - "ldr x21, [x11]", - "eor w27, w4, w21", - "subs x26, x4, x21", + "ldr x20, [x11]", + "eor w27, w4, w20", + "subs x26, x4, x20", "cfinv", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x8 (8)", "b.eq #-0x1c" ] }, "repnz scasb": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 25, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x30", "cbz x5, #+0x28", - "ldrb w21, [x11]", - "eor w27, w4, w21", + "ldrb w20, [x11]", + "eor w27, w4, w20", + "lsl w0, w4, #24", + "cmp w0, w20, lsl #24", + "sub w26, w4, w20", + "cfinv", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x1 (1)", + "b.ne #-0x24", + "b #+0x2c", + "cbz x5, #+0x28", + "ldrb w20, [x11]", + "eor w27, w4, w20", "lsl w0, w4, #24", - "cmp w0, w21, lsl #24", - "sub w26, w4, w21", + "cmp w0, w20, lsl #24", + "sub w26, w4, w20", "cfinv", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x1 (1)", "b.ne #-0x24" ] }, "repnz scasw": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 25, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #1", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x30", "cbz x5, #+0x28", - "ldrh w21, [x11]", - "eor w27, w4, w21", + "ldrh w20, [x11]", + "eor w27, w4, w20", "lsl w0, w4, #16", - "cmp w0, w21, lsl #16", - "sub w26, w4, w21", + "cmp w0, w20, lsl #16", + "sub w26, w4, w20", "cfinv", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "add x11, x11, #0x2 (2)", + "b.ne #-0x24", + "b #+0x2c", + "cbz x5, #+0x28", + "ldrh w20, [x11]", + "eor w27, w4, w20", + "lsl w0, w4, #16", + "cmp w0, w20, lsl #16", + "sub w26, w4, w20", + "cfinv", + "sub x5, x5, #0x1 (1)", + "sub x11, x11, #0x2 (2)", "b.ne #-0x24" ] }, "repnz scasd": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 21, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #2", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x28", + "cbz x5, #+0x20", + "ldr w20, [x11]", + "eor w27, w4, w20", + "subs w26, w4, w20", + "cfinv", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x4 (4)", + "b.ne #-0x1c", + "b #+0x24", "cbz x5, #+0x20", - "ldr w21, [x11]", - "eor w27, w4, w21", - "subs w26, w4, w21", + "ldr w20, [x11]", + "eor w27, w4, w20", + "subs w26, w4, w20", "cfinv", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x4 (4)", "b.ne #-0x1c" ] }, "repnz scasq": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 21, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #3", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x28", "cbz x5, #+0x20", - "ldr x21, [x11]", - "eor w27, w4, w21", - "subs x26, x4, x21", + "ldr x20, [x11]", + "eor w27, w4, w20", + "subs x26, x4, x20", + "cfinv", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x8 (8)", + "b.ne #-0x1c", + "b #+0x24", + "cbz x5, #+0x20", + "ldr x20, [x11]", + "eor w27, w4, w20", + "subs x26, x4, x20", "cfinv", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x8 (8)", "b.ne #-0x1c" ] }, diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 26e1fac028..7590652008 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -3295,16 +3295,27 @@ ] }, "repz cmpsb": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 28, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x44", + "cbz x5, #+0x70", "ldrsb x20, [x28, #714]", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldrb w26, [x11]", "ldrb w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x1 (1)", + "add x10, x10, #0x1 (1)", + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x18", + "b #+0x20", + "ldrb w26, [x11]", + "ldrb w27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x1 (1)", + "sub x10, x10, #0x1 (1)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "mov x20, x27", @@ -3318,17 +3329,27 @@ ] }, "repz cmpsw": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 28, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x48", + "cbz x5, #+0x70", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #1", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldrh w26, [x11]", "ldrh w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x2 (2)", + "add x10, x10, #0x2 (2)", + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x18", + "b #+0x20", + "ldrh w26, [x11]", + "ldrh w27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x2 (2)", + "sub x10, x10, #0x2 (2)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "mov x20, x27", @@ -3342,17 +3363,27 @@ ] }, "repz cmpsd": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x40", + "cbz x5, #+0x68", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #2", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldr w26, [x11]", "ldr w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x4 (4)", + "add x10, x10, #0x4 (4)", + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x18", + "b #+0x20", + "ldr w26, [x11]", + "ldr w27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x4 (4)", + "sub x10, x10, #0x4 (4)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "mov x20, x27", @@ -3364,17 +3395,27 @@ ] }, "repz cmpsq": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x40", + "cbz x5, #+0x68", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #3", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldr x26, [x11]", "ldr x27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x8 (8)", + "add x10, x10, #0x8 (8)", + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x18", + "b #+0x20", + "ldr x26, [x11]", + "ldr x27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x8 (8)", + "sub x10, x10, #0x8 (8)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "mov x20, x27", @@ -3386,16 +3427,27 @@ ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 28, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x44", + "cbz x5, #+0x70", "ldrsb x20, [x28, #714]", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldrb w26, [x11]", "ldrb w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x1 (1)", + "add x10, x10, #0x1 (1)", + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x18", + "b #+0x20", + "ldrb w26, [x11]", + "ldrb w27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x1 (1)", + "sub x10, x10, #0x1 (1)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "mov x20, x27", @@ -3409,17 +3461,27 @@ ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 28, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x48", + "cbz x5, #+0x70", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #1", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldrh w26, [x11]", "ldrh w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x2 (2)", + "add x10, x10, #0x2 (2)", + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x18", + "b #+0x20", + "ldrh w26, [x11]", + "ldrh w27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x2 (2)", + "sub x10, x10, #0x2 (2)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "mov x20, x27", @@ -3433,17 +3495,27 @@ ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x40", + "cbz x5, #+0x68", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #2", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldr w26, [x11]", "ldr w27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x4 (4)", + "add x10, x10, #0x4 (4)", + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x18", + "b #+0x20", + "ldr w26, [x11]", + "ldr w27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x4 (4)", + "sub x10, x10, #0x4 (4)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "mov x20, x27", @@ -3455,17 +3527,27 @@ ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x40", + "cbz x5, #+0x68", "ldrsb x20, [x28, #714]", - "lsl x20, x20, #3", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x24", "ldr x26, [x11]", "ldr x27, [x10]", "subs x5, x5, #0x1 (1)", - "add x11, x11, x20", - "add x10, x10, x20", + "add x11, x11, #0x8 (8)", + "add x10, x10, #0x8 (8)", + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x18", + "b #+0x20", + "ldr x26, [x11]", + "ldr x27, [x10]", + "subs x5, x5, #0x1 (1)", + "sub x11, x11, #0x8 (8)", + "sub x10, x10, #0x8 (8)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "mov x20, x27", @@ -3858,55 +3940,90 @@ ] }, "rep lodsb": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 17, "Comment": "0xac", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x20", "cbz x5, #+0x18", - "ldrb w21, [x10]", - "bfxil x4, x21, #0, #8", + "ldrb w20, [x10]", + "bfxil x4, x20, #0, #8", "sub x5, x5, #0x1 (1)", - "add x10, x10, x20", + "add x10, x10, #0x1 (1)", + "b #-0x14", + "b #+0x1c", + "cbz x5, #+0x18", + "ldrb w20, [x10]", + "bfxil x4, x20, #0, #8", + "sub x5, x5, #0x1 (1)", + "sub x10, x10, #0x1 (1)", "b #-0x14" ] }, "rep lodsw": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 17, "Comment": "0xad", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #1", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x20", "cbz x5, #+0x18", - "ldrh w21, [x10]", - "bfxil x4, x21, #0, #16", + "ldrh w20, [x10]", + "bfxil x4, x20, #0, #16", "sub x5, x5, #0x1 (1)", - "add x10, x10, x20", + "add x10, x10, #0x2 (2)", + "b #-0x14", + "b #+0x1c", + "cbz x5, #+0x18", + "ldrh w20, [x10]", + "bfxil x4, x20, #0, #16", + "sub x5, x5, #0x1 (1)", + "sub x10, x10, #0x2 (2)", "b #-0x14" ] }, "rep lodsd": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 15, "Comment": "0xad", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #2", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x1c", "cbz x5, #+0x14", "ldr w4, [x10]", "sub x5, x5, #0x1 (1)", - "add x10, x10, x20", + "add x10, x10, #0x4 (4)", + "b #-0x10", + "b #+0x18", + "cbz x5, #+0x14", + "ldr w4, [x10]", + "sub x5, x5, #0x1 (1)", + "sub x10, x10, #0x4 (4)", "b #-0x10" ] }, "rep lodsq": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 15, "Comment": "0xad", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #3", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x1c", "cbz x5, #+0x14", "ldr x4, [x10]", "sub x5, x5, #0x1 (1)", - "add x10, x10, x20", + "add x10, x10, #0x8 (8)", + "b #-0x10", + "b #+0x18", + "cbz x5, #+0x14", + "ldr x4, [x10]", + "sub x5, x5, #0x1 (1)", + "sub x10, x10, #0x8 (8)", "b #-0x10" ] }, @@ -3971,152 +4088,266 @@ ] }, "repz scasb": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 29, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x38", + "cbz x5, #+0x30", + "ldrb w20, [x11]", + "eor w27, w4, w20", + "lsl w0, w4, #24", + "cmp w0, w20, lsl #24", + "sub w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x1 (1)", + "b.eq #-0x2c", + "b #+0x34", "cbz x5, #+0x30", - "ldrb w21, [x11]", - "eor w27, w4, w21", + "ldrb w20, [x11]", + "eor w27, w4, w20", "lsl w0, w4, #24", - "cmp w0, w21, lsl #24", - "sub w26, w4, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", + "cmp w0, w20, lsl #24", + "sub w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x1 (1)", "b.eq #-0x2c" ] }, "repz scasw": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 29, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #1", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x38", "cbz x5, #+0x30", - "ldrh w21, [x11]", - "eor w27, w4, w21", + "ldrh w20, [x11]", + "eor w27, w4, w20", "lsl w0, w4, #16", - "cmp w0, w21, lsl #16", - "sub w26, w4, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", + "cmp w0, w20, lsl #16", + "sub w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "add x11, x11, #0x2 (2)", + "b.eq #-0x2c", + "b #+0x34", + "cbz x5, #+0x30", + "ldrh w20, [x11]", + "eor w27, w4, w20", + "lsl w0, w4, #16", + "cmp w0, w20, lsl #16", + "sub w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", + "sub x5, x5, #0x1 (1)", + "sub x11, x11, #0x2 (2)", "b.eq #-0x2c" ] }, "repz scasd": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 25, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #2", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x30", "cbz x5, #+0x28", - "ldr w21, [x11]", - "eor w27, w4, w21", - "subs w26, w4, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", + "ldr w20, [x11]", + "eor w27, w4, w20", + "subs w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x4 (4)", + "b.eq #-0x24", + "b #+0x2c", + "cbz x5, #+0x28", + "ldr w20, [x11]", + "eor w27, w4, w20", + "subs w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x4 (4)", "b.eq #-0x24" ] }, "repz scasq": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 25, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #3", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x30", "cbz x5, #+0x28", - "ldr x21, [x11]", - "eor w27, w4, w21", - "subs x26, x4, x21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", + "ldr x20, [x11]", + "eor w27, w4, w20", + "subs x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x8 (8)", + "b.eq #-0x24", + "b #+0x2c", + "cbz x5, #+0x28", + "ldr x20, [x11]", + "eor w27, w4, w20", + "subs x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x8 (8)", "b.eq #-0x24" ] }, "repnz scasb": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 29, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x38", "cbz x5, #+0x30", - "ldrb w21, [x11]", - "eor w27, w4, w21", + "ldrb w20, [x11]", + "eor w27, w4, w20", "lsl w0, w4, #24", - "cmp w0, w21, lsl #24", - "sub w26, w4, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", + "cmp w0, w20, lsl #24", + "sub w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "add x11, x11, #0x1 (1)", + "b.ne #-0x2c", + "b #+0x34", + "cbz x5, #+0x30", + "ldrb w20, [x11]", + "eor w27, w4, w20", + "lsl w0, w4, #24", + "cmp w0, w20, lsl #24", + "sub w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", + "sub x5, x5, #0x1 (1)", + "sub x11, x11, #0x1 (1)", "b.ne #-0x2c" ] }, "repnz scasw": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 29, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #1", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x38", "cbz x5, #+0x30", - "ldrh w21, [x11]", - "eor w27, w4, w21", + "ldrh w20, [x11]", + "eor w27, w4, w20", "lsl w0, w4, #16", - "cmp w0, w21, lsl #16", - "sub w26, w4, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", + "cmp w0, w20, lsl #16", + "sub w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x2 (2)", + "b.ne #-0x2c", + "b #+0x34", + "cbz x5, #+0x30", + "ldrh w20, [x11]", + "eor w27, w4, w20", + "lsl w0, w4, #16", + "cmp w0, w20, lsl #16", + "sub w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x2 (2)", "b.ne #-0x2c" ] }, "repnz scasd": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 25, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #2", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x30", "cbz x5, #+0x28", - "ldr w21, [x11]", - "eor w27, w4, w21", - "subs w26, w4, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", + "ldr w20, [x11]", + "eor w27, w4, w20", + "subs w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x4 (4)", + "b.ne #-0x24", + "b #+0x2c", + "cbz x5, #+0x28", + "ldr w20, [x11]", + "eor w27, w4, w20", + "subs w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x4 (4)", "b.ne #-0x24" ] }, "repnz scasq": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 25, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "lsl x20, x20, #3", + "lsr x20, x20, #63", + "cbz x20, #+0x8", + "b #+0x30", "cbz x5, #+0x28", - "ldr x21, [x11]", - "eor w27, w4, w21", - "subs x26, x4, x21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", + "ldr x20, [x11]", + "eor w27, w4, w20", + "subs x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", + "sub x5, x5, #0x1 (1)", + "add x11, x11, #0x8 (8)", + "b.ne #-0x24", + "b #+0x2c", + "cbz x5, #+0x28", + "ldr x20, [x11]", + "eor w27, w4, w20", + "subs x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "sub x5, x5, #0x1 (1)", - "add x11, x11, x20", + "sub x11, x11, #0x8 (8)", "b.ne #-0x24" ] },