From 90c1282f3a188d03ee7a43eb90f0430b58401af5 Mon Sep 17 00:00:00 2001 From: Billy Laws Date: Mon, 18 Nov 2024 22:31:50 +0000 Subject: [PATCH] Dispatcher: Support forcing a temp single instr block on ARM64EC JIT entry --- FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h | 3 +++ FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h index 2348d9cd6a..b38df6ed0d 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h +++ b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h @@ -76,6 +76,9 @@ constexpr size_t CPU_AREA_EMULATOR_STACK_BASE_OFFSET = 0x8; constexpr size_t CPU_AREA_EMULATOR_DATA_OFFSET = 0x30; #endif +// Will force one single instruction block to be generated first if set when entering the JIT filling SRA. +constexpr auto ENTRY_FILL_SRA_SINGLE_INST_REG = TMP1; + // Predicate register temporaries (used when AVX support is enabled) // PRED_TMP_16B indicates a predicate register that indicates the first 16 bytes set to 1. // PRED_TMP_32B indicates a predicate register that indicates the first 32 bytes set to 1. diff --git a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp index 4157d20a25..2e0d2bfb2a 100644 --- a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp +++ b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp @@ -93,6 +93,10 @@ void Dispatcher::EmitDispatcher() { ldr(STATE, EC_ENTRY_CPUAREA_REG, CPU_AREA_EMULATOR_DATA_OFFSET); FillStaticRegs(); + ldr(RipReg, STATE_PTR(CpuStateFrame, State.rip)); + // Force a single instruction block if ENTRY_FILL_SRA_SINGLE_INST_REG is nonzero entering the JIT, used for inline SMC handling. + cbnz(ARMEmitter::Size::i32Bit, ENTRY_FILL_SRA_SINGLE_INST_REG, &CompileSingleStep); + // Enter JIT b(&LoopTop);