From 640e911af4a0ca6a3e02d56ec0668e7b5275be4c Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sun, 28 Apr 2024 21:16:37 -0700 Subject: [PATCH] Adds unit tests for ADC/SBB garbage upper data bug Reproduces broken rendering in Final Fantasy 7 (SteamID 39140) --- unittests/ASM/FEX_bugs/add_sub_carry.asm | 29 ++++ unittests/ASM/FEX_bugs/add_sub_carry_2.asm | 167 +++++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 unittests/ASM/FEX_bugs/add_sub_carry.asm create mode 100644 unittests/ASM/FEX_bugs/add_sub_carry_2.asm diff --git a/unittests/ASM/FEX_bugs/add_sub_carry.asm b/unittests/ASM/FEX_bugs/add_sub_carry.asm new file mode 100644 index 0000000000..54205249b7 --- /dev/null +++ b/unittests/ASM/FEX_bugs/add_sub_carry.asm @@ -0,0 +1,29 @@ +%ifdef CONFIG +{ + "RegData": { + "RAX": "0xaeadacac9a9a41e5", + "RBX": "0x6162636520238df8" + } +} +%endif + +; FEX had a bug with smaller than 32-bit operations corrupting sbb and adc results. +; A small test that tests both sbb and adc to ensure it returns data correctly. +; This was noticed in Final Fantasy 7 (steamid 39140) having broken rendering on the title screen. +mov rax, 0x4142434445464748 +mov rbx, 0x5152535455565758 +mov rcx, 0x6162636465666768 + +clc +sbb al, bl +sbb ax, bx +sbb eax, ebx +sbb rax, rbx + +clc +adc bl, cl +adc bx, cx +adc ebx, ecx +adc rbx, rcx + +hlt diff --git a/unittests/ASM/FEX_bugs/add_sub_carry_2.asm b/unittests/ASM/FEX_bugs/add_sub_carry_2.asm new file mode 100644 index 0000000000..902ac7a820 --- /dev/null +++ b/unittests/ASM/FEX_bugs/add_sub_carry_2.asm @@ -0,0 +1,167 @@ +%ifdef CONFIG +{ + "RegData": { + "RAX": "0xedededee26260e6c", + "RBX": "0x121212129498c16d" + } +} +%endif + +; FEX had a bug with smaller than 32-bit operations corrupting sbb and adc results. +; A small test that tests both sbb and adc to ensure it returns data correctly. +; This was noticed in Final Fantasy 7 (steamid 39140) having broken rendering on the title screen. +mov rax, 0x4142434445464748 +mov rbx, 0x5152535455565758 +mov rcx, 0x6162636465666768 + +clc +sbb al, bl +sbb ax, bx +sbb eax, ebx +sbb rax, rbx + +%assign i 0 +%rep 256 +sbb al, [rel .data1 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +sbb ax, [rel .data2 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +sbb eax, [rel .data4 + i] +%assign i i+1 +%endrep + + +%assign i 0 +%rep 256 +sbb rax, [rel .data8 + i] +%assign i i+1 +%endrep + +stc +%assign i 0 +%rep 256 +sbb al, [rel .data1 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +sbb ax, [rel .data2 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +sbb eax, [rel .data4 + i] +%assign i i+1 +%endrep + + +%assign i 0 +%rep 256 +sbb rax, [rel .data8 + i] +%assign i i+1 +%endrep + + + + +clc +adc bl, cl +adc bx, cx +adc ebx, ecx +adc rbx, rcx + + +%assign i 0 +%rep 256 +adc bl, [rel .data1 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +adc bx, [rel .data2 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +adc ebx, [rel .data4 + i] +%assign i i+1 +%endrep + + +%assign i 0 +%rep 256 +adc rbx, [rel .data8 + i] +%assign i i+1 +%endrep + + +stc +%assign i 0 +%rep 256 +adc bl, [rel .data1 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +adc bx, [rel .data2 + i] +%assign i i+1 +%endrep + +%assign i 0 +%rep 256 +adc ebx, [rel .data4 + i] +%assign i i+1 +%endrep + + +%assign i 0 +%rep 256 +adc rbx, [rel .data8 + i] +%assign i i+1 +%endrep + + + + +hlt + +.data1: +%assign i 0 +%rep 256 +db i +%assign i i+1 +%endrep + +.data2: +%assign i 0 +%rep 256 +dw i +%assign i i+1 +%endrep + +.data4: +%assign i 0 +%rep 256 +dd i +%assign i i+1 +%endrep + +.data8: +%assign i 0 +%rep 256 +dq i +%assign i i+1 +%endrep