diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json
index 9936778c38..401146a808 100644
--- a/unittests/InstructionCountCI/Atomics.json
+++ b/unittests/InstructionCountCI/Atomics.json
@@ -69,139 +69,145 @@
       ]
     },
     "lock adc byte [rax], cl": {
-      "ExpectedInstructionCount": 21,
+      "ExpectedInstructionCount": 22,
       "Comment": "0x10",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "ldaddalb w20, w20, [x4]",
-        "eor w27, w20, w5",
-        "cset w21, hs",
-        "adc w22, w20, w5",
-        "uxtb w26, w22",
-        "cmp x26, x5",
-        "cset x22, lo",
-        "cmp x26, x5",
-        "cset x23, ls",
-        "cmp x21, #0x1 (1)",
-        "csel x21, x23, x22, eq",
+        "uxtb w20, w5",
+        "adc w21, wzr, w20",
+        "ldaddalb w21, w21, [x4]",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxtb w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "mrs x22, nzcv",
-        "orr w21, w22, w21, lsl #29",
-        "eor w22, w20, w5",
-        "eor w20, w26, w20",
-        "bic w20, w20, w22",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "bic w20, w21, w20",
         "ubfx x20, x20, #7, #1",
-        "orr w20, w21, w20, lsl #28",
+        "orr w20, w22, w20, lsl #28",
         "msr nzcv, x20"
       ]
     },
     "lock adc word [rax], cx": {
-      "ExpectedInstructionCount": 21,
+      "ExpectedInstructionCount": 22,
       "Comment": "0x11",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "ldaddalh w20, w20, [x4]",
-        "eor w27, w20, w5",
-        "cset w21, hs",
-        "adc w22, w20, w5",
-        "uxth w26, w22",
-        "cmp x26, x5",
-        "cset x22, lo",
-        "cmp x26, x5",
-        "cset x23, ls",
-        "cmp x21, #0x1 (1)",
-        "csel x21, x23, x22, eq",
+        "uxth w20, w5",
+        "adc w21, wzr, w20",
+        "ldaddalh w21, w21, [x4]",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxth w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "mrs x22, nzcv",
-        "orr w21, w22, w21, lsl #29",
-        "eor w22, w20, w5",
-        "eor w20, w26, w20",
-        "bic w20, w20, w22",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "bic w20, w21, w20",
         "ubfx x20, x20, #15, #1",
-        "orr w20, w21, w20, lsl #28",
+        "orr w20, w22, w20, lsl #28",
         "msr nzcv, x20"
       ]
     },
     "lock adc dword [rax], ecx": {
-      "ExpectedInstructionCount": 4,
+      "ExpectedInstructionCount": 5,
       "Comment": "0x11",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "ldaddal w20, w20, [x4]",
-        "eor w27, w20, w5",
-        "adcs w26, w20, w5"
+        "mov w20, w5",
+        "adc w21, wzr, w20",
+        "ldaddal w21, w21, [x4]",
+        "eor w27, w21, w20",
+        "adcs w26, w21, w20"
       ]
     },
     "lock sbb byte [rax], cl": {
-      "ExpectedInstructionCount": 23,
+      "ExpectedInstructionCount": 24,
       "Comment": "0x18",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "neg w1, w20",
-        "ldaddalb w1, w20, [x4]",
-        "eor w27, w20, w5",
-        "cset w21, hs",
-        "add w22, w5, w21",
-        "sub w22, w20, w22",
-        "uxtb w26, w22",
-        "cmp w26, w20",
-        "cset x22, hi",
-        "cmp w26, w20",
-        "cset x23, hs",
-        "cmp x21, #0x1 (1)",
-        "csel x21, x23, x22, eq",
+        "uxtb w20, w5",
+        "adc w21, wzr, w20",
+        "neg w1, w21",
+        "ldaddalb w1, w21, [x4]",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxtb w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "mrs x22, nzcv",
-        "orr w21, w22, w21, lsl #29",
-        "eor w22, w20, w5",
-        "eor w20, w26, w20",
-        "and w20, w20, w22",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "and w20, w21, w20",
         "ubfx x20, x20, #7, #1",
-        "orr w20, w21, w20, lsl #28",
+        "orr w20, w22, w20, lsl #28",
         "msr nzcv, x20"
       ]
     },
     "lock sbb word [rax], cx": {
-      "ExpectedInstructionCount": 23,
+      "ExpectedInstructionCount": 24,
       "Comment": "0x19",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "neg w1, w20",
-        "ldaddalh w1, w20, [x4]",
-        "eor w27, w20, w5",
-        "cset w21, hs",
-        "add w22, w5, w21",
-        "sub w22, w20, w22",
-        "uxth w26, w22",
-        "cmp w26, w20",
-        "cset x22, hi",
-        "cmp w26, w20",
-        "cset x23, hs",
-        "cmp x21, #0x1 (1)",
-        "csel x21, x23, x22, eq",
+        "uxth w20, w5",
+        "adc w21, wzr, w20",
+        "neg w1, w21",
+        "ldaddalh w1, w21, [x4]",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxth w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "mrs x22, nzcv",
-        "orr w21, w22, w21, lsl #29",
-        "eor w22, w20, w5",
-        "eor w20, w26, w20",
-        "and w20, w20, w22",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "and w20, w21, w20",
         "ubfx x20, x20, #15, #1",
-        "orr w20, w21, w20, lsl #28",
+        "orr w20, w22, w20, lsl #28",
         "msr nzcv, x20"
       ]
     },
     "lock sbb dword [rax], ecx": {
-      "ExpectedInstructionCount": 11,
+      "ExpectedInstructionCount": 12,
       "Comment": "0x19",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "neg w1, w20",
-        "ldaddal w1, w20, [x4]",
-        "eor w27, w20, w5",
-        "mrs x21, nzcv",
-        "eor w21, w21, #0x20000000",
-        "msr nzcv, x21",
-        "sbcs w26, w20, w5",
+        "mov w20, w5",
+        "adc w21, wzr, w20",
+        "neg w1, w21",
+        "ldaddal w1, w21, [x4]",
+        "eor w27, w21, w20",
+        "mrs x22, nzcv",
+        "eor w22, w22, #0x20000000",
+        "msr nzcv, x22",
+        "sbcs w26, w21, w20",
         "mrs x20, nzcv",
         "eor w20, w20, #0x20000000",
         "msr nzcv, x20"
diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json
index d535a3386d..5584c00652 100644
--- a/unittests/InstructionCountCI/FlagM/Atomics.json
+++ b/unittests/InstructionCountCI/FlagM/Atomics.json
@@ -70,125 +70,131 @@
       ]
     },
     "lock adc byte [rax], cl": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 19,
       "Comment": "0x10",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "ldaddalb w20, w20, [x4]",
-        "eor w27, w20, w5",
-        "cset w21, hs",
-        "adc w22, w20, w5",
-        "uxtb w26, w22",
-        "cmp x26, x5",
-        "cset x22, lo",
-        "cmp x26, x5",
-        "cset x23, ls",
-        "cmp x21, #0x1 (1)",
-        "csel x21, x23, x22, eq",
+        "uxtb w20, w5",
+        "adc w21, wzr, w20",
+        "ldaddalb w21, w21, [x4]",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxtb w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "rmif x21, #63, #nzCv",
-        "eor w21, w20, w5",
-        "eor w20, w26, w20",
-        "bic w20, w20, w21",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "bic w20, w21, w20",
         "rmif x20, #7, #nzcV"
       ]
     },
     "lock adc word [rax], cx": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 19,
       "Comment": "0x11",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "ldaddalh w20, w20, [x4]",
-        "eor w27, w20, w5",
-        "cset w21, hs",
-        "adc w22, w20, w5",
-        "uxth w26, w22",
-        "cmp x26, x5",
-        "cset x22, lo",
-        "cmp x26, x5",
-        "cset x23, ls",
-        "cmp x21, #0x1 (1)",
-        "csel x21, x23, x22, eq",
+        "uxth w20, w5",
+        "adc w21, wzr, w20",
+        "ldaddalh w21, w21, [x4]",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxth w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "rmif x21, #63, #nzCv",
-        "eor w21, w20, w5",
-        "eor w20, w26, w20",
-        "bic w20, w20, w21",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "bic w20, w21, w20",
         "rmif x20, #15, #nzcV"
       ]
     },
     "lock adc dword [rax], ecx": {
-      "ExpectedInstructionCount": 4,
+      "ExpectedInstructionCount": 5,
       "Comment": "0x11",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "ldaddal w20, w20, [x4]",
-        "eor w27, w20, w5",
-        "adcs w26, w20, w5"
+        "mov w20, w5",
+        "adc w21, wzr, w20",
+        "ldaddal w21, w21, [x4]",
+        "eor w27, w21, w20",
+        "adcs w26, w21, w20"
       ]
     },
     "lock sbb byte [rax], cl": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 21,
       "Comment": "0x18",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "neg w1, w20",
-        "ldaddalb w1, w20, [x4]",
-        "eor w27, w20, w5",
-        "cset w21, hs",
-        "add w22, w5, w21",
-        "sub w22, w20, w22",
-        "uxtb w26, w22",
-        "cmp w26, w20",
-        "cset x22, hi",
-        "cmp w26, w20",
-        "cset x23, hs",
-        "cmp x21, #0x1 (1)",
-        "csel x21, x23, x22, eq",
+        "uxtb w20, w5",
+        "adc w21, wzr, w20",
+        "neg w1, w21",
+        "ldaddalb w1, w21, [x4]",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxtb w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "rmif x21, #63, #nzCv",
-        "eor w21, w20, w5",
-        "eor w20, w26, w20",
-        "and w20, w20, w21",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "and w20, w21, w20",
         "rmif x20, #7, #nzcV"
       ]
     },
     "lock sbb word [rax], cx": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 21,
       "Comment": "0x19",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "neg w1, w20",
-        "ldaddalh w1, w20, [x4]",
-        "eor w27, w20, w5",
-        "cset w21, hs",
-        "add w22, w5, w21",
-        "sub w22, w20, w22",
-        "uxth w26, w22",
-        "cmp w26, w20",
-        "cset x22, hi",
-        "cmp w26, w20",
-        "cset x23, hs",
-        "cmp x21, #0x1 (1)",
-        "csel x21, x23, x22, eq",
+        "uxth w20, w5",
+        "adc w21, wzr, w20",
+        "neg w1, w21",
+        "ldaddalh w1, w21, [x4]",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxth w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "rmif x21, #63, #nzCv",
-        "eor w21, w20, w5",
-        "eor w20, w26, w20",
-        "and w20, w20, w21",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "and w20, w21, w20",
         "rmif x20, #15, #nzcV"
       ]
     },
     "lock sbb dword [rax], ecx": {
-      "ExpectedInstructionCount": 7,
+      "ExpectedInstructionCount": 8,
       "Comment": "0x19",
       "ExpectedArm64ASM": [
-        "adc w20, wzr, w5",
-        "neg w1, w20",
-        "ldaddal w1, w20, [x4]",
-        "eor w27, w20, w5",
+        "mov w20, w5",
+        "adc w21, wzr, w20",
+        "neg w1, w21",
+        "ldaddal w1, w21, [x4]",
+        "eor w27, w21, w20",
         "cfinv",
-        "sbcs w26, w20, w5",
+        "sbcs w26, w21, w20",
         "cfinv"
       ]
     },
diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json
index b34877fcb8..a8e7537b6f 100644
--- a/unittests/InstructionCountCI/FlagM/Primary.json
+++ b/unittests/InstructionCountCI/FlagM/Primary.json
@@ -359,57 +359,63 @@
       ]
     },
     "adc bl, cl": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 19,
       "Comment": "0x10",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
-        "cset w20, hs",
-        "adc w21, w7, w5",
-        "uxtb w26, w21",
-        "cmp x26, x5",
-        "cset x21, lo",
-        "cmp x26, x5",
-        "cset x22, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxtb w20, w5",
+        "uxtb w21, w7",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxtb w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "rmif x20, #63, #nzCv",
-        "eor w20, w7, w5",
-        "eor w21, w26, w7",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
         "bic w20, w21, w20",
         "rmif x20, #7, #nzcV",
         "bfxil x7, x26, #0, #8"
       ]
     },
     "adc bx, cx": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 19,
       "Comment": "0x11",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
-        "cset w20, hs",
-        "adc w21, w7, w5",
-        "uxth w26, w21",
-        "cmp x26, x5",
-        "cset x21, lo",
-        "cmp x26, x5",
-        "cset x22, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxth w20, w5",
+        "uxth w21, w7",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxth w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "rmif x20, #63, #nzCv",
-        "eor w20, w7, w5",
-        "eor w21, w26, w7",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
         "bic w20, w21, w20",
         "rmif x20, #15, #nzcV",
         "bfxil x7, x26, #0, #16"
       ]
     },
     "adc ebx, ecx": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 5,
       "Comment": "0x11",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
-        "adcs w26, w7, w5",
+        "mov w20, w5",
+        "mov w21, w7",
+        "eor w27, w21, w20",
+        "adcs w26, w21, w20",
         "mov x7, x26"
       ]
     },
@@ -423,66 +429,72 @@
       ]
     },
     "db 0x12, 0xcb": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 19,
       "Comment": [
         "0x12",
         "adc bl, cl but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
-        "cset w20, hs",
-        "adc w21, w5, w7",
-        "uxtb w26, w21",
-        "cmp x26, x7",
-        "cset x21, lo",
-        "cmp x26, x7",
-        "cset x22, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxtb w20, w7",
+        "uxtb w21, w5",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxtb w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "rmif x20, #63, #nzCv",
-        "eor w20, w5, w7",
-        "eor w21, w26, w5",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
         "bic w20, w21, w20",
         "rmif x20, #7, #nzcV",
         "bfxil x5, x26, #0, #8"
       ]
     },
     "db 0x66, 0x13, 0xcb": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 19,
       "Comment": [
         "0x13",
         "adc bx, cx but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
-        "cset w20, hs",
-        "adc w21, w5, w7",
-        "uxth w26, w21",
-        "cmp x26, x7",
-        "cset x21, lo",
-        "cmp x26, x7",
-        "cset x22, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxth w20, w7",
+        "uxth w21, w5",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxth w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "rmif x20, #63, #nzCv",
-        "eor w20, w5, w7",
-        "eor w21, w26, w5",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
         "bic w20, w21, w20",
         "rmif x20, #15, #nzcV",
         "bfxil x5, x26, #0, #16"
       ]
     },
     "db 0x13, 0xcb": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 5,
       "Comment": [
         "0x13",
         "adc ebx, ecx but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
-        "adcs w26, w5, w7",
+        "mov w20, w7",
+        "mov w21, w5",
+        "eor w27, w21, w20",
+        "adcs w26, w21, w20",
         "mov x5, x26"
       ]
     },
@@ -499,11 +511,11 @@
       ]
     },
     "adc al, 1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 16,
       "Comment": "0x14",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxtb w27, w4",
         "cset w21, hs",
         "adc w20, w27, w20",
         "uxtb w26, w20",
@@ -517,16 +529,15 @@
         "rmif x20, #63, #nzCv",
         "bic w20, w26, w27",
         "rmif x20, #7, #nzcV",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #8"
       ]
     },
     "adc ax, 1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 16,
       "Comment": "0x15",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxth w27, w4",
         "cset w21, hs",
         "adc w20, w27, w20",
         "uxth w26, w20",
@@ -540,7 +551,6 @@
         "rmif x20, #63, #nzCv",
         "bic w20, w26, w27",
         "rmif x20, #15, #nzcV",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #16"
       ]
     },
@@ -549,7 +559,7 @@
       "Comment": "0x15",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "mov w27, w4",
         "adcs w26, w27, w20",
         "mov x4, x26"
       ]
@@ -565,56 +575,59 @@
       ]
     },
     "adc al, -1": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 17,
       "Comment": "0x14",
       "ExpectedArm64ASM": [
         "mov w20, #0xff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "adc w20, w4, w20",
+        "uxtb w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "adc w20, w21, w20",
         "uxtb w26, w20",
         "cmp w26, #0xff (255)",
         "cset x20, lo",
         "cmp w26, #0xff (255)",
-        "cset x22, ls",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x22, x20, eq",
+        "cset x23, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x23, x20, eq",
         "cmn wzr, w26, lsl #24",
         "rmif x20, #63, #nzCv",
-        "bic w20, w4, w26",
+        "bic w20, w21, w26",
         "rmif x20, #7, #nzcV",
         "bfxil x4, x26, #0, #8"
       ]
     },
     "adc ax, -1": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 17,
       "Comment": "0x15",
       "ExpectedArm64ASM": [
         "mov w20, #0xffff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "adc w22, w4, w20",
-        "uxth w26, w22",
+        "uxth w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxth w26, w23",
         "cmp w26, w20",
-        "cset x22, lo",
+        "cset x23, lo",
         "cmp w26, w20",
         "cset x20, ls",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x20, x22, eq",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x20, x23, eq",
         "cmn wzr, w26, lsl #16",
         "rmif x20, #63, #nzCv",
-        "bic w20, w4, w26",
+        "bic w20, w21, w26",
         "rmif x20, #15, #nzcV",
         "bfxil x4, x26, #0, #16"
       ]
     },
     "adc eax, -1": {
-      "ExpectedInstructionCount": 4,
+      "ExpectedInstructionCount": 5,
       "Comment": "0x15",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffffff",
-        "mvn w27, w4",
-        "adcs w26, w4, w20",
+        "mov w21, w4",
+        "mvn w27, w21",
+        "adcs w26, w21, w20",
         "mov x4, x26"
       ]
     },
@@ -629,60 +642,66 @@
       ]
     },
     "sbb bl, cl": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 20,
       "Comment": "0x18",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
-        "cset w20, hs",
-        "add w21, w5, w20",
-        "sub w21, w7, w21",
-        "uxtb w26, w21",
-        "cmp x26, x7",
-        "cset x21, hi",
-        "cmp x26, x7",
-        "cset x22, hs",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxtb w20, w5",
+        "uxtb w21, w7",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxtb w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "rmif x20, #63, #nzCv",
-        "eor w20, w7, w5",
-        "eor w21, w26, w7",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
         "and w20, w21, w20",
         "rmif x20, #7, #nzcV",
         "bfxil x7, x26, #0, #8"
       ]
     },
     "sbb bx, cx": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 20,
       "Comment": "0x19",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
-        "cset w20, hs",
-        "add w21, w5, w20",
-        "sub w21, w7, w21",
-        "uxth w26, w21",
-        "cmp x26, x7",
-        "cset x21, hi",
-        "cmp x26, x7",
-        "cset x22, hs",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxth w20, w5",
+        "uxth w21, w7",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxth w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "rmif x20, #63, #nzCv",
-        "eor w20, w7, w5",
-        "eor w21, w26, w7",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
         "and w20, w21, w20",
         "rmif x20, #15, #nzcV",
         "bfxil x7, x26, #0, #16"
       ]
     },
     "sbb ebx, ecx": {
-      "ExpectedInstructionCount": 5,
+      "ExpectedInstructionCount": 7,
       "Comment": "0x19",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
+        "mov w20, w5",
+        "mov w21, w7",
+        "eor w27, w21, w20",
         "cfinv",
-        "sbcs w26, w7, w5",
+        "sbcs w26, w21, w20",
         "cfinv",
         "mov x7, x26"
       ]
@@ -699,69 +718,75 @@
       ]
     },
     "db 0x1A, 0xcb": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 20,
       "Comment": [
         "0x1A",
         "sbb bl, cl but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
-        "cset w20, hs",
-        "add w21, w7, w20",
-        "sub w21, w5, w21",
-        "uxtb w26, w21",
-        "cmp x26, x5",
-        "cset x21, hi",
-        "cmp x26, x5",
-        "cset x22, hs",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxtb w20, w7",
+        "uxtb w21, w5",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxtb w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "rmif x20, #63, #nzCv",
-        "eor w20, w5, w7",
-        "eor w21, w26, w5",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
         "and w20, w21, w20",
         "rmif x20, #7, #nzcV",
         "bfxil x5, x26, #0, #8"
       ]
     },
     "db 0x66, 0x1B, 0xcb": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 20,
       "Comment": [
         "0x1B",
         "sbb bx, cx but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
-        "cset w20, hs",
-        "add w21, w7, w20",
-        "sub w21, w5, w21",
-        "uxth w26, w21",
-        "cmp x26, x5",
-        "cset x21, hi",
-        "cmp x26, x5",
-        "cset x22, hs",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxth w20, w7",
+        "uxth w21, w5",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxth w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "rmif x20, #63, #nzCv",
-        "eor w20, w5, w7",
-        "eor w21, w26, w5",
+        "rmif x22, #63, #nzCv",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
         "and w20, w21, w20",
         "rmif x20, #15, #nzcV",
         "bfxil x5, x26, #0, #16"
       ]
     },
     "db 0x1B, 0xcb": {
-      "ExpectedInstructionCount": 5,
+      "ExpectedInstructionCount": 7,
       "Comment": [
         "0x1B",
         "sbb ebx, ecx but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
+        "mov w20, w7",
+        "mov w21, w5",
+        "eor w27, w21, w20",
         "cfinv",
-        "sbcs w26, w5, w7",
+        "sbcs w26, w21, w20",
         "cfinv",
         "mov x5, x26"
       ]
@@ -781,18 +806,18 @@
       ]
     },
     "sbb al, 1": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 17,
       "Comment": "0x1C",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxtb w27, w4",
         "cset w21, hs",
         "add w20, w20, w21",
         "sub w20, w27, w20",
         "uxtb w26, w20",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x20, hi",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x22, hs",
         "cmp x21, #0x1 (1)",
         "csel x20, x22, x20, eq",
@@ -800,23 +825,22 @@
         "rmif x20, #63, #nzCv",
         "bic w20, w27, w26",
         "rmif x20, #7, #nzcV",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #8"
       ]
     },
     "sbb ax, 1": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 17,
       "Comment": "0x1D",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxth w27, w4",
         "cset w21, hs",
         "add w20, w20, w21",
         "sub w20, w27, w20",
         "uxth w26, w20",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x20, hi",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x22, hs",
         "cmp x21, #0x1 (1)",
         "csel x20, x22, x20, eq",
@@ -824,7 +848,6 @@
         "rmif x20, #63, #nzCv",
         "bic w20, w27, w26",
         "rmif x20, #15, #nzcV",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #16"
       ]
     },
@@ -833,7 +856,7 @@
       "Comment": "0x1D",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "mov w27, w4",
         "cfinv",
         "sbcs w26, w27, w20",
         "cfinv",
@@ -853,59 +876,62 @@
       ]
     },
     "sbb al, -1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 18,
       "Comment": "0x1C",
       "ExpectedArm64ASM": [
         "mov w20, #0xff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "add w20, w20, w21",
-        "sub w20, w4, w20",
+        "uxtb w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "add w20, w20, w22",
+        "sub w20, w21, w20",
         "uxtb w26, w20",
-        "cmp x26, x4",
+        "cmp w26, w21",
         "cset x20, hi",
-        "cmp x26, x4",
-        "cset x22, hs",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x22, x20, eq",
+        "cmp w26, w21",
+        "cset x23, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x23, x20, eq",
         "cmn wzr, w26, lsl #24",
         "rmif x20, #63, #nzCv",
-        "bic w20, w26, w4",
+        "bic w20, w26, w21",
         "rmif x20, #7, #nzcV",
         "bfxil x4, x26, #0, #8"
       ]
     },
     "sbb ax, -1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 18,
       "Comment": "0x1D",
       "ExpectedArm64ASM": [
         "mov w20, #0xffff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "add w20, w20, w21",
-        "sub w20, w4, w20",
+        "uxth w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "add w20, w20, w22",
+        "sub w20, w21, w20",
         "uxth w26, w20",
-        "cmp x26, x4",
+        "cmp w26, w21",
         "cset x20, hi",
-        "cmp x26, x4",
-        "cset x22, hs",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x22, x20, eq",
+        "cmp w26, w21",
+        "cset x23, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x23, x20, eq",
         "cmn wzr, w26, lsl #16",
         "rmif x20, #63, #nzCv",
-        "bic w20, w26, w4",
+        "bic w20, w26, w21",
         "rmif x20, #15, #nzcV",
         "bfxil x4, x26, #0, #16"
       ]
     },
     "sbb eax, -1": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 7,
       "Comment": "0x1D",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffffff",
-        "mvn w27, w4",
+        "mov w21, w4",
+        "mvn w27, w21",
         "cfinv",
-        "sbcs w26, w4, w20",
+        "sbcs w26, w21, w20",
         "cfinv",
         "mov x4, x26"
       ]
diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
index 6c1b652617..3594966638 100644
--- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
@@ -34,11 +34,11 @@
       ]
     },
     "adc al, 1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 16,
       "Comment": "GROUP1 0x80 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxtb w27, w4",
         "cset w21, hs",
         "adc w20, w27, w20",
         "uxtb w26, w20",
@@ -52,23 +52,22 @@
         "rmif x20, #63, #nzCv",
         "bic w20, w26, w27",
         "rmif x20, #7, #nzcV",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #8"
       ]
     },
     "sbb al, 1": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 17,
       "Comment": "GROUP1 0x80 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxtb w27, w4",
         "cset w21, hs",
         "add w20, w20, w21",
         "sub w20, w27, w20",
         "uxtb w26, w20",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x20, hi",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x22, hs",
         "cmp x21, #0x1 (1)",
         "csel x20, x22, x20, eq",
@@ -76,7 +75,6 @@
         "rmif x20, #63, #nzCv",
         "bic w20, w27, w26",
         "rmif x20, #7, #nzcV",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #8"
       ]
     },
@@ -146,46 +144,48 @@
       ]
     },
     "adc al, -1": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 17,
       "Comment": "GROUP1 0x80 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0xff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "adc w20, w4, w20",
+        "uxtb w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "adc w20, w21, w20",
         "uxtb w26, w20",
         "cmp w26, #0xff (255)",
         "cset x20, lo",
         "cmp w26, #0xff (255)",
-        "cset x22, ls",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x22, x20, eq",
+        "cset x23, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x23, x20, eq",
         "cmn wzr, w26, lsl #24",
         "rmif x20, #63, #nzCv",
-        "bic w20, w4, w26",
+        "bic w20, w21, w26",
         "rmif x20, #7, #nzcV",
         "bfxil x4, x26, #0, #8"
       ]
     },
     "sbb al, -1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 18,
       "Comment": "GROUP1 0x80 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0xff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "add w20, w20, w21",
-        "sub w20, w4, w20",
+        "uxtb w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "add w20, w20, w22",
+        "sub w20, w21, w20",
         "uxtb w26, w20",
-        "cmp x26, x4",
+        "cmp w26, w21",
         "cset x20, hi",
-        "cmp x26, x4",
-        "cset x22, hs",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x22, x20, eq",
+        "cmp w26, w21",
+        "cset x23, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x23, x20, eq",
         "cmn wzr, w26, lsl #24",
         "rmif x20, #63, #nzCv",
-        "bic w20, w26, w4",
+        "bic w20, w26, w21",
         "rmif x20, #7, #nzcV",
         "bfxil x4, x26, #0, #8"
       ]
@@ -287,7 +287,7 @@
       "Comment": "GROUP1 0x81 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0x100",
-        "mov x27, x4",
+        "mov w27, w4",
         "adcs w26, w27, w20",
         "mov x4, x26"
       ]
@@ -307,7 +307,7 @@
       "Comment": "GROUP1 0x81 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0x100",
-        "mov x27, x4",
+        "mov w27, w4",
         "cfinv",
         "sbcs w26, w27, w20",
         "cfinv",
@@ -453,7 +453,7 @@
       "Comment": "GROUP1 0x81 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffff00",
-        "mov x27, x4",
+        "mov w27, w4",
         "adcs w26, w27, w20",
         "mov x4, x26"
       ]
@@ -473,7 +473,7 @@
       "Comment": "GROUP1 0x81 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffff00",
-        "mov x27, x4",
+        "mov w27, w4",
         "cfinv",
         "sbcs w26, w27, w20",
         "cfinv",
@@ -620,7 +620,7 @@
       "Comment": "GROUP1 0x83 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "mov w27, w4",
         "adcs w26, w27, w20",
         "mov x4, x26"
       ]
@@ -640,7 +640,7 @@
       "Comment": "GROUP1 0x83 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "mov w27, w4",
         "cfinv",
         "sbcs w26, w27, w20",
         "cfinv",
@@ -783,12 +783,13 @@
       ]
     },
     "adc eax, -1": {
-      "ExpectedInstructionCount": 4,
+      "ExpectedInstructionCount": 5,
       "Comment": "GROUP1 0x83 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffffff",
-        "mvn w27, w4",
-        "adcs w26, w4, w20",
+        "mov w21, w4",
+        "mvn w27, w21",
+        "adcs w26, w21, w20",
         "mov x4, x26"
       ]
     },
@@ -803,13 +804,14 @@
       ]
     },
     "sbb eax, -1": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 7,
       "Comment": "GROUP1 0x83 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffffff",
-        "mvn w27, w4",
+        "mov w21, w4",
+        "mvn w27, w21",
         "cfinv",
-        "sbcs w26, w4, w20",
+        "sbcs w26, w21, w20",
         "cfinv",
         "mov x4, x26"
       ]
diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json
index 5fcaf32e0c..fe8eb6ccd7 100644
--- a/unittests/InstructionCountCI/Primary.json
+++ b/unittests/InstructionCountCI/Primary.json
@@ -358,63 +358,69 @@
       ]
     },
     "adc bl, cl": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 22,
       "Comment": "0x10",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
-        "cset w20, hs",
-        "adc w21, w7, w5",
-        "uxtb w26, w21",
-        "cmp x26, x5",
-        "cset x21, lo",
-        "cmp x26, x5",
-        "cset x22, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxtb w20, w5",
+        "uxtb w21, w7",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxtb w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "eor w21, w7, w5",
-        "eor w22, w26, w7",
-        "bic w21, w22, w21",
-        "ubfx x21, x21, #7, #1",
-        "orr w20, w20, w21, lsl #28",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "bic w20, w21, w20",
+        "ubfx x20, x20, #7, #1",
+        "orr w20, w22, w20, lsl #28",
         "bfxil x7, x26, #0, #8",
         "msr nzcv, x20"
       ]
     },
     "adc bx, cx": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 22,
       "Comment": "0x11",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
-        "cset w20, hs",
-        "adc w21, w7, w5",
-        "uxth w26, w21",
-        "cmp x26, x5",
-        "cset x21, lo",
-        "cmp x26, x5",
-        "cset x22, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxth w20, w5",
+        "uxth w21, w7",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxth w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "eor w21, w7, w5",
-        "eor w22, w26, w7",
-        "bic w21, w22, w21",
-        "ubfx x21, x21, #15, #1",
-        "orr w20, w20, w21, lsl #28",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "bic w20, w21, w20",
+        "ubfx x20, x20, #15, #1",
+        "orr w20, w22, w20, lsl #28",
         "bfxil x7, x26, #0, #16",
         "msr nzcv, x20"
       ]
     },
     "adc ebx, ecx": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 5,
       "Comment": "0x11",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
-        "adcs w26, w7, w5",
+        "mov w20, w5",
+        "mov w21, w7",
+        "eor w27, w21, w20",
+        "adcs w26, w21, w20",
         "mov x7, x26"
       ]
     },
@@ -428,72 +434,78 @@
       ]
     },
     "db 0x12, 0xcb": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 22,
       "Comment": [
         "0x12",
         "adc bl, cl but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
-        "cset w20, hs",
-        "adc w21, w5, w7",
-        "uxtb w26, w21",
-        "cmp x26, x7",
-        "cset x21, lo",
-        "cmp x26, x7",
-        "cset x22, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxtb w20, w7",
+        "uxtb w21, w5",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxtb w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "eor w21, w5, w7",
-        "eor w22, w26, w5",
-        "bic w21, w22, w21",
-        "ubfx x21, x21, #7, #1",
-        "orr w20, w20, w21, lsl #28",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "bic w20, w21, w20",
+        "ubfx x20, x20, #7, #1",
+        "orr w20, w22, w20, lsl #28",
         "bfxil x5, x26, #0, #8",
         "msr nzcv, x20"
       ]
     },
     "db 0x66, 0x13, 0xcb": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 22,
       "Comment": [
         "0x13",
         "adc bx, cx but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
-        "cset w20, hs",
-        "adc w21, w5, w7",
-        "uxth w26, w21",
-        "cmp x26, x7",
-        "cset x21, lo",
-        "cmp x26, x7",
-        "cset x22, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxth w20, w7",
+        "uxth w21, w5",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxth w26, w23",
+        "cmp w26, w20",
+        "cset x23, lo",
+        "cmp w26, w20",
+        "cset x24, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "eor w21, w5, w7",
-        "eor w22, w26, w5",
-        "bic w21, w22, w21",
-        "ubfx x21, x21, #15, #1",
-        "orr w20, w20, w21, lsl #28",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "bic w20, w21, w20",
+        "ubfx x20, x20, #15, #1",
+        "orr w20, w22, w20, lsl #28",
         "bfxil x5, x26, #0, #16",
         "msr nzcv, x20"
       ]
     },
     "db 0x13, 0xcb": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 5,
       "Comment": [
         "0x13",
         "adc ebx, ecx but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
-        "adcs w26, w5, w7",
+        "mov w20, w7",
+        "mov w21, w5",
+        "eor w27, w21, w20",
+        "adcs w26, w21, w20",
         "mov x5, x26"
       ]
     },
@@ -510,11 +522,11 @@
       ]
     },
     "adc al, 1": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 19,
       "Comment": "0x14",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxtb w27, w4",
         "cset w21, hs",
         "adc w20, w27, w20",
         "uxtb w26, w20",
@@ -530,17 +542,16 @@
         "bic w21, w26, w27",
         "ubfx x21, x21, #7, #1",
         "orr w20, w20, w21, lsl #28",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #8",
         "msr nzcv, x20"
       ]
     },
     "adc ax, 1": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 19,
       "Comment": "0x15",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxth w27, w4",
         "cset w21, hs",
         "adc w20, w27, w20",
         "uxth w26, w20",
@@ -556,7 +567,6 @@
         "bic w21, w26, w27",
         "ubfx x21, x21, #15, #1",
         "orr w20, w20, w21, lsl #28",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #16",
         "msr nzcv, x20"
       ]
@@ -566,7 +576,7 @@
       "Comment": "0x15",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "mov w27, w4",
         "adcs w26, w27, w20",
         "mov x4, x26"
       ]
@@ -582,24 +592,25 @@
       ]
     },
     "adc al, -1": {
-      "ExpectedInstructionCount": 19,
+      "ExpectedInstructionCount": 20,
       "Comment": "0x14",
       "ExpectedArm64ASM": [
         "mov w20, #0xff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "adc w20, w4, w20",
+        "uxtb w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "adc w20, w21, w20",
         "uxtb w26, w20",
         "cmp w26, #0xff (255)",
         "cset x20, lo",
         "cmp w26, #0xff (255)",
-        "cset x22, ls",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x22, x20, eq",
+        "cset x23, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x23, x20, eq",
         "cmn wzr, w26, lsl #24",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "bic w21, w4, w26",
+        "mrs x22, nzcv",
+        "orr w20, w22, w20, lsl #29",
+        "bic w21, w21, w26",
         "ubfx x21, x21, #7, #1",
         "orr w20, w20, w21, lsl #28",
         "bfxil x4, x26, #0, #8",
@@ -607,24 +618,25 @@
       ]
     },
     "adc ax, -1": {
-      "ExpectedInstructionCount": 19,
+      "ExpectedInstructionCount": 20,
       "Comment": "0x15",
       "ExpectedArm64ASM": [
         "mov w20, #0xffff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "adc w22, w4, w20",
-        "uxth w26, w22",
+        "uxth w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "adc w23, w21, w20",
+        "uxth w26, w23",
         "cmp w26, w20",
-        "cset x22, lo",
+        "cset x23, lo",
         "cmp w26, w20",
         "cset x20, ls",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x20, x22, eq",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x20, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "bic w21, w4, w26",
+        "mrs x22, nzcv",
+        "orr w20, w22, w20, lsl #29",
+        "bic w21, w21, w26",
         "ubfx x21, x21, #15, #1",
         "orr w20, w20, w21, lsl #28",
         "bfxil x4, x26, #0, #16",
@@ -632,12 +644,13 @@
       ]
     },
     "adc eax, -1": {
-      "ExpectedInstructionCount": 4,
+      "ExpectedInstructionCount": 5,
       "Comment": "0x15",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffffff",
-        "mvn w27, w4",
-        "adcs w26, w4, w20",
+        "mov w21, w4",
+        "mvn w27, w21",
+        "adcs w26, w21, w20",
         "mov x4, x26"
       ]
     },
@@ -652,68 +665,74 @@
       ]
     },
     "sbb bl, cl": {
-      "ExpectedInstructionCount": 21,
+      "ExpectedInstructionCount": 23,
       "Comment": "0x18",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
-        "cset w20, hs",
-        "add w21, w5, w20",
-        "sub w21, w7, w21",
-        "uxtb w26, w21",
-        "cmp x26, x7",
-        "cset x21, hi",
-        "cmp x26, x7",
-        "cset x22, hs",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxtb w20, w5",
+        "uxtb w21, w7",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxtb w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "eor w21, w7, w5",
-        "eor w22, w26, w7",
-        "and w21, w22, w21",
-        "ubfx x21, x21, #7, #1",
-        "orr w20, w20, w21, lsl #28",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "and w20, w21, w20",
+        "ubfx x20, x20, #7, #1",
+        "orr w20, w22, w20, lsl #28",
         "bfxil x7, x26, #0, #8",
         "msr nzcv, x20"
       ]
     },
     "sbb bx, cx": {
-      "ExpectedInstructionCount": 21,
+      "ExpectedInstructionCount": 23,
       "Comment": "0x19",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
-        "cset w20, hs",
-        "add w21, w5, w20",
-        "sub w21, w7, w21",
-        "uxth w26, w21",
-        "cmp x26, x7",
-        "cset x21, hi",
-        "cmp x26, x7",
-        "cset x22, hs",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxth w20, w5",
+        "uxth w21, w7",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxth w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "eor w21, w7, w5",
-        "eor w22, w26, w7",
-        "and w21, w22, w21",
-        "ubfx x21, x21, #15, #1",
-        "orr w20, w20, w21, lsl #28",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "and w20, w21, w20",
+        "ubfx x20, x20, #15, #1",
+        "orr w20, w22, w20, lsl #28",
         "bfxil x7, x26, #0, #16",
         "msr nzcv, x20"
       ]
     },
     "sbb ebx, ecx": {
-      "ExpectedInstructionCount": 9,
+      "ExpectedInstructionCount": 11,
       "Comment": "0x19",
       "ExpectedArm64ASM": [
-        "eor w27, w7, w5",
-        "mrs x20, nzcv",
-        "eor w20, w20, #0x20000000",
-        "msr nzcv, x20",
-        "sbcs w26, w7, w5",
+        "mov w20, w5",
+        "mov w21, w7",
+        "eor w27, w21, w20",
+        "mrs x22, nzcv",
+        "eor w22, w22, #0x20000000",
+        "msr nzcv, x22",
+        "sbcs w26, w21, w20",
         "mrs x20, nzcv",
         "eor w20, w20, #0x20000000",
         "mov x7, x26",
@@ -736,77 +755,83 @@
       ]
     },
     "db 0x1A, 0xcb": {
-      "ExpectedInstructionCount": 21,
+      "ExpectedInstructionCount": 23,
       "Comment": [
         "0x1A",
         "sbb bl, cl but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
-        "cset w20, hs",
-        "add w21, w7, w20",
-        "sub w21, w5, w21",
-        "uxtb w26, w21",
-        "cmp x26, x5",
-        "cset x21, hi",
-        "cmp x26, x5",
-        "cset x22, hs",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxtb w20, w7",
+        "uxtb w21, w5",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxtb w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #24",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "eor w21, w5, w7",
-        "eor w22, w26, w5",
-        "and w21, w22, w21",
-        "ubfx x21, x21, #7, #1",
-        "orr w20, w20, w21, lsl #28",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "and w20, w21, w20",
+        "ubfx x20, x20, #7, #1",
+        "orr w20, w22, w20, lsl #28",
         "bfxil x5, x26, #0, #8",
         "msr nzcv, x20"
       ]
     },
     "db 0x66, 0x1B, 0xcb": {
-      "ExpectedInstructionCount": 21,
+      "ExpectedInstructionCount": 23,
       "Comment": [
         "0x1B",
         "sbb bx, cx but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
-        "cset w20, hs",
-        "add w21, w7, w20",
-        "sub w21, w5, w21",
-        "uxth w26, w21",
-        "cmp x26, x5",
-        "cset x21, hi",
-        "cmp x26, x5",
-        "cset x22, hs",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x22, x21, eq",
+        "uxth w20, w7",
+        "uxth w21, w5",
+        "eor w27, w21, w20",
+        "cset w22, hs",
+        "add w23, w20, w22",
+        "sub w23, w21, w23",
+        "uxth w26, w23",
+        "cmp w26, w21",
+        "cset x23, hi",
+        "cmp w26, w21",
+        "cset x24, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x22, x24, x23, eq",
         "cmn wzr, w26, lsl #16",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "eor w21, w5, w7",
-        "eor w22, w26, w5",
-        "and w21, w22, w21",
-        "ubfx x21, x21, #15, #1",
-        "orr w20, w20, w21, lsl #28",
+        "mrs x23, nzcv",
+        "orr w22, w23, w22, lsl #29",
+        "eor w20, w21, w20",
+        "eor w21, w26, w21",
+        "and w20, w21, w20",
+        "ubfx x20, x20, #15, #1",
+        "orr w20, w22, w20, lsl #28",
         "bfxil x5, x26, #0, #16",
         "msr nzcv, x20"
       ]
     },
     "db 0x1B, 0xcb": {
-      "ExpectedInstructionCount": 9,
+      "ExpectedInstructionCount": 11,
       "Comment": [
         "0x1B",
         "sbb ebx, ecx but modrm.rm as source"
       ],
       "ExpectedArm64ASM": [
-        "eor w27, w5, w7",
-        "mrs x20, nzcv",
-        "eor w20, w20, #0x20000000",
-        "msr nzcv, x20",
-        "sbcs w26, w5, w7",
+        "mov w20, w7",
+        "mov w21, w5",
+        "eor w27, w21, w20",
+        "mrs x22, nzcv",
+        "eor w22, w22, #0x20000000",
+        "msr nzcv, x22",
+        "sbcs w26, w21, w20",
         "mrs x20, nzcv",
         "eor w20, w20, #0x20000000",
         "mov x5, x26",
@@ -832,18 +857,18 @@
       ]
     },
     "sbb al, 1": {
-      "ExpectedInstructionCount": 21,
+      "ExpectedInstructionCount": 20,
       "Comment": "0x1C",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxtb w27, w4",
         "cset w21, hs",
         "add w20, w20, w21",
         "sub w20, w27, w20",
         "uxtb w26, w20",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x20, hi",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x22, hs",
         "cmp x21, #0x1 (1)",
         "csel x20, x22, x20, eq",
@@ -853,24 +878,23 @@
         "bic w21, w27, w26",
         "ubfx x21, x21, #7, #1",
         "orr w20, w20, w21, lsl #28",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #8",
         "msr nzcv, x20"
       ]
     },
     "sbb ax, 1": {
-      "ExpectedInstructionCount": 21,
+      "ExpectedInstructionCount": 20,
       "Comment": "0x1D",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxth w27, w4",
         "cset w21, hs",
         "add w20, w20, w21",
         "sub w20, w27, w20",
         "uxth w26, w20",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x20, hi",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x22, hs",
         "cmp x21, #0x1 (1)",
         "csel x20, x22, x20, eq",
@@ -880,7 +904,6 @@
         "bic w21, w27, w26",
         "ubfx x21, x21, #15, #1",
         "orr w20, w20, w21, lsl #28",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #16",
         "msr nzcv, x20"
       ]
@@ -890,7 +913,7 @@
       "Comment": "0x1D",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "mov w27, w4",
         "mrs x21, nzcv",
         "eor w21, w21, #0x20000000",
         "msr nzcv, x21",
@@ -918,25 +941,26 @@
       ]
     },
     "sbb al, -1": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 21,
       "Comment": "0x1C",
       "ExpectedArm64ASM": [
         "mov w20, #0xff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "add w20, w20, w21",
-        "sub w20, w4, w20",
+        "uxtb w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "add w20, w20, w22",
+        "sub w20, w21, w20",
         "uxtb w26, w20",
-        "cmp x26, x4",
+        "cmp w26, w21",
         "cset x20, hi",
-        "cmp x26, x4",
-        "cset x22, hs",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x22, x20, eq",
+        "cmp w26, w21",
+        "cset x23, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x23, x20, eq",
         "cmn wzr, w26, lsl #24",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "bic w21, w26, w4",
+        "mrs x22, nzcv",
+        "orr w20, w22, w20, lsl #29",
+        "bic w21, w26, w21",
         "ubfx x21, x21, #7, #1",
         "orr w20, w20, w21, lsl #28",
         "bfxil x4, x26, #0, #8",
@@ -944,25 +968,26 @@
       ]
     },
     "sbb ax, -1": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 21,
       "Comment": "0x1D",
       "ExpectedArm64ASM": [
         "mov w20, #0xffff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "add w20, w20, w21",
-        "sub w20, w4, w20",
+        "uxth w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "add w20, w20, w22",
+        "sub w20, w21, w20",
         "uxth w26, w20",
-        "cmp x26, x4",
+        "cmp w26, w21",
         "cset x20, hi",
-        "cmp x26, x4",
-        "cset x22, hs",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x22, x20, eq",
+        "cmp w26, w21",
+        "cset x23, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x23, x20, eq",
         "cmn wzr, w26, lsl #16",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "bic w21, w26, w4",
+        "mrs x22, nzcv",
+        "orr w20, w22, w20, lsl #29",
+        "bic w21, w26, w21",
         "ubfx x21, x21, #15, #1",
         "orr w20, w20, w21, lsl #28",
         "bfxil x4, x26, #0, #16",
@@ -970,15 +995,16 @@
       ]
     },
     "sbb eax, -1": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 11,
       "Comment": "0x1D",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffffff",
-        "mvn w27, w4",
-        "mrs x21, nzcv",
-        "eor w21, w21, #0x20000000",
-        "msr nzcv, x21",
-        "sbcs w26, w4, w20",
+        "mov w21, w4",
+        "mvn w27, w21",
+        "mrs x22, nzcv",
+        "eor w22, w22, #0x20000000",
+        "msr nzcv, x22",
+        "sbcs w26, w21, w20",
         "mrs x20, nzcv",
         "eor w20, w20, #0x20000000",
         "mov x4, x26",
diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json
index 750f446f03..e0c54f1147 100644
--- a/unittests/InstructionCountCI/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/PrimaryGroup.json
@@ -37,11 +37,11 @@
       ]
     },
     "adc al, 1": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 19,
       "Comment": "GROUP1 0x80 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxtb w27, w4",
         "cset w21, hs",
         "adc w20, w27, w20",
         "uxtb w26, w20",
@@ -57,24 +57,23 @@
         "bic w21, w26, w27",
         "ubfx x21, x21, #7, #1",
         "orr w20, w20, w21, lsl #28",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #8",
         "msr nzcv, x20"
       ]
     },
     "sbb al, 1": {
-      "ExpectedInstructionCount": 21,
+      "ExpectedInstructionCount": 20,
       "Comment": "GROUP1 0x80 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "uxtb w27, w4",
         "cset w21, hs",
         "add w20, w20, w21",
         "sub w20, w27, w20",
         "uxtb w26, w20",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x20, hi",
-        "cmp x26, x27",
+        "cmp w26, w27",
         "cset x22, hs",
         "cmp x21, #0x1 (1)",
         "csel x20, x22, x20, eq",
@@ -84,7 +83,6 @@
         "bic w21, w27, w26",
         "ubfx x21, x21, #7, #1",
         "orr w20, w20, w21, lsl #28",
-        "mov x4, x27",
         "bfxil x4, x26, #0, #8",
         "msr nzcv, x20"
       ]
@@ -159,24 +157,25 @@
       ]
     },
     "adc al, -1": {
-      "ExpectedInstructionCount": 19,
+      "ExpectedInstructionCount": 20,
       "Comment": "GROUP1 0x80 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0xff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "adc w20, w4, w20",
+        "uxtb w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "adc w20, w21, w20",
         "uxtb w26, w20",
         "cmp w26, #0xff (255)",
         "cset x20, lo",
         "cmp w26, #0xff (255)",
-        "cset x22, ls",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x22, x20, eq",
+        "cset x23, ls",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x23, x20, eq",
         "cmn wzr, w26, lsl #24",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "bic w21, w4, w26",
+        "mrs x22, nzcv",
+        "orr w20, w22, w20, lsl #29",
+        "bic w21, w21, w26",
         "ubfx x21, x21, #7, #1",
         "orr w20, w20, w21, lsl #28",
         "bfxil x4, x26, #0, #8",
@@ -184,25 +183,26 @@
       ]
     },
     "sbb al, -1": {
-      "ExpectedInstructionCount": 20,
+      "ExpectedInstructionCount": 21,
       "Comment": "GROUP1 0x80 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0xff",
-        "mvn w27, w4",
-        "cset w21, hs",
-        "add w20, w20, w21",
-        "sub w20, w4, w20",
+        "uxtb w21, w4",
+        "mvn w27, w21",
+        "cset w22, hs",
+        "add w20, w20, w22",
+        "sub w20, w21, w20",
         "uxtb w26, w20",
-        "cmp x26, x4",
+        "cmp w26, w21",
         "cset x20, hi",
-        "cmp x26, x4",
-        "cset x22, hs",
-        "cmp x21, #0x1 (1)",
-        "csel x20, x22, x20, eq",
+        "cmp w26, w21",
+        "cset x23, hs",
+        "cmp x22, #0x1 (1)",
+        "csel x20, x23, x20, eq",
         "cmn wzr, w26, lsl #24",
-        "mrs x21, nzcv",
-        "orr w20, w21, w20, lsl #29",
-        "bic w21, w26, w4",
+        "mrs x22, nzcv",
+        "orr w20, w22, w20, lsl #29",
+        "bic w21, w26, w21",
         "ubfx x21, x21, #7, #1",
         "orr w20, w20, w21, lsl #28",
         "bfxil x4, x26, #0, #8",
@@ -310,7 +310,7 @@
       "Comment": "GROUP1 0x81 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0x100",
-        "mov x27, x4",
+        "mov w27, w4",
         "adcs w26, w27, w20",
         "mov x4, x26"
       ]
@@ -330,7 +330,7 @@
       "Comment": "GROUP1 0x81 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0x100",
-        "mov x27, x4",
+        "mov w27, w4",
         "mrs x21, nzcv",
         "eor w21, w21, #0x20000000",
         "msr nzcv, x21",
@@ -492,7 +492,7 @@
       "Comment": "GROUP1 0x81 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffff00",
-        "mov x27, x4",
+        "mov w27, w4",
         "adcs w26, w27, w20",
         "mov x4, x26"
       ]
@@ -512,7 +512,7 @@
       "Comment": "GROUP1 0x81 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffff00",
-        "mov x27, x4",
+        "mov w27, w4",
         "mrs x21, nzcv",
         "eor w21, w21, #0x20000000",
         "msr nzcv, x21",
@@ -675,7 +675,7 @@
       "Comment": "GROUP1 0x83 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "mov w27, w4",
         "adcs w26, w27, w20",
         "mov x4, x26"
       ]
@@ -695,7 +695,7 @@
       "Comment": "GROUP1 0x83 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "mov x27, x4",
+        "mov w27, w4",
         "mrs x21, nzcv",
         "eor w21, w21, #0x20000000",
         "msr nzcv, x21",
@@ -854,12 +854,13 @@
       ]
     },
     "adc eax, -1": {
-      "ExpectedInstructionCount": 4,
+      "ExpectedInstructionCount": 5,
       "Comment": "GROUP1 0x83 /2",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffffff",
-        "mvn w27, w4",
-        "adcs w26, w4, w20",
+        "mov w21, w4",
+        "mvn w27, w21",
+        "adcs w26, w21, w20",
         "mov x4, x26"
       ]
     },
@@ -874,15 +875,16 @@
       ]
     },
     "sbb eax, -1": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 11,
       "Comment": "GROUP1 0x83 /3",
       "ExpectedArm64ASM": [
         "mov w20, #0xffffffff",
-        "mvn w27, w4",
-        "mrs x21, nzcv",
-        "eor w21, w21, #0x20000000",
-        "msr nzcv, x21",
-        "sbcs w26, w4, w20",
+        "mov w21, w4",
+        "mvn w27, w21",
+        "mrs x22, nzcv",
+        "eor w22, w22, #0x20000000",
+        "msr nzcv, x22",
+        "sbcs w26, w21, w20",
         "mrs x20, nzcv",
         "eor w20, w20, #0x20000000",
         "mov x4, x26",