diff --git a/unittests/InstructionCountCI/X87store-SVE.json b/unittests/InstructionCountCI/X87store-SVE.json
index d4feba020f..f6052ed39c 100644
--- a/unittests/InstructionCountCI/X87store-SVE.json
+++ b/unittests/InstructionCountCI/X87store-SVE.json
@@ -14,15 +14,14 @@
   },
   "Instructions": {
     "fstp tword [rax]": {
-      "ExpectedInstructionCount": 14,
+      "ExpectedInstructionCount": 13,
       "Comment": "Single 80-bit store.",
       "ExpectedArm64ASM": [
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "mov x0, #0xa",
-        "whilelt p5.b, xzr, x0",
-        "st1b {z2.b}, p5, [x4]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x4]",
         "ldrb w21, [x28, #1298]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
@@ -35,7 +34,7 @@
     },
     "2-store 80bit": {
       "x86InstructionCount": 2,
-      "ExpectedInstructionCount": 27,
+      "ExpectedInstructionCount": 25,
       "x86Insts": [
         "fstp tword [rax]",
         "fstp tword [rax+10]"
@@ -44,9 +43,8 @@
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "mov x0, #0xa",
-        "whilelt p5.b, xzr, x0",
-        "st1b {z2.b}, p5, [x4]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x4]",
         "ldrb w21, [x28, #1298]",
         "mov w22, #0x1",
         "lsl w23, w22, w20",
@@ -58,9 +56,8 @@
         "add x21, x4, #0xa (10)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "mov x0, #0xa",
-        "whilelt p5.b, xzr, x0",
-        "st1b {z2.b}, p5, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w22, w22, w20",
         "bic w21, w21, w22",
@@ -72,7 +69,7 @@
     },
     "8-store 80bit": {
       "x86InstructionCount": 8,
-      "ExpectedInstructionCount": 105,
+      "ExpectedInstructionCount": 97,
       "x86Insts": [
         "fstp tword [rax]",
         "fstp tword [rax+10]",
@@ -87,9 +84,8 @@
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "mov x0, #0xa",
-        "whilelt p5.b, xzr, x0",
-        "st1b {z2.b}, p5, [x4]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x4]",
         "ldrb w21, [x28, #1298]",
         "mov w22, #0x1",
         "lsl w23, w22, w20",
@@ -101,9 +97,8 @@
         "add x21, x4, #0xa (10)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "mov x0, #0xa",
-        "whilelt p5.b, xzr, x0",
-        "st1b {z2.b}, p5, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -114,9 +109,8 @@
         "add x21, x4, #0x14 (20)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "mov x0, #0xa",
-        "whilelt p5.b, xzr, x0",
-        "st1b {z2.b}, p5, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -127,9 +121,8 @@
         "add x21, x4, #0x1e (30)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "mov x0, #0xa",
-        "whilelt p5.b, xzr, x0",
-        "st1b {z2.b}, p5, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -140,9 +133,8 @@
         "add x21, x4, #0x28 (40)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "mov x0, #0xa",
-        "whilelt p5.b, xzr, x0",
-        "st1b {z2.b}, p5, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -153,9 +145,8 @@
         "add x21, x4, #0x32 (50)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "mov x0, #0xa",
-        "whilelt p5.b, xzr, x0",
-        "st1b {z2.b}, p5, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -166,9 +157,8 @@
         "add x21, x4, #0x3c (60)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "mov x0, #0xa",
-        "whilelt p5.b, xzr, x0",
-        "st1b {z2.b}, p5, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
@@ -179,9 +169,8 @@
         "add x21, x4, #0x46 (70)",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "mov x0, #0xa",
-        "whilelt p5.b, xzr, x0",
-        "st1b {z2.b}, p5, [x21]",
+        "ptrue p0.h, vl5",
+        "st1h {z2.h}, p0, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w22, w22, w20",
         "bic w21, w21, w22",