From 2019f8138ef92903c10f9ff470fd56defdc0f892 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Thu, 19 Dec 2024 17:29:45 -0800 Subject: [PATCH] ArchHelpers/Arm64: Fixes LDAPUR and STLUR backpatching The immediate offset masking was at the completely wrong offset when I wrote these handlers. No idea how I managed to mess those up so badly. Should fix at least some of the issues with #4216 --- FEXCore/Source/Utils/ArchHelpers/Arm64.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/FEXCore/Source/Utils/ArchHelpers/Arm64.cpp b/FEXCore/Source/Utils/ArchHelpers/Arm64.cpp index 3dcb392310..526760fd17 100644 --- a/FEXCore/Source/Utils/ArchHelpers/Arm64.cpp +++ b/FEXCore/Source/Utils/ArchHelpers/Arm64.cpp @@ -2118,7 +2118,7 @@ HandleUnalignedAccess(FEXCore::Core::InternalThreadState* Thread, UnalignedHandl LDUR |= Size << 30; LDUR |= AddrReg << 5; LDUR |= DataReg; - LDUR |= Instr & (0b1'1111'1111 << 9); + LDUR |= Instr & (0b1'1111'1111 << 12); if (HandleType != UnalignedHandlerType::NonAtomic) { // Ordering matters with cross-thread visibility! std::atomic_ref(PC[1]).store(DMB_LD, std::memory_order_release); // Back-patch the half-barrier. @@ -2132,7 +2132,7 @@ HandleUnalignedAccess(FEXCore::Core::InternalThreadState* Thread, UnalignedHandl STUR |= Size << 30; STUR |= AddrReg << 5; STUR |= DataReg; - STUR |= Instr & (0b1'1111'1111 << 9); + STUR |= Instr & (0b1'1111'1111 << 12); if (HandleType != UnalignedHandlerType::NonAtomic) { std::atomic_ref(PC[-1]).store(DMB, std::memory_order_release); // Back-patch the half-barrier. }